Prosecution Insights
Last updated: April 19, 2026
Application No. 17/516,847

SUBMOUNT ARCHITECTURE FOR MULTIMODE NODES

Final Rejection §103
Filed
Nov 02, 2021
Examiner
CHIEM, DINH D
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cisco Technology Inc.
OA Round
4 (Final)
72%
Grant Probability
Favorable
5-6
OA Rounds
3y 0m
To Grant
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
388 granted / 535 resolved
+4.5% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
46 currently pending
Career history
581
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
52.8%
+12.8% vs TC avg
§102
35.7%
-4.3% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 535 resolved cases

Office Action

§103
DETAILED ACTION This office action is in response to applicant’s amendment filed on 4/29/2025. Claims 1-7, and 9-21 are under consideration. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 2014/0212093 A1, herein “Lai”) in view of Epitaux et al. (US 7,329,054 B1, herein “Epitaux”) Regarding claim 1, Lai discloses an apparatus (10; Fig. 1 and 2) comprising: a printed circuit board (PCB 100); a substrate (substrate 200) with a finer structuring than the PCB, wherein a bottom surface of the substrate is coupled to the PCB, wherein the substrate includes one or more cavities (hole 222), each cavity including a plurality of side walls and a bottom wall, and the bottom wall of each cavity being spaced from the bottom surface of the substrate by a distance that is smaller than a distance between a top surface of the substrate and the bottom surface of the substrate; electro-optical components (photoelectric dies 300, Para [0017]), each electro-optical component being mounted in cavity of the one or more cavities in the substrate, each electro-optical component being mounted to the substrate at the bottom wall of the cavity, wherein a height of the plurality of side walls of each cavity is greater than or equal to a height of each electro-optical component such that a top surface of each electro-optical component is below or even with the top surface of the substrate (the height of the side walls is greater than the height of photoelectric dies 300), the electro-optical components including one or more optical components arranged to emit optical signals towards and/or receive optical signals from an area above the top surface of the substrate (see ray trace from photoelectric dies 300); a plurality of wire bonds (wires 400), each wire bond connecting a top surface of an electro-optical component of the electro-optical components to the top surface of the substrate such that each wire is flat or spans a vertical distance in each cavity; and an optical transfer assembly (500) mounted over the one or more cavities, the optical transfer assembly including a main body that supports one or more lenses (lenses 520) positioned in the area above the top surface to guide the optical signals emitted from the one or more optical components and/or the optical signals to be received by the one or more optical components, wherein the main body is optically coupled to the one or more fibers for directing the optical signals to or from one or more ports (Para [0010]). PNG media_image1.png 288 430 media_image1.png Greyscale Lai does not explicitly disclose the main body is attached to one or more fibers for directing the optical signals from one or more ports. Epitaux teaches optical fibers (10) are attached to the main body of the optical transceiver module via grooves (18). The fibers held within ferrule (40) is attached to the main body of the optical interconnect module (Fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the side coupled optical fiber as taught by Epitaux would have been modifiable to the device of Lai at the ledge on the fourth layer (240). One motivation for attaching the optical fiber to the main body is for the input and output of optical signals carried by the optical fiber from or to an external source. Claim 2. Lai in view of Epitaux (herein “Lai / Epitaux”) teach the electro-optical components (Epitaux: laser 42 and photodetector 40 in Fig. 7) further comprise an integrated circuit (drivers 46) that is coupled to the top surface of the substrate (16a). Lai / Epitaux do not explicitly teach the integrated circuit (drivers 46) is flip-chip bonded. Epitaux teaches the eletro-optical components (photodetectors 40, laser diodes 42), integrated circuit (trans-impedance amplifiers 44, laser diode drivers 46) reside in multilayered substrate (16). Substrate (16) has the similar construction and materials as substrate 15 (Col. 5, line 62 to Col. 6, line 1). Multilayered substrate (15) comprises layer (15a) includes contact regions 33 for interconnection with an analog integrated circuit (31). The two devices may be coupled using conventional interconnect technology, preferably flip chip bonding (Col. 4, lines 46-64). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple integrated circuit to the top surface of the substrate via flip-chip bonding. One motivation is the passive chip alignment designed into flip-chip bonding technique and the electrical interconnection flip-chip bonding creates in multilayered substrates. Claim 3. Lai / Epitaux teach flip-chip bonding technique wherein optical components of the electro-optical components are connected to electrical components of the electro-optical components via the substrate so that the apparatus does not include chip-to-chip bond wires. The multilayer substrate are electrically interconnected through contact pads and substrate vias (Epitaux: Col. 5, lines 9-20). Claim 11, Lai discloses a method comprising: providing a printed circuit board (PCB 100); mounting a bottom surface of a substrate (substrate 200) with a finer structuring than the PCB to the PCB; mounting electro-optical components (photoelectric dies 300, Para [0017]) within one or more cavities (hole 222) in the substrate, wherein a height of plurality of side walls of each cavity, of the one or more cavities, is greater than or equal to a height of each electro-optical component mounted in each cavity such that a top surface of each electro-optical component is below or even with a top surface of the substrate, the electro-optical components including one or more optical components arranged to emit optical signals towards and/or receive optical signals from an area above a top surface of the substrate (see ray trace from photoelectric dies 300); connecting the top surface of each electro-optical component to the top surface of the substrate with a wire bond (wires 400) such that each wire is flat or spans a vertical distance in each cavity; positioning an optical transfer assembly (500) over the one or more cavities, the optical transfer assembly including a main body that supports one or more lenses (lenses 520) in the area above the top surface of the substrate to guide the optical signals emitted from the one or more optical components and/or the optical signals to be received by the one or more optical components; and wherein the main body is optically coupled to the one or more fibers for directing the optical signals to or from one or more ports (Para [0010]). Lai does not explicitly disclose the main body is attached to one or more fibers for directing the optical signals from one or more ports. Epitaux teaches optical fibers (10) are attached to the main body of the optical transceiver module via grooves (18). The fibers held within ferrule (40) is attached to the main body of the optical interconnect module (Fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the side coupled optical fiber as taught by Epitaux would have been modifiable to the device of Lai at the ledge on the fourth layer (240). One motivation for attaching the optical fiber to the main body is for the input and output of optical signals carried by the optical fiber from or to an external source. Claim 12. Lai in view of Epitaux (herein “Lai / Epitaux”) teach the method of claim 11, wherein electro-optical components (Epitaux: laser 42 and photodetector 40 in Fig. 7) further comprise an integrated circuit (drivers 46) that is coupled to the top surface of the substrate (16a). Lai / Epitaux do not explicitly teach coupling the integrated circuit (drivers 46) via flip-chip bonding. Epitaux discloses the eletro-optical components (photodetectors 40, laser diodes 42), integrated circuit (trans-impedance amplifiers 44, laser diode drivers 46) reside in multilayered substrate (16). Substrate (16) has the similar construction and materials as substrate 15 (Col. 5, line 62 to Col. 6, line 1). Multilayered substrate (15) comprises layer (15a) includes contact regions 33 for interconnection with an analog integrated circuit (31). The two devices may be coupled using conventional interconnect technology, preferably flip chip bonding (Col. 4, lines 46-64). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple integrated circuit to the top surface of the substrate via flip-chip bonding. One motivation is the passive alignment designed into flip-chip bonding technique and the electrical interconnection flip-chip bonding creates in multilayered substrates. Claim 13. Lai / Epitaux teach flip-chip bonding technique wherein optical components of the electro-optical components are connected to electrical components of the electro-optical components via the substrate so that the apparatus does not include chip-to-chip bond wires. The multilayer substrate are electrically interconnected through contact pads and substrate vias (Epitaux: Col. 5, lines 9-20). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lai / Epitaux in view Lai / Epitaux teach the method of claim 13, wherein mounting the electro-optical components within the one or more cavities further comprises: Mounting the one or more optical components (Epitaux: photodetectors 40, laser diodes 42) within the one or more cavities to create a reduced longitudinal gap between one or more tops of the one or more optical components and the top surface of the substrate. Figure 7 of Epitaux shows the apertures provided for the optical components are filled in and rise closers to the top of the surface of multilayer substrate 16 (Fig. 7 replicated below). PNG media_image2.png 446 425 media_image2.png Greyscale Epitaux further teaches in Fig. 5 in implementations where off-shelf devices such as VCSELs and PINs from Emcore Corporation, these devices electrically couple to the analog circuit 31 through wirebonds, contact pads, and substrate vias. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention modify electrical connections as taught by Epitaux in the various embodiments per design specifications. One motivation for providing wirebonds on the top surfaces of the optical devices and the top surface of the substrate is for assembling transceivers that do not have strict design specifications and off shelf devices would be easily incorporated with external wirebonds. PNG media_image3.png 418 466 media_image3.png Greyscale Claim 15. Lai / Epitaux teaches mounting the optical transfer assembly above the one or more optical components (photoelectric dies 300, Para [0017] is in alignment with lens element 500). Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lai / Epitaux as applied to claim 1 above, and further in view of Dubin (US 8,933,473 B1, herein “Dubin”). Lai / Epitaux teach the apparatus of claim 1 and the method claim 11, but Lai / Epitaux do not teach the optical transfer assembly abuts the top surface of the substrate. The Specification discloses the optical transfer assembly “abuts” the top surface of the substrate via the encapsulant seals the cavity and over the cavity it extends such that the encapsulant is a part of the optical transfer assembly; thus “abuts” the top surface of the substrate (Specification Para [0051] and Figs. 5-6). Dubin teaches a transceiver package (100) wherein the electro-optical components are placed in a cavity and an encapsulant (130) fills the cavity (115) such that the encapsulant abuts the top surface of the substrate (Prior Art Fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the cavity of Lai / Epitaux by filling the cavity with encapsulant and leveling it to the top surface of the substrate. One motivation would be to hermetically seal and protect the electro-optical components from physical or environmental damage. Claims 5-7, and 16-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lai / Epitaux as applied to claim 1 above, and further in view of Bettman et al. (US 2020/0144151 A1, herein “Bettman”). Regarding claim 5, Lai / Epitaux teach the apparatus of claim 1, but Lai / Epitaux do not teach the one or more optical components of the electro-optical components dissipate heat along at least a first heat dissipation path and electrical components of the electro-optical components dissipate heat along at least a second heat dissipation path that is distinct form the first heat dissipation path. Bettman teaches thermal management system for an optical transceiver wherein the optical components (Fig. 7C, optical element 28) is mounted on an optical element heat spreader (36). The heat spreader (36) allows the heat to dissipate over the surface area of the heat spreader (36) as seen from top view in Fig. 1A. The electrical components are on IC die (26) dissipate heat along at least a second heat dissipation path that is distinct from the first heat dissipation path through IC heat spreader (34) and through the heat sink (76). See Figs. 10A and 10B). The heat paths are all distinct in that they spread through different bodies (e.g., optical element heat spreader 36, IC heat spreader 34, and heat sink 76). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the supporting substrate with heat dissipating material for the multi-purpose of supporting substrate and heat dissipation . One motivation would be to quickly dissipate heat at different paths to maintain optimal functioning temperature. Regarding claim 6, Bettman further teaches the substrate (substrate body 38, top view shown in Fig. 12B). The substrate (38) is provided with a mounting aperture (50 in Fig. 12C and 12D). The mounting aperture is a thermal void that defines a thermal boundary between the heat spreader (36) whereon the optical element (28) is mounted and heat spreader (34) whereon the IC die (26) is mounted. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the cavity with a void to create a thermal boundary between the IC die and the optical element. One motivation would be to quickly dissipate heat at different paths to maintain optimal functioning temperature while avoiding the thermal energy from the components to blend and create hot spot(s). Regarding claim 7, Bettman further teaches the heat spreader (36) dissipates heat over the top and side surface areas of the spreader. And the IC heat spreader (34) dissipates heat over the top and bottom of the spreader (34). See Figs. 10A and 10B. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the supporting substrate with heat dissipating material for the multi-purpose of supporting substrate and heat dissipation. One motivation would be to quickly dissipate heat at different paths to maintain optimal functioning temperature. Claims 16 and 18. Lai discloses an apparatus (10 in Fig. 2) comprising: a printed circuit board (PCB 100); a substrate (substrate 200) with a finer structuring than the PCB, wherein a bottom surface of the substrate is coupled to the PCB; electro-optical components (photoelectric dies 300, Para [0017]) mounted in one or more cavities (hole 222) of the substrate, wherein a height of a plurality of side walls of each cavity is greater than or equal to a height of each electro-optical component mounted in each cavity such that a top surface of each electro-optical component is below or even with a top surface of the substrate. And Lai discloses a plurality of wire bonds (wires 400), wherein each wire bond connects a top surface of an electro-optical component to a top surface of the substrate, such that each wire is flat or spans a vertical distance in each cavity (Fig. 2). However, Lai does not disclose the one or more electrical components are flip-chip bonded. Epitaux teaches the eletro-optical components (photodetectors 40, laser diodes 42), integrated circuit (trans-impedance amplifiers 44, laser diode drivers 46) reside in multilayered substrate (16). Substrate (16) has the similar construction and materials as substrate 15 (Col. 5, line 62 to Col. 6, line 1). Multilayered substrate (15) comprises layer (15a) includes contact regions 33 for interconnection with an analog integrated circuit (31). The two devices may be coupled using conventional interconnect technology, preferably flip chip bonding (Col. 4, lines 46-64). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple integrated circuit to the top surface of the substrate via flip-chip bonding. One motivation is the passive alignment designed into flip-chip bonding technique and the electrical interconnection flip-chip bonding creates in multilayered substrates. Lai / Epitaux do not teach one or more optical components of the electro-optical components dissipate heat along at least a first heat dissipation path and one or more electrical components of the electro-optical components dissipate heat along at least a second heat dissipation path that dissipates heat in a different direction from the first heat dissipation path. Bettman teaches thermal management system for an optical transceiver wherein the optical components (Fig. 7C, optical element 28) is mounted on an optical element heat spreader (36). The heat spreader (36) allows the heat to dissipate over the surface area of the heat spreader (36) as seen from top view in Fig. 1A. The electrical components are on IC die (26) dissipate heat along at least a second heat dissipation path that is distinct from the first heat dissipation path through IC heat spreader (34) and through the heat sink (76). See Figs. 10A and 10B). The heat paths are all distinct in that they spread through different bodies (e.g., optical element heat spreader 36, IC heat spreader 34, and heat sink 76). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the supporting substrate with heat dissipating material for the multi-purpose of supporting substrate and heat dissipation and heat sink is a well-known thermal management component in optoelectronic modules. One motivation would be to quickly dissipate heat at different paths to maintain optimal functioning temperature. Claim 17. Bettman further teaches a thermal void Bettman further teaches the substrate (substrate body 38, top view shown in Fig. 12B). The substrate (38) is provided with a mounting aperture (50 in Fig. 12C and 12D). The mounting aperture is a thermal void that defines a thermal boundary between the heat spreader (36) whereon the optical element 28 is mounted and heat spreader (34) whereon the IC die (26) is mounted. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the cavity with a void to create a thermal boundary between the IC die and the optical element. One motivation would be to quickly dissipate heat at different paths to maintain optimal functioning temperature while avoiding the thermal energy from the components to blend and create hot spot(s). Claim 19. Bettman further teaches the heat spreader (36) dissipates heat over the top and side surface areas of the spreader. And the IC heat spreader (34) dissipates heat over the top and bottom of the spreader (34). See Figs. 10A and 10B. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the supporting substrate with heat dissipating material for the multi-purpose of supporting substrate and heat dissipation. One motivation would be to quickly dissipate heat at different paths to maintain optimal functioning temperature. Claim 20. Lai / Epitaux teach the apparatus of claim 18, and Epitaux further teaches the heat spreading cap (35) provides a hermetic seal for the integrated circuit (31) with the substrate (Col. 4, lines 65-67). Lai / Epitaux do not explicitly teach the first heat dissipation path extends from one or more bottoms of the one or more cavities. Bettman teaches optical elements (28) are mounted on optical heat spreader (36). Thus, the heat dissipation path extends from one or more bottoms of the one or more cavities. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the supporting substrate with heat dissipating material for the multi-purpose of supporting substrate and heat dissipation. One motivation would be to quickly dissipate heat at different paths to maintain optimal functioning temperature. Claim 21. Lai / Epitaux teaches each cavity of the one or more cavities receives multiple optical components of the one or more optical components (Lai: photoelectric dies 300 has photodiode and laser diodes packaged together, Para [0017]). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lai / Epitaux as applied to claim 1 above, and further in view of Yuen (US 6,583,902 B1, herein “Yuen”). Lai / Epitaux teach the apparatus of claim 1, but Lai / Epitaux do not teach each cavity of the one or more cavities receives a single optical component of the one or more optical components. Yuen teaches an optical transceiver (Fig. 8) wherein the enclosed cavities (41) are provided for individual optoelectronic circuit (13) of a multi-channel transceiver. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Lai / Epitaux by etching multiple cavities to support individual optical components, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179. One motivation would be to provide a transceiver that is capable of processing multiple channels. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lai / Epitaux as applied to claim 1 above, and further in view of Tuominen et al. (US 2021/0243889 A1, herein “Tuominen”). Lai / Epitaux teach the apparatus of claim 1, but Lai / Epitaux do not teach a carrier substrate on which the one or more optical components are mounted within the one or more cavities. Tuominen teaches optical element is assembled onto a component carrier prior to assembling the optical element into a module package, wherein the carrier is preferably laminated layer stack which includes an embedded component such as a sensor component. Such a carrier can be easily assembled and align without the risk of introducing burnt stack material, dirt and dust which may cause malfunctions (Para [0014], [0024], and [0073]). Moreover, a flash phenomenon such as when wirebonding is carried out which may cause the surface to which the optical element is provided with electrical connection may resist electrical bonding. The burned surface must be cleaned before continuing assembly process. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify apparatus of Lai / Epitaux with the carrier for the optical element to be positioned thereon. One motivated would be to avoid burnt stack material from causing poor electrical connections. Response to Arguments Applicant’s arguments with respect to claims 1-7, and 9-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIN D CHIEM/Examiner, Art Unit 2874 /THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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Prosecution Timeline

Nov 02, 2021
Application Filed
Mar 16, 2024
Non-Final Rejection — §103
Jun 11, 2024
Applicant Interview (Telephonic)
Jun 14, 2024
Examiner Interview Summary
Jun 18, 2024
Response Filed
Sep 30, 2024
Final Rejection — §103
Dec 30, 2024
Request for Continued Examination
Jan 02, 2025
Response after Non-Final Action
Jan 25, 2025
Non-Final Rejection — §103
Apr 14, 2025
Applicant Interview (Telephonic)
Apr 16, 2025
Examiner Interview Summary
Apr 29, 2025
Response Filed
Oct 11, 2025
Final Rejection — §103 (current)

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Expected OA Rounds
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Grant Probability
90%
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