Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detail Action
This office action is in response to RCE filed on 12/26/2025.
Claims 1, and 3-11, 13-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 11, and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt, (US 2018/0357743 A1) in view of Mathur et al. (US 2009/0251475 Al)
Per claim 1,
Uhrenholt discloses
a central processing unit (CPU), the CPU is configured to run a high-level application; (Fig. 1, see system CPU, [0100-0101], see CPU, GPU under control of CPU via API calls, to execute an application 106)
a highly parallel processing Unit (HPPU) communicatively coupled to the CPU, wherein the HPPU includes an array of at least hundreds of parallel processing cores, ([0069], see graphic processor may comprise any desired and suitable programmable processing circuitry or cores. A desired number of cores to process intensive tasks can be scaled to at least hundreds.; [0019], see executing operations in parallel using processing cores; Fig. 1, HPPU (GPU) is communicatively coupled to CPU 102.)
and wherein the CPU calls the HPPU for execution of highly computational intensive tasks of the high-level application in parallel, ([0018], see executing operations in parallel)
Uhrenholt does not, however, Mathur discloses
a library of low-level graphics codes written in a low-level programming language using native APIs, wherein the library is integrated as part of the HPPU and is specific for the array of parallel processing cores of the HPPU; (HPPU/GPU, Fig. 2,204a-f for low level libraries; also see [0027], [0069], low-level libraries implemented on GPUs and since the low-level libraries is implemented on GPUs, the low-level libraries are considered part of the GPU and integrated and since the low-level libraries are implemented on GPUs, it is considered specific for the array of parallel processing core.; [0086], Fig. 5, GPU framework ; [0070], disclosed raster low-level library in one interpretation corresponds to native API, where raster low-level library can be directly accessed by GPU)
wherein the library of low-level graphics codes enables the HPPU to execute the tasks of the high-level application ([0063], see parallel tasks; [0069]-[0071],see GPU-accelerated image processing using capacities of specific library implemented on GPUs)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Mathur into the teachings of Uhrenholt to include the limitation disclosed by Mathur. The modification would be obvious to one of ordinary skill in the art to want to use Mathur to enable implementation of match capability low-level library code on GPU to process various tasks in order to render high-quality rendering as suggested by Mathur [0070])
Per claim 4, the rejection of claim 3 is incorporated;
Uhrenholt/Mathur discloses
the low-level programming language of the graphics codes comprises Vulkan. (Uhrenholt, [0133], see compiling higher level skeleton program expressions into the lower level skeleton program instructions…written in Vulkan)
Per claim 5, the rejection of claim 1 is incorporated;
Uhrenholt/Mathur discloses
wherein at least hundereds of processing cores of the array of processing cores comprises thousands of processing cores. (Uhrenholt, [0069], see any desired cores corresponding to thousands as scaled as needed.)
Per claim 11,
Uhrenholt/Mathur discloses
running the high-level software application by a central processing unit (CPU); (Fig. 1, see system CPU, [0100-0101], see CPU, GPU under control of CPU via API calls, to execute an application)
calling a graphics processing unit (GPU) which is directly coupled to the CPU comprising an array of at least hundreds of parallel processing cores and executing the highly intensive computational tasks of the software application in parallel by array of at least hundred of parallel processing cores using the graphics codes; ([0069], see graphic processor may comprise any desired and suitable programmable processing circuitry or cores. A desired number of cores to process intensive tasks can be scaled to at least hundreds; [0019], see executing operations in parallel using processing cores)
and
returning results of the highly intensive computational tasks to the CPU. ([0100], see GPU under control of CPU to perform computer operations in response to API calls. [0128], see [0128], see GPU generating desired graphic output)
Uhrenholt does not, however, Mathur discloses
An integrated Libraries of low-level graphics codes written in a low-level programming language; wherein the integrated library is part of the GPU (Fig. 2,204a-f for low level libraries; also see [0027], [0069], low-level libraries implemented on GPUs; [0086], Fig. 5, GPU framework, and since the low-level libraries is implemented on GPUs, the low-level libraries are considered part of the GPU and integrated. ; [0086], Fig. 5, GPU framework )
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Mathur into the teachings of Uhrenholt to include the limitation disclosed by Mathur. The modification would be obvious to one of ordinary skill in the art to want to use match capability low-level library code to processing various tasks in order to render high-quality image as suggested by Mathur [0070])
Per claim 14, see rejection of claim 4.
Per claim 15, see rejection of claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt, (US 2018/0357743 A1) in view of Mathur et al. (US 2009/0251475 Al) and further in view of Hania et al. (US 2020/0183698 A1)
Per claim 3, the rejection of claim 1 is incorporated;
Uhrenholt/Marthur does not, however,
Hania discloses
wherein the array of processing cores comprises Compute Unified Device Architecture (CUDA) cores. ( [0029],see CUDA processing cores.)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Hania into the teachings of Uhrenholt/Marthur to include the limitation disclosed by Hania. The modification would be obvious to one of ordinary skill in the art to want to reduce or eliminate bottleneck as suggested by Hania ([0028])
Per claim 13, see rejection of claim 3.
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt, (US 2018/0357743 A1) in view of Mathur et al. (US 2009/0251475 Al) and further in view of Tian et al. (US 2019/0286479 A1).
Per claim 6, the rejection of claim 1 is incorporated;
Uhrenholt/Mathur discloses
wherein the execution of the highly computational intensive tasks is accelerated by thousands running on processing cores of the GPU (Uhrenholt , [0069], see graphic processor may comprise any desired and suitable programmable processing circuitry or cores. A desired number of cores to process intensive tasks can be scaled to thousands as desired. [0019], executing many operations corresponding to threads using many cores. )
Uhrenholt/Marthur does not specifically disclose
Parallel threads on processing cores;
However, Tian discloses
Parallel threads on processing cores ( [0027], see array of processor cores or parallel processors, each execute a number of parallel threads.)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Tian into the teachings of Uhrenholt/Marthur to include the limitation disclosed by Tian. The modification would be obvious to one of ordinary skill in the art to want to accelerate processing of visual media and parallel computing tasks as suggested by Tian([0002])
Per claim 16, see rejection of claim 6.
Claim(s) 7-10 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uhrenholt, (US 2018/0357743 A1) in view of Mathur et al. (US 2009/0251475 Al) and further Olgiati et al. (US 10891525 B1)
Per claim 7, the rejection of claim 1 is incorporated;
Uhrenholt/Mathur does not specifically disclose, however, Olgiati discloses
the graphics codes are for performing heavy intensive computational computer vision tasks. (c11:4-11, see computer vision, for example, image processing and machine learning are considered heavy intensive tasks.)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Olgiati into the teachings of Uhrenholt/Mathur to include the limitation disclosed by Olgiati. The modification would be obvious to one of ordinary skill in the art to want to use GPU/CPU for analyzing images using computer vision to assist decision making as suggested by Olgiati (C2:40-50)
Per claim 8, the rejection of claim 7 is incorporated;
Uhrenholt/Mathur/Olgiati discloses
wherein the heavy intensive computational computer vision tasks includes classification, objection detection, 3D computer graphics and modeling tasks. (Olgiati, C11: 4-22, computer vision, see recognize the object, 3D graphics, and shape modeling (corresponding to modeling tasks; C4: 20-30, classified as dog discloses classification and objection detection.)
Per claim 9, the rejection of claim 4 is incorporated;
Uhrenholt/Mathur does not specifically disclose, however, Olgiati discloses
the graphics codes are for performing heavy intensive computational computer vision tasks. (c11:4-11, see computer vision, for example, image processing and machine learning are considered heavy intensive tasks.)
Therefore, it would have been obvious to a person of ordinary skill before the effective filing date of the invention to incorporate the teachings of Olgiati into the teachings of Uhrenholt/Mathur to include the limitation disclosed by Olgiati. The modification would be obvious to one of ordinary skill in the art to want to sue GPU/CPU for analyzing images using computer vision to assist decision making as suggested by Olgiati (C2:40-50)
Per claim 10, the rejection of claim 9 is incorporated;
Uhrenholt/Mathur/Olgiati discloses
wherein the heavy intensive computational computer vision tasks includes classification, objection detection, 3D computer graphics and modeling tasks. (Olgiati, C11: 4-22, computer vision, see recognize the object, 3D graphics, and shape modeling (corresponding to modeling tasks; C4: 20-30, classified as dog discloses classification and objection detection.)
Per claims 17-20, see rejections of claims 7-10.
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
Claims have been amended to substitute “GPU” with “HPPU” and “directly connected to” with “communicatively coupled to”. GPU and HPPU are used interchangeably in this context.
Applicant argues –
(Per remark page 7), Applicant argues “the portable framework is not part of the GPU (or HPPU) Instead, the framework is disposed between the CPU and GPU.”
It appears applicant argues the Framework of Mathur is not part of a GPU/HPPU. Examiner agrees that the Framework by itself is not part of GPU/HPPU, however, framework enables/provides implementation of low-level library on GPU/HPPU. The Framework of Mathur enables/provides low-level library to be implemented on GPU/HPPU as disclosed in Mather, [0069-0070]
Mathur [0069] specifically discloses “the low-level libraries are implemented on GPUs” appears to disclose “GPU/HPPU includes…a library of low-level graphics code written in low-level programming language;” Similarly, [0070], appears to disclose the framework enables CPU working with GPU implementing graphics low-level library on GPU.
One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., Inc., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The rejection is based on combination of Uhrenholt and Mathur. Applicant’s argument appears to be focused on the Marthur’s framework is not part of the GPU and disregard the rejection is based on combination of two prior art.
B.(remark page 8), the rejection of claim 1 based on Uhrenholt and Mathur has no motivation to combine.
The rejection of claim 1 clearly articulates the reason for combining Uhrenholt and Mathur. Mathur’s Framework enables GPU/HPPU to implement low-level graphics codes for various types of specialized graphics processing, including Gk-GPU, IL-GPU, etc., (see Mathur paragraphs 69-70) and results in high-quality rendering. The Mathur’s framework may not directly disclose low-level graphics codes as part of the GPU/HPPU. However, Mathur’s framework enables the implementation of low-level graphics code as part of the GPU/HPPU.
Further, Mathur [0069] specifically discloses “the low-level libraries are implemented on GPUs” appears to disclose “GPU/HPPU includes…a library of low-level graphics code written in low-level programming language;” Similarly, [0070], appears to disclose the framework enables CPU working with GPU implementing graphics low-level library on GPU. Mathur does not appear to teach away or criticize low-level libraries implemented on GPU. On the contrary, it discloses such.
The modification would be obvious to one of ordinary skill in the art to want to use capability matching low-level library code to process various tasks in order to render high-quality image as suggested by Mathur [0070])
Arguments related to claims 3, 13, 6, 16, 7-10 and 17-20 appears to base on similar arguments related to claims 1 and 11 and are not convincing as reasoned above.
For reasons above, rejections to argued claims are maintained.
Note to Applicant— there are three RCEs in the prosecution. Examiner understands the applicant intents to claim the “integrated library” as part of GPU. However, for a library to be part of a GPU can be achieved in different ways. An integrated library of GPU can be initially outside of an GPU and then uploaded to the GPU memory, or the library can be “burned in” to integrate when the GPU is manufactured. It appears the intent is to claim the later, however, the claim language does not limit to the later.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
It is noted that any citation [[s]] to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. [[See, MPEP 2123]]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Wang whose telephone number is 571-272-5934. The examiner can normally be reached on Monday – Friday 8:00AM -4:00PM. Any inquiry of general nature or relating to the status of this application should be directed to the TC2100 Group receptionist: 571-272-2100.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock, can be reached at 571-272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHILIP WANG/Primary Examiner, Art Unit 2199
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