DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The rejections from the Office Action of 12/9/2025 are hereby withdrawn. New grounds for rejection are presented below.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/9/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6, 7, 10-12, 15, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (US 20120310569 A1)[hereinafter “Fan”], Bonaccio et al. (US 5706222 A)[hereinafter “Bonnacio”], Sheng et al. (US 20100117878 A1)[hereinafter “Sheng”], Leyendecker at al. (US 20120049655 A1)[hereinafter “Leyendecker”], Jonsson et al. (US 20100321216 A1)[hereinafter Jonsson], and Underwood (US 4782324 A).
Regarding Claims 1, 11, and 19, Fan discloses a method (and corresponding computer/meter including sensor, sensing circuitry, processor or processing unit, and memory) of processing power signals [Paragraph [0018] – “The present invention provides systems, methods, and apparatus for measuring the fundamental frequency of single-phase and poly-phase power line signals and other signals.”] comprising:
receiving, at an analog to digital converter (ADC)[Paragraph [0024] – “In Step 204, the A/D converter 104 sampling frequency, f.sub.ad, is adjusted to f.sub.ad=n.times.f.sub.m. In Step 206, the DSP 106 reads in N samples of v.sub.ref, where N is an integer multiple of n, such as N=640 when n=64.”], an analog poly-phase signal [Fig. 2, steps 204/206. See Paragraph [0024].] associated with power delivered using alternating current (AC)[Paragraph [0024] – “In the US, 60 Hz is the nominal frequency of the power network and in the EU, 50 Hz is the nominal frequency.”], the analog poly-phase signal having at least one current component [Inherent, see Paragraph [0018] – “The present invention can also be used to synchronize voltage/current sampling to power line fundamental frequency so that DFT/FFT and RMS calculations may be performed on full cycles of data to ensure at least +/-0.1% measurement accuracy of voltage RMS and current RMS.”] and at least one voltage component comprising a reference voltage component [Paragraph [0024] – “Since there are no significant differences among fundamental frequencies of voltage channels of a poly-phase public power network, frequency may be measured on any one of the voltage channels. The selected channel is called v.sub.ref. A user may also select to use either a LL voltage or a LN voltage. In Step 204, the A/D converter 104 sampling frequency, f.sub.ad, is adjusted to f.sub.ad=n.times.f.sub.m. In Step 206, the DSP 106 reads in N samples of v.sub.ref, where N is an integer multiple of n, such as N=640 when n=64.”];
converting, using the ADC, the analog poly-phase signal to a digital poly-phase signal sampled at a first sampling rate [Paragraph [0024] – “In Step 204, the A/D converter 104 sampling frequency, f.sub.ad, is adjusted to f.sub.ad=n.times.f.sub.m. In Step 206, the DSP 106 reads in N samples of v.sub.ref, where N is an integer multiple of n, such as N=640 when n=64.”];
detecting, using a fundamental frequency detector, a fundamental frequency of the analog poly-phase signal based on the digital poly-phase signal [Paragraph [0032] – “Flow continues to Step 228 where the fundamental frequency f.sub.m is determined”], wherein the fundamental frequency detector comprises a band-pass filter [Fig. 3, step 212A which feeds into step 214.] and a zero-crossing detector [See Fig. 2, steps 214/218 as described in Paragraphs [0027]-[0030].];
determining, by a sampling rate converter, a second sampling rate [Paragraph [0033] – “To improve the accuracy of the method 200 further, the process may be repeated using the above-calculated value of the fundamental frequency f.sub.m to adjust the A/D converter 104 sampling rate instead of using the nominal frequency.”Paragraph [0024] – “In Step 204, the A/D converter 104 sampling frequency, f.sub.ad, is adjusted to f.sub.ad=n.times.f.sub.m. In Step 206, the DSP 106 reads in N samples of v.sub.ref, where N is an integer multiple of n, such as N=640 when n=64.”], wherein the second sampling rate is set according to
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[Paragraph [0024] – “In Step 204, the A/D converter 104 sampling frequency, f.sub.ad, is adjusted to f.sub.ad=n.times.f.sub.m. In Step 206, the DSP 106 reads in N samples of v.sub.ref, where N is an integer multiple of n, such as N=640 when n=64.”], where Fs is the second sampling rate [f.sub.ad], FL is the fundamental frequency [f.sub.m], NLC is a maximum integer number of cycles in a predetermined time period [Paragraph [0024] – “When the sampling is synchronized to the line frequency, integer "m" will be the number of full cycles where m=N/n.” Fan teaches the integer “m” as taking the form of a multiplier for the calculated sampling rate; exactly the same as the recited “NLC” for a sampling period.], and where m is a positive integer [The “little n” parameter being 64, which is of the form 2^6 where the recited exponent “m” would be the integer “6.”];
resampling the digital poly-phase signal at the second sampling rate [The process of Fig. 2 being an iterative loop where the sampling rate is modified in response to a freshly determined f.sub.m.];
calculating, by a metering measurement calculator, one or more measurements based on the updated frequency-domain signal [Paragraph [0032] – “Flow continues to Step 228 where the fundamental frequency f.sub.m is determined”]; and
determining an energy consumption based on the one or more measurements [Paragraph [0043] – “the present invention instead first determines the fundamental power line frequency using the method 200 and circuit 100 described above. Then a sampling clock signal generated based on the determined fundamental power line frequency is supplied to the A/D converter used to sample the power line for measuring voltage RMS, current RMS, calculating DFTs, or calculating FFTs.”Paragraph [0018] – “The present invention also provides systems, methods, and apparatus to synchronize voltage and current sampling to power line frequency so that subsequent root mean square (RMS) or Digital Fourier Transform/Fast Fourier Transform (DFT/FFT) calculations are performed on data representing full power cycles to improve measurement accuracy of voltage RMS, current RMS, power, and energy.”Method 200 is performed to determine the fundamental frequency, FFT is then performed, and then power and energy measurements are determined.].
Fan fails to disclose detecting by a peak voltage detector, peaks of the at least one voltage component of the digital poly-phase signal and performing the process when the peaks are at or above a voltage threshold because Fan evaluates signal frequency based on zero-crossings [Abstract – “calculating a fundamental frequency of the signal based on the first number of full cycles sampled and the relative position of the first and last zero-crossings.”].
However, Bonnacio discloses evaluating a sinusoidal signal using thresholds to determine peak locations [See Figs. 2A/2B]. It would have been obvious to use such threshold to determine peaks and/or troughs in the AC signal as part of determining signal frequency because doing so would have allowed for an effective manner of identifying the timings of corresponding signal positions. By definition [Merriam-Webster, “frequency” – “the number of times that a periodic function repeats the same sequence of values during a unit variation of the independent variable”], timings of corresponding signal positions establish signal frequency.
Fan discloses for each cycle of the resampled digital poly-phase signal: transforming the resampled digital poly-phase signal to a frequency-domain signal using Fast Fourier Transformation (FFT)[See Paragraph [0043]], but fails to disclose:
calculating a phase angle of the reference voltage component based on the frequency-domain signal;
adjusting the resampled digital poly-phase signal by compensating the calculated phase angle of the reference voltage component; and
transforming the adjusted resampled digital poly-phase signal to an updated frequency-domain signal using FFT.
However, Sheng discloses a phase error correction scheme where calibration FFTs are performed on data from ADCs in order to adjust ADC timings to correct for phase angle errors present in the signal [See Abstract, Figs. 2 and 5, and Paragraphs [0012]-[0015]]. It would have been obvious to perform such a phase angle error correction of the reference voltage component prior to the FFT analysis of Fan in order to reduce the effects of phase angle error on the results of the frequency domain analysis.
Fan fails to disclose that when the peaks are below the voltage threshold, the peak voltage detector generates a switch off signal to disable the fundamental frequency detector.
However, Leyendecker discloses a circuit that monitors voltage [See Fig. 2 and Paragraph [0019] – “sense element 10 for sensing a voltage drop across the resistor”] relative to a threshold for determining whether to put another device in power save mode [See Fig. 2 and Paragraph [0018] – “The power save control B comprises further a threshold circuit 12 coupled to the current sense element 10, for switching the operating voltage VDD for the modem C off, when the supply current for the appliance is below a threshold value, and for switching the operating voltage VDD for the modem C on, when the supply current is above a threshold value.”].
It would have been obvious to utilize such an approach and switch the fundamental frequency detector off when the peaks are below the threshold voltage in order to save power.
Fan fails to disclose up-sampling the digital poly-phase signal by a factor of L, L being an integer; and down-sampling the up-sampled digital poly-phase signal by a factor of M, wherein M = LFADC/Fs, where Fs is the second sampling rate, and FADC is the first sampling rate.
However, Jonsson teaches up-sampling the digital poly-phase signal by a factor of L, L being an integer; and down-sampling the up-sampled digital poly-phase signal by a factor of M, wherein M = LFADC/Fs, where Fs is the second sampling rate, and FADC is the first sampling rate (Para 6, “FIG. 1 illustrates a typical rate conversion system using a traditional rate converter for a rational rate conversion. In this example, the output is sampled at a rate of L/M times the input sampling rate. The input is signal is first up sampled to the least common multiple of the input and output sampling rate by up sampler 102. Up sampler 102 typically inserts zeroes between the input samples to increase the sampling rate in a process known as zero-padding. This converts the input signal to an up sampled signal at L times the sampling rate. The up sampled signal is then filtered using filter 104 which is a usually a low pass filter. The filter smoothers out the up sampled signal and also prevents aliasing from the down sampling process which is performed by down sampler 106. Typically, down sampler 106 uses decimation to convert from the higher intermediate rate to the lower output rate. The result is a signal that has been down sampled by a factor of M or a total rate change by a factor of L/M”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement up sampling and down sampling as taught by Jonsson into the poly phase filter of Ko since the technique of Jonsson is applied on poly phase filter. Therefore, this technique of sampling technique for poly phase filter facilitate the efficient and low complexity solution for rate conversion.
Fan discloses that the detecting the fundamental frequency comprises: applying the poly-phase digital signal to the band-pass filter having a passband [Fig. 3, step 212A which feeds into step 214.]; detecting two adjacent zero-crossings; and calculating the fundamental frequency based on the two adjacent zero-crossings [See Fig. 2, steps 214/218 as described in Paragraphs [0027]-[0030].].
Fan fails to disclose that the band-pass filter is a 8th order elliptic biquadratic band-pass filter. However, Underwood discloses the use of such a filter [Column 6 lines 10-15 and 59-65. Column 9 lines 25-29 – “It is to be understood that the present invention contemplates the cascading of simple interpolator sections having similar pass band/stop band transition characteristics. The interpolators used in the present invention should have very sharp transition regions.”]. It would have been obvious to use such a filter as the filter of Fan because this is a known type of filter.
Regarding Claims 2 and 12, Fan discloses that the analog poly-phase signal is a three-phase power signal [Paragraph [0021] – “The example in FIG. 1 depicts three phase voltage lines inputting analog AC voltage signals to the voltage step down circuit 102 which are output the A/D converter 104.”], and the reference voltage component is a phase A line voltage [Paragraph [0024] – “Since there are no significant differences among fundamental frequencies of voltage channels of a poly-phase public power network, frequency may be measured on any one of the voltage channels. The selected channel is called v.sub.ref. A user may also select to use either a LL voltage or a LN voltage.”].
Regarding Claim 4, Fan discloses that the passband is centered at the recited range [Paragraph [0026] – “The band pass filter may be designed to have, for example, a center frequency f.sub.c of 55 Hz”], but fails to explicitly disclose that the passband is from 50 Hz to 60 Hz. However, it would have been obvious to narrow the passband as recited as a design choice to filter out noise lying too far outside of the center frequency.
Regarding Claims 6 and 15, Underwood discloses that the 8th order elliptic biquadratic band-pass filter comprises four biquadratic filters in cascade [See the cascade arrangement of Fig. 6].
Regarding Claims 7, 16, and 20, Fan discloses that the determining the second sampling rate comprises: setting the second sampling rate as an integer multiple of the fundamental frequency [Paragraph [0024] – “In Step 204, the A/D converter 104 sampling frequency, f.sub.ad, is adjusted to f.sub.ad=n.times.f.sub.m. In Step 206, the DSP 106 reads in N samples of v.sub.ref, where N is an integer multiple of n, such as N=640 when n=64.”].
Regarding Claims 10 and 18, the application of the teachings of Jonsson to the context of Fan would disclose that the up-sampling and the down-sampling is by using a poly-phase resampler comprising a poly-phase filter bank [Performing the up-sampling/down-sampling process of Jonsson when resampling each of the three-phase input signals of Fan].
Response to Amendment
Applicant argues:
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Examiner’s Response:
The Examiner respectfully disagrees. The filter of Underwood would allow for noise filtering as it is a band pass filter [Column 9 lines 25-29 – “It is to be understood that the present invention contemplates the cascading of simple interpolator sections having similar pass band/stop band transition characteristics. The interpolators used in the present invention should have very sharp transition regions.”]. No improper hindsight is present; rather, proper consideration of the state of the prior has been performed. Underwood is analogous art as Underwood provides a signal filter suitable for use in the same field of endeavor as the instant Invention (signal processing) and that solves the same problem in the same way (bandpass filtering).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 6130531 A – Phase Angle Measurement Method And System In Electric Power Systems
US 8847576 B1 – Phase Compensation Method And Apparatus For Current Transformers
US 6081768 A – Digital Peak Detector
US 20110291695 A1 – MONITORING DEVICE FOR AN ELECTRIC POWER SYSTEM
US 20120293144 A1 – VOLTAGE/CURRENT CONTROL APPARATUS AND METHOD
US 20070159217 A1 – Power Down Detection Circuit
US 5321350 A – Fundamental Frequency And Period Detector
US 5103675 A – Signal Detector And Method For Detecting Signals Having Selected Frequency Characteristics
US 8970254 B1 – Systems And Methods For Frequency Detection
US 9510401 B1 – Reduced Standby Power In An Electronic Power Control System
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE ROBERT QUIGLEY whose telephone number is (313)446-4879. The examiner can normally be reached 9AM-5PM EST.
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/KYLE R QUIGLEY/Primary Examiner, Art Unit 2857
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