DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/09/2026 has been entered.
Response to Amendment
The Amendment filed March 09, 2026 has been entered. Currently, claim 1 has been amended, claim 21 has been newly added, and claims 1-16, 18-21 are pending in the application. Examiner notes that although claims 19-20 have been labeled as new, these sets of claims have been previously presented in the claims filed on 10/28/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 16, 18-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (U.S. Patent No. 9173583 B2).
Regarding independent claim 1, Chen discloses an electrode arrangement (1) (Col. 2, lines 64-67 – Col. 3, lines 1-4 & Figs 1-4), comprising:
a semiconductor carrier substrate (11) having a first side surface (111) and a second side surface (112) opposite to the first side surface (Col. 3, lines 5-7);
a first array of electrodes (24) arranged above the first side surface (Col. 3, lines 57-60);
a second array of electrodes (38) arranged below the second side surface (Col. 3, lines 61-65);
an electronic circuitry (12) for processing electrical signals (via a plurality of electrical elements 121 which includes complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical systems (MEMS)) recorded by the first array of the electrodes and the second array of electrodes (Col. 3, lines 8-23), said electronic circuitry comprising at least one layer arranged above the first side surface and below the first array of electrodes (see Fig. 4A);
a connecting layer (combination of first protection layer 18 and second protection layer 22) (Col. 3, lines 47-60) arranged above the at least one layer of the electronic circuitry (see Figs. 3, 4A), said connecting layer being configured to connect the electrodes of the first array and the electrodes of the second array to the electronic circuitry (Col. 3, lines 47-60), wherein the connecting layer is configured to provide a first connection in a plane of the connecting layer between a first point (see annotated Figs. 1 and 3 below) and a second point (see annotated Fig. 1) for connecting an electrode in the second array to the electronic circuitry (Col. 3, lines 44-51). Examiner notes that the first point and the second point include portions of a first redistribution layer 16 that surrounds/encapsulates pad 124 as well as the pad itself;
a first interconnect (122, specifically the one located on the right side of the electrode arrangement as seen in the annotated Fig. 3 below) for electrically connecting the first point to the electronic circuitry (Col. 3, lines 19-23);
a plurality of through-substrate vias TSVs (14), extending completely through the semiconductor carrier substrate between the first side surface and the second side surface for forming an electrical connection through the semiconductor carrier substrate (Col. 3, lines 29-43);
a second interconnect (122, specifically the one located on a left side of the first interconnect as seen in the annotated Fig. 1 below) extending through a plane defined by the at least one layer of the electronic circuitry, wherein the second interconnect and a first TSV (see annotated Fig. 1 below) of the plurality of TSVs electrically connect the second point to the electrode in the second array (see Fig. 1).
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Regarding claim 2, Chen discloses wherein the connecting layer is configured to provide a second connection in a plane of the connecting layer between a third point and a fourth point (see annotated Fig. 1 below) for connecting an electrode in the first array to the electronic circuitry (Col. 3, lines 44-51; Examiner notes that the third point and the fourth point include portions of a first redistribution layer 16 that surrounds/encapsulates pad 124 as well as the pad itself), the electrode arrangement further comprising a third interconnect (see annotated Fig. 1 below) for electrically connecting the third point to the electronic circuitry (Col. 3, lines 19-23), a fourth interconnect (see annotated Fig. 1 below) for connecting the fourth point to a second TSV (see annotated Fig. 1 below) of the plurality of TSVs, a fifth interconnect (20, see annotated Fig. 1 below) for connecting the electrode in the first array to a third TSV (see annotated Fig. 1 below) of the plurality of TSVs (Col. 3, lines 51-60), and a bridging structure (combination of isolation layer 36 and portions of a conductive material of the second array of electrodes that are situated between disconnected portions of the isolation layer as seen by the arrow in annotated Fig. 3 below) arranged at the second side surface for connecting the second TSV to the third TSV (Col. 3, line 67 – Col. 4, lines 1-11).
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Regarding claim 3, Chen discloses wherein the connecting layer is configured to provide a second connection in a plane of the connecting layer between a third point and a fourth point (see annotated Fig. 1 below claim 2) for connecting an electrode in the first array to the electronic circuitry (Col. 3, lines 44-51; Examiner notes that the third point and the fourth point include portions of a first redistribution layer 16 that surrounds/encapsulates pad 124 as well as the pad itself), the electrode arrangement further comprising a third interconnect (see annotated Fig. 1 below claim 2) for electrically connecting the third point to the electronic circuitry (Col. 3, lines 19-23), and a fourth interconnect (see annotated Fig. 1 below claim 2) for connecting the electrode in the first array to the fourth point.
Regarding claim 5, Chen discloses a neural probe, said neural probe comprising the electrode arrangement according to claim 1, wherein the semiconductor carrier substrate is adapted for being inserted into a brain (Col. 2, lines 64-67 – Col. 3, lines 1-4).
Regarding claim 16, Chen discloses wherein the electrode arrangement comprises a plurality of connections for connecting a plurality of electrodes in the second array of electrodes to the electronic circuitry (see Fig. 1), wherein the first connection is part of a plurality of first connections, the first interconnect is part of a plurality of first interconnects, and the second interconnect is part of a plurality of second interconnects (in the manufacturing process of the electrode arrangement, a wafer 10 is diced to form a plurality of neural sensing devices that encompass the electrode arrangement, leading to a plurality of the connections and the interconnects found in the electrode arrangement; Col. 8, lines 29-33 & Fig. 21), wherein each connection for connecting an electrode in the second array of electrodes to the electronic circuitry comprises a separate first connection of the plurality of first connections, a separate first interconnect of the plurality of first interconnects, a separate TSV of the plurality of TSVs, and a separate second interconnect of the plurality of interconnects (see annotated Fig. 1 below claim 1).
Regarding claim 18, Chen discloses further comprising a barrier structure (44) arranged above the first array of electrodes (Col. 8, lines 29-33 & Fig. 21).
Regarding claim 19, Chen discloses wherein each TSV extends through the semiconductor carrier substrate at least from the first side surface to the second side surface (see Fig. 1).
Regarding claim 20, Chen discloses wherein the first interconnect is directly connected to the first point and the second interconnect is directly connected to the second point (Col. 3, lines 19-23 & Fig. 1).
Regarding claim 21, Chen discloses wherein the semiconductor carrier substrate is a single layer (see Fig. 4A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 1, and further in view of Sekitani (U.S. Application No. 20150276430 A1).
Regarding claim 4, Chen discloses the invention substantially as claimed in claim 1 discussed above.
However, Chen does not disclose a back-end-of-line capacitance structure formed at the second side surface between the second array of electrodes and the semiconductor carrier substrate.
Sekitani , in the same field of endeavor, teaches a signal detection device comprising a back-end-of-line capacitance structure (102) (pa. 0041-0042).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the capacitance structure taught by Sekitani, to the electrode arrangement structure of Chen, specifically at the second side surface of the semiconductor carrier substrate, for the purpose of storing electrical energy, blocking direct current (DC), and filtering noise.
Response to Arguments
Applicant’s arguments, see pages 9-11, filed 03/09/2026, with respect to the 103 rejection of claim 1 under Sekitani in view of Rickert have been fully considered and are persuasive. Specifically, Applicant’s amendments to claim 1 to further require the TSVs to completely extend through the semiconductor carrier substrate is defined over Sekitani and Rickert given that they do not contemplate this claimed structure. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chen (U.S. Patent No. 9173583 B2). It is the Examiner’s position that the newly filed rejections based on the new references are tenable for at least the reasoning set forth in the action above.
Conclusion
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/A.V.G./Examiner, Art Unit 3794 /Ronald Hupczey, Jr./Primary Examiner, Art Unit 3794
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