DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/30/2025 has been entered.
Response to Arguments
Prior Art Rejections
Applicant’s arguments, filed 10/30/2025, with respect to the rejections under 35 USC 103 have been fully considered. The combination of Botimer/Shao/Mills does not clearly show “wherein each data subset of the plurality of data subsets comprises a plurality of pairs of data, wherein the plurality of pairs of data comprises different pixel values and different weight values”, as asserted by Applicant. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art references.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Constantin et al. (EP 3674982 A1, hereinafter “Constantin”) in view of Shao et al. (US 20200293867 A1, hereinafter “Shao”), in further view of Martin et al. (US 20190138567 A1, hereinafter “Martin”).
As per claim 1, Constantin teaches A computing device, comprising: an arithmetic circuit, (Constantin: Fig. 3, elements 11, 13; wherein the combination of elements 11 and 13 corresponds to the data reuse circuit), coupled to a plurality of dot product data circuits (Constantin: Fig. 3 element 13), wherein the data reuse circuit is configured to read (Constantin: Fig. 3 elements 11; [0056]), and determines a plurality of data subsets from the data set, so as to respectively input the plurality of data subsets into the plurality of dot product data circuits (Constantin: [0060], wherein data in each lane corresponds to data in each data subset), wherein each two adjacent dot product data circuits is configured to be used for two adjacent convolution operations in each operation cycle (Constantin: element 13; [0061]), and the two adjacent convolution operations correspond to two pixel matrices with a portion of the same pixels (Constantin: [0060]), wherein two data subsets inputted into two adjacent dot product data circuits comprise a portion of the same data (Constantin: [0060], MAC arrays in one dimension reuse the data from overlapping windows of activation values);
and the plurality of dot product data circuits, wherein each dot product data circuit of the plurality of dot product data circuits is configured to perform a dot product operation on an inputted data subset, so as to generate a dot product operation result (Constantin: element 13; [0061]),
wherein each data subset of the plurality of data subsets comprises a plurality of pairs of data, wherein the plurality of pairs of data comprises different pixel and different weight values (Constantin: [0060]-[0061], it follows that when each activation lane comprises a different order of activation data, even when the weights are the same order between two adjacent MAC arrays, each pair of (activation value, weight value) comprises different values for all pairs between the two adjacent MAC arrays).
However, while Constantin discloses shifting in activation input to the activation buffer ([0060]), Constantin does not explicitly disclose where the activation data is received from. Constantin also discloses a plurality of MAC arrays; however, Constantin only explicitly discloses details of an embodiment of the MAC circuitry when performing bit-wise operations (Fig. 4) and does not disclose circuitry for larger bit-width operations. Thus, Constantin does not teach a general register; and wherein the each dot product data circuit of the plurality of dot product data circuits comprises a plurality of multipliers, a plurality of adders, and an accumulation register,
Shao teaches a general register (Shao: Fig. 2 element 208; [0035], [0029]; wherein the global buffer comprises a register file).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to combine, with a reasonable expectation of success, the global buffer of Shao to the hardware accelerator of Constantin. One would have been motivated to combine these references because both references disclose performing convolution with pixel matrices, and the multi-level dataflow of Shao improves energy and/or execution efficiency (Shao [0026]).
Constantin/Shao does not explicitly disclose details of the multiply and accumulate circuitry for non-bit-wise operations. Thus, Constantin/Shao does not teach wherein the each dot product data circuit of the plurality of dot product data circuits comprises a plurality of multipliers, a plurality of adders, and an accumulation register.
Martin teaches wherein the each dot product data circuit of the plurality of dot product data circuits comprises a plurality of multipliers, a plurality of adders, and an accumulation register (Martin: Fig. 4 element 302; [0034]; Fig. 3 element 304; [0037]).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to substitute, with a reasonable expectation of success, the multiply and accumulate array circuitry of Constantin with the convolution engine and accumulator circuitry of Martin. One would have been motivated to combine these references because both references disclose multiply-accumulate circuitry for performing convolution operations, and combining prior art elements according to known methods to yield predictable results (of performing a convolution operation on operands with bit-widths larger than 1).
As per claim 2, Constantin/Shao/Martin further teaches The computing device according to claim 1, wherein the each dot product data circuit of the plurality of dot product data circuits is further configured to generate a current cumulative result of the dot product data circuit based on a previous cumulative result of the dot product data circuit and the dot product operation result (Martin: [0037], “Each accumulator 304 receives the output of one convolution engine 302 and adds the output to the previous convolution engine output”).
As per claim 3, Constantin/Shao/Martin further teaches The computing device according to claim 2, wherein the each dot product data circuit of the plurality of dot product data circuits is further configured to write the current cumulative result to the general register to serve as a convolution operation result when it is determined that a convolution operation has ended (Shao: [0044]).
As per claim 6, Constantin/Shao/Martin further teaches The computing device according to claim 1, wherein the computing device is a stream processor (Constantin: [0012] The computing device of Constantin/Shao is a stream processor because it is a parallel computing system, and Chan (US 20190171448 A1) is evidence for a parallel system as a steam processor (Chen [0002])).
As per claims 7-9, it is directed to a method corresponding to the computing device of claims 1-3, respectively, and is rejected for the same reasons.
Conclusion
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182