DETAILED ACTION
Claims 1 through 14 originally filed 15 November 2021. By amendment received 26 November 2024; claims 1, 2, 4, and 5 are amended. By amendment received 21 April 2025; claim 1 is amended and claim 15 is added. By amendment received 12 November 2025; claims 1 and 15 are amended and claims 16 and 17 are added. Claims 1 through 17 are addressed by this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered; they are addressed below.
It is noted that all items submitted to the office are converted into black and white before reaching the examination staff. Because of this, some colored lettering and markings in the remarks are faded. If it is convenient, it would be appreciated if colors are removed from documents prior to submission or if only colors which convert well to black and white are utilized (e.g., darker colors for black regions).
Applicant argues that the amendment to claim 15 overcomes the previous rejection under 35 U.S.C. 112(a). This argument is persuasive and the corresponding rejection is withdrawn.
Applicant argues that Joseph (US Pub. 2017/0033535) does not teach or render obvious the amended features of claim 15. This argument is persuasive. However, upon further search and consideration, Yoshikawa (US Pub. 2010/0208760) has been located which, in combination with the previously cited art, renders this feature obvious. As such, new rejections have been formulated as set forth below.
Applicant argues that the combined teachings of Sirbu et al. (Sirbu, US Pub. 2019/0312413) and Tanaka (US Pub. 2007/0241354) does not teach or render obvious the amended features of claim 15. This argument is persuasive. However, upon further search and consideration, Yoshikawa has been located which, in combination with the previously cited art, renders this feature obvious. As such, new rejections have been formulated as set forth below.
Applicant argues that the combined teachings of Sirbu and Tanaka do not teach or render obvious the limitation "A first semiconductor structure; a second semiconductor structure, located on the first semiconductor structure" because, according to applicant, Tanaka does not teach this feature. To support this argument, applicant contends that the layer of Tanaka that most closely corresponds to the second semiconductor structure in location is not formed of a semiconductor material.
Initially, in light of the above change in rejection, the claim containing this limitation is now rejected on the basis of the combined teachings of Sirbu, Tanaka, and Yoshikawa (see below). Accordingly, this argument is considered in light of this new rejection.
Applicant's argument is not persuasive because it does not address the rejection (MPEP §2145IV). Specifically, the argued limitation was and is rejected as being taught by Sirbu rather than Tanaka. Since Sirbu is cited as teaching this feature rather than Tanaka, the absence of this feature from Tanaka alone does not weigh on the obviousness of this feature in the rejection based on the combined teachings of Sirbu, Tanaka, and Yoshikawa (MPEP §2145IV). As such, this argument is not persuasive.
The limitation "A first semiconductor structure; a second semiconductor structure, located on the first semiconductor structure" is rendered obvious by the combined teachings of Sirbu, Tanaka, and Yoshikawa (see below). Applicant's argument that Tanaka does not teach this feature is not persuasive because it does not address the rejection (MPEP §2145IV).
Applicant argues that the combined teachings of Sirbu and Tanaka do not teach or render obvious the added limitations of claims 16 and 17. However, upon review, it is determined that Sirbu teaches these new features. As such, rejections for these new claims have been formulated as set forth below.
The authorization of communications via the internet in the Remarks is not effective. Such authorization must be provided on a separate paper to be entitled acceptance (MPEP §502.03II). Internet authorization must be submitted on a separate paper to be entitled to acceptance in accordance with 37 CFR 1.4(c).
As such, all claims are addressed as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 through 11, 13, 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sirbu et al. (Sirbu, US Pub. 2019/0312413), in view of Tanaka (US Pub. 2007/0241354), and further in view of Yoshikawa (US Pub. 2010/0208760).
Regarding claim 1, Sirbu discloses, "A base, having a first surface and a second surface" (p. [0027] and Fig. 1, pt. 10). "The first surface being a light exiting surface" (p. [0029] and Fig. 1, pts. 10 and 100). "An epitaxial structure, located on the second surface of the base" (p. [0030] and Fig. 1, pts. 2 and 10). "A first semiconductor structure" (p. [0030] and Fig. 1, pt. 22). "A second semiconductor structure, located on the first semiconductor structure" (p. [0030] and Fig. 1, pts. 22 and 32). "An intermediate layer, located on the second semiconductor structure" (p. [0030] and Fig. 1, pts. 32 and 42). "A third semiconductor structure, located on the intermediate layer" (p. [0030] and Fig. 1, pts. 32A and 42). "A fourth semiconductor structure, located on the third semiconductor structure" (p. [0030] and Fig. 1, pts. 24 and 32A). "An active structure, located between the third semiconductor structure and the fourth semiconductor structure" (p. [0030] and Fig. 1, pts. 24, 62, and 32A). Sirbu does not explicitly disclose, "A first electrode structure and a second electrode structure, located on the fourth semiconductor structure." "Wherein a part of the first electrode structure penetrates the fourth semiconductor structure, the active structure and the third semiconductor structure and is connected to the intermediate layer." "Wherein the second electrode structure substantially correspond to the current conduction region and portions of the current limiting region." Tanaka discloses, "A first electrode structure and a second electrode structure, located on the fourth semiconductor structure" (p. [0057] and Fig. 2, pts. 8, 15, and 33). "Wherein a part of the first electrode structure penetrates the fourth semiconductor structure, the active structure and the third semiconductor structure and is connected to the intermediate layer" (p. [0058] and Fig. 2, pts. 3, 4, 5, 6, 7, 8, and 33). "Wherein the second electrode structure substantially correspond to the current conduction region and portions of the current limiting region" (p. [0053] and Fig. 2, pts. 11a, 11b, and 15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sirbu with the teachings of Tanaka. In view of the teachings of Sirbu regarding a VCSEL with electrodes provided on the same side of the substrate, the alternate layout of the electrodes to be provided atop the upper most layer as well as the alternate material usage for analogous layers within the laser device as taught by Tanaka would enhance the teachings of Sirbu by allowing the electrodes to be provided atop a level surface in a manner that facilitates further connection as well as by providing alternate materials that are generally suitable for use in a VCSEL and allow use of an alternate material system or different fabrication techniques.
The combination of Sirbu and Tanaka does not explicitly disclose, "A current-confining layer, formed in the third semiconductor structure." "[The current-confining layer] having a current conduction region and a current limiting region." "Wherein the current conduction region is surrounded and defined by the current limiting region." Yoshikawa discloses, "A current-confining layer, formed in the third semiconductor structure" (p. [0028] and Fig. 2, pts. 106 and 106A). "[The current-confining layer] having a current conduction region and a current limiting region" (p. [0030] and Fig. 2, pt. 106A). "Wherein the current conduction region is surrounded and defined by the current limiting region" (p. [0030] and Fig. 2, pt. 106A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Sirbu and Tanaka with the teachings of Yoshikawa. In view of the teachings of Sirbu regarding a VCSEL with a region for current confinement, the additional inclusion of a current confinement region beneath the active region as taught by Yoshikawa would enhance the teachings of Sirbu and Tanaka by allowing the degree of current concentration to be improved.
Regarding claim 2, Sirbu discloses, "An optical component, located on the first surface of the base" (p. [0042] and Fig. 2, pts. 10A and 12).
Regarding claim 3, Sirbu discloses, "Wherein the base is a gallium arsenide (GaAs) substrate" (p. [0027] and Fig. 1, pt. 10).
Regarding claim 4, Sirbu does not explicitly disclose, "Wherein the intermediate layer comprises gallium arsenide (GaAs) or indium gallium phosphide (InGaP)." Tanaka discloses, "Wherein the intermediate layer comprises gallium arsenide (GaAs) or indium gallium phosphide (InGaP)" (p. [0046], [0059], and Fig. 2, pt. 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sirbu with the teachings of Tanaka for the reasons provided above regarding claim 1.
Regarding claim 5, Sirbu discloses, "Wherein the intermediate layer has a p-type or n-type conductivity type" (p. [0037] and Fig. 1, pt. 32).
Regarding claim 6, The combination of Sirbu, Tanaka, and Yoshikawa does not explicitly disclose, "Wherein a thickness of the intermediate layer is an odd-number multiple of 1/4n of a light emitting wavelength of the semiconductor laser, wherein n is a refractive index." The examiner takes Official Notice of the fact that it was known in the art to dimension layers within a VCSEL and near a DBR reflector thereof to have a thickness of an odd integer multiple of the wavelength since such dimensioning allows the layer to additionally operate in concert with the DBR by providing a reflective function. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to dimension the intermediate layer to have a thickness that is an integer multiple of a quarter wavelength so as to additionally operate in concert with the DBR layer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 7, Sirbu discloses, "A contact layer located on the fourth semiconductor structure" (p. [0028] and Fig. 1, pts. 34 and 44).
Regarding claim 8, Sirbu discloses, "A mirror layer located on the contact layer" (p. [0031] and Fig. 1, pts. 24 and 44).
Regarding claim 9, The combination of Sirbu, Tanaka, and Yoshikawa does not explicitly disclose, "Wherein the mirror layer is embedded in the second electrode." The examiner takes Official Notice of the fact that it was known in the art to cover a DBR of a VCSEL with an electrode so as to allow the electrode to provide an additional reflective function. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to embed the upper DBR in an upper electrode, since such an arrangement would allow the electrode to contribute to the reflection provided by the reflector.
Regarding claim 10, Sirbu discloses, "Wherein the base includes an undoped base layer" (p. [0027] and Fig. 1, pt. 10, where the substrate is not identified as doped).
Regarding claim 11, Sirbu discloses, "Wherein at least one of the first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure includes a distributed Bragg reflector structure" (p. [0030] and Fig. 1, pt. 22).
Regarding claim 13, Sirbu discloses, "Wherein a surface of the base includes patterned surface structures" (p. [0042] and Fig. 2, pts. 10A and 12).
Regarding claim 14, Sirbu does not explicitly disclose, "Wherein the base is a glass substrate." Tanaka discloses, "Wherein the base is a glass substrate" (p. [0045] and Fig. 2, pt. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sirbu with the teachings of Tanaka for the reasons provided above regarding claim 1.
Regarding claim 16, Sirbu discloses, "Wherein conductivities of the first semiconductor structure and the second semiconductor structure are different" (p. [0030], [0037], and Fig. 1, pts. 22 and 32).
Regarding claim 17, Sirbu discloses, "Wherein the first semiconductor structure is an un-doped distributed Bragg reflector (DBR)" (p. [0030] and Fig. 1, pt. 22).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sirbu, in view of Tanaka, in view of Yoshikawa, and further in view of Tsuji (US Pub. 2019/0067899).
Regarding claim 12, The combination of Sirbu, Tanaka, and Yoshikawa does not explicitly disclose, "Wherein each of the second semiconductor structure and the third semiconductor structure includes the distributed Bragg reflector structure." Tsuji discloses, "Wherein each of the second semiconductor structure and the third semiconductor structure includes the distributed Bragg reflector structure" (p. [0064] and Fig. 1, pts. 11 and 13). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Sirbu, Tanaka, and Yoshikawa with the teachings of Tsuji. In view of the teachings of Sirbu regarding a VCSEL with a contact layer between a lower DBR layer and an active layer and the teachings of Yoshikawa regarding a VCSEL in which the lower DBR layer is present both below and within the post, the additional formation of the layer below the contact layer, the contact layer, and the layer above the contact layer as a DBR structure as taught by Tsuji would enhance the teachings of Sirbu, Tanaka, and Yoshikawa by providing additional layers for providing the required reflection and thereby allowing for either a higher reflectivity or a reduced overall thickness.
The combination of Sirbu, Tanaka, Yoshikawa, and Tsuji does not explicitly disclose, "A number of pairs of the distributed Bragg reflector in the second semiconductor structure is smaller than a number of pairs of the distributed Bragg reflector in the third semiconductor structure." The examiner takes Official Notice of the fact that it was known in the art to adjust the number of layers in a multilayer reflector so as to adjust the reflectivity of that reflector. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the number of reflector pairs in the second and third semiconductor structures relative to one another so as to regulate how these layers reflect light within the cavity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Joseph (US Pub. 2017/0033535) in view of Yoshikawa.
Regarding claim 15, Joseph discloses, "A base, having a first surface and a second surface" (p. [0222] and Fig. 8, pt. 81). "The first surface being a light exiting surface" (p. [0220] and Fig. 14B). "An epitaxial stacked structure, located on the second surface of the base" (p. [0221]-[0230] and Fig. 8, pts. 81, 82, 83, 84, 85, 86, 87, 88, and 89). "A first semiconductor structure" (p. [0223] and Fig. 8, pt. 82). "A second semiconductor structure, located on the first semiconductor structure" (p. [0224] and Fig. 8, pts. 82 and 83). "An intermediate layer, located on the second semiconductor structure" (p. [0225] and Fig. 8, pts. 83 and 84). "A third semiconductor structure, located on the intermediate layer" (p. [0226] and Fig. 8, pts. 84 and 85). "A fourth semiconductor structure, located on the third semiconductor structure" (p. [0229] and Fig. 8, pts. 85 and 88). "An active structure, located between the third semiconductor structure and the fourth semiconductor structure" (p. [0227] and Fig. 8, pts. 85, 86, and 88). "A first recess region and a second recess region formed in the epitaxial stacked structure and passes through the fourth semiconductor structure, the active structure, the third semiconductor structure to reach the intermediate layer" (p. [0225], [0235], [0238], and Figs. 8, 10A, and 10B, pts. 84, 1001, and 1004). "A first electrode structure located on the fourth semiconductor structure and in the second recess region" (p. [0229], [0254] and Figs. 8, 10B, and 13, pts. 88, 1001, and 1302). "[The first electrode structure] connected to the intermediate layer" (p. [0225], [0254] and Figs. 8 and 13, pts. 84 and 1302). "A second electrode structure located on the fourth semiconductor structure and connected to the fourth semiconductor structure" (p. [0229], [0255] and Figs. 8 and 13, pts. 88 and 1303). "A protection structure located between the first electrode structure and the epitaxial stacked structure" (p. [0253] and Fig. 13, pts. 1301 and 1303). "[The protection structure] between the second electrode structure and the epitaxial stacked structure" (p. [0253] and Fig. 13, pts. 1301 and 1302). Joseph does not explicitly disclose, "Wherein the first recess region surrounds at least one light emitting hole and define a location of the light emitting hole." Yoshikawa discloses, "Wherein the first recess region surrounds at least one light emitting hole and define a location of the light emitting hole" (p. [0029], [0030], and Figs. 1 and 2, pts. 106A, 110A, 114, and 122). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joseph with the teachings of Yoshikawa. In view of the teachings of Joseph regarding a VCSEL with trenches provided for creating a current confinement aperture, the alternate construction of the trenches as rings around the emission region as taught by Yoshikawa would enhance the teachings of Joseph by allowing the current confinement aperture to be evenly formed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Onishi et al. (Onishi, US Pub. 2010/0014551) is cited for teaching a VCSEL in which the lower DBR is formed of an undoped lower region and a doped upper region.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sean P Hagan whose telephone number is (571)270-1242. The examiner can normally be reached Monday - Thursday, 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at 571-272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN P HAGAN/Examiner, Art Unit 2828