DETAILED ACTION
Claims 1 through 14 originally filed 15 November 2021. By amendment received 26 November 2024; claims 1, 2, 4, and 5 are amended. By amendment received 21 April 2025; claim 1 is amended and claim 15 is added. By amendment received 12 November 2025; claims 1 and 15 are amended and claims 16 and 17 are added. By amendment received 5 June 2026; claims 1 and 15 are amended. Claims 1 through 17 are addressed by this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5 June 2026 has been entered.
Response to Arguments
Applicant's arguments have been fully considered; they are addressed below.
Applicant argues that the combined teachings of Sirbu et al. (Sirbu, US Pub. 2019/0312413), Tanaka (US Pub. 2007/0241354), and Yoshikawa (US Pub. 2010/0208760) does not teach or render obvious the limitation "Wherein the recess passes through the fourth semiconductor structure, the active structure, and the third semiconductor structure" as required by amended claim 1. This argument is persuasive and the rejection of claims 1 through 14, 16, and 17 are withdrawn. However, upon further search and consideration, it is determined that Joseph (US Pub. 2017/0033535), in combination with the previously cited art, renders this feature obvious. As such, new rejections have been formulated as set forth below.
Applicant argues that the combined teachings of Joseph and Yoshikawa do not teach or render obvious the limitations "Wherein the first recess region surrounds at least one light emitting hole and define a location of the light emitting hole" and "The first recess region and the second recess region are mutually separated and are not in mutual communication" because, according to applicant, neither Joseph nor Yoshikawa individually teach all features of these limitations. To support this argument, applicant contends that Joseph does not teach a first region that surrounds the light emitting hole and Yoshikawa does not teach a configuration in which recesses are not in mutual communication.
Applicant's argument is not persuasive because it only addresses the references individually where the rejection is based on the combination of these references (MPEP §2145IV). Specifically, Joseph teaches first recess regions, used for producing oxide apertures, and a second recess region in which the various recess regions are not in mutual communication (Joseph, ¶235 & ¶238 describing the arrangement of Figures 10A and 10B in which first recesses 1004 and second recess 1001 are not in mutual communication). Yoshikawa teaches a recess, used for producing oxide apertures, that surrounds the light emission region (Yoshikawa, ¶29-30 describing the arrangement of Figures 1 and 2 in which groove 114 surrounds aperture 122). The recess of Yoshikawa corresponds in function to the first recesses of Joseph such that implementing a recess in like manner to Yoshikawa within the device of Joseph would involve creating a trench surrounding the light emission apertures in place of the first recesses of Joseph. The first and second recesses of Joseph are separate therein and Yoshikawa does not include recesses corresponding to the second recesses of Joseph, so one of ordinary skill in the art would have found it obvious to maintain the second recesses of Joseph as being separate from the first recesses even in the case that the first recesses are modified to be formatted as in Yoshikawa. Since Joseph teaches first and second recesses that are not in mutual communication and since Yoshikawa teaches that the first recesses may alternately surround the emission aperture, the combined teachings of Joseph and Yoshikawa render obvious the simultaneous presence of these features. As such, this argument is not persuasive.
The limitations "Wherein the first recess region surrounds at least one light emitting hole and define a location of the light emitting hole" and "The first recess region and the second recess region are mutually separated and are not in mutual communication" are rendered obvious by the combined teachings of Joseph and Yoshikawa (see below). Applicant's argument that neither Joseph nor Yoshikawa individually teach all features of these limitations is not persuasive because it only addresses the references individually where the rejection is based on the combination of these references (MPEP §2145IV).
The authorization of communications via the internet in the Remarks is not effective. Such authorization must be provided on a separate paper to be entitled acceptance (MPEP §502.03II). Internet authorization must be submitted on a separate paper to be entitled to acceptance in accordance with 37 CFR 1.4(c).
As such, all claims are addressed as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 through 7 and 10 through 14 are rejected under 35 U.S.C. 103 as being unpatentable over Joseph (US Pub. 2017/0033535), in view of Yoshikawa (US Pub. 2010/0208760), and further in view of Tan et al. (Tan, US Pub. 2019/0013646)aka (US Pub. 2007/0241354).
Regarding claim 1, Joseph discloses, "A base, having a first surface and a second surface" (p. [0222] and Fig. 8, pt. 81). "The first surface being a light exiting surface" (p. [0220] and Fig. 14B). "An epitaxial structure, located on the second surface of the base" (p. [0221]-[0230] and Fig. 8, pts. 81, 82, 83, 84, 85, 86, 87, 88, and 89). "A first semiconductor structure" (p. [0223] and Fig. 8, pt. 82). "A second semiconductor structure, located on the first semiconductor structure" (p. [0224] and Fig. 8, pts. 82 and 83). "An intermediate layer, located on the second semiconductor structure" (p. [0225] and Fig. 8, pts. 83 and 84). "A third semiconductor structure, located on the intermediate layer" (p. [0226] and Fig. 8, pts. 84 and 85). "The current-confining layer having a current conduction region and a current limiting region" (p. [0240] and Fig. 10D and pts. 125 and 126). "Wherein the current conduction region is surrounded and defined by the current limiting region" (p. [0240] and Fig. 10D and pts. 125 and 126). "A fourth semiconductor structure, located on the third semiconductor structure" (p. [0229] and Fig. 8, pts. 85 and 88). "An active structure, located between the third semiconductor structure and the fourth semiconductor structure" (p. [0227] and Fig. 8, pts. 85, 86, and 88). "Wherein the recess passes through the fourth semiconductor structure, the active structure, and the third semiconductor structure" (p. [0225], [0235], [0238], and Figs. 8, 10A, and 10B, pts. 84, 85, 86, 88, 1001, and 1004). "A first electrode structure and a second electrode structure, located on the fourth semiconductor structure" (p. [0229], [0254], [0255] and Figs. 8, 10B, and 13, pts. 88, 1001, 1302, and 1303). "Wherein a part of the first electrode structure penetrates the fourth semiconductor structure, the active structure and the third semiconductor structure and is connected to the intermediate layer" (p. [0225], [0254] and Figs. 8 and 13, pts. 84, 85, 86, 88, and 1302). Joseph does not explicitly disclose, "A current-confining layer, formed in the third semiconductor structure by oxidation via a recess." Yoshikawa discloses, "A current-confining layer, formed in the third semiconductor structure by oxidation via a recess" (p. [0028], [0030], and Fig. 2, pts. 106, 106A, and 114). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joseph with the teachings of Yoshikawa. In view of the teachings of Joseph regarding a VCSEL with trenches provided for creating a current confinement aperture, the alternate construction of the trenches as rings around the emission region as taught by Yoshikawa would enhance the teachings of Joseph by allowing the current confinement aperture to be evenly formed.
The combination of Joseph and Yoshikawa does not explicitly disclose, "Wherein the second electrode structure substantially corresponded to the current conduction region and portions of the current limiting region." Tanaka discloses, "Wherein the second electrode structure substantially corresponded to the current conduction region and portions of the current limiting region" (p. [0053] and Fig. 2, pts. 11a, 11b, and 15). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Joseph and Yoshikawa with the teachings of Tanaka. In view of the teachings of Joseph regarding a VCSEL with electrodes covering a current injection opening, the alternate layout of the electrodes to be provided atop the upper most layer as well as the alternate material usage for analogous layers within the laser device as taught by Tanaka would enhance the teachings of Joseph and Yoshikawa by providing a suitably alternate manner of fabricating the electrode connected to the current injection aperture associated with the laser device as well as by providing alternate materials that are generally suitable for use in a VCSEL and allow use of an alternate material system or different fabrication techniques.
Regarding claim 2, Joseph discloses, "An optical component, located on the first surface of the base" (p. [0282] and Fig. 17. pt. 171).
Regarding claim 3, Joseph discloses, "Wherein the base is a gallium arsenide (GaAs) substrate" (p. [0222] and Fig. 8, pt. 81).
Regarding claim 4, The combination of Joseph and Yoshikawa does not explicitly disclose, "Wherein the intermediate layer comprises gallium arsenide (GaAs) or indium gallium phosphide (InGaP)." Tanaka discloses, "Wherein the intermediate layer comprises gallium arsenide (GaAs) or indium gallium phosphide (InGaP)" (p. [0046], [0059], and Fig. 2, pt. 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Joseph and Yoshikawa with the teachings of Tanaka for the reasons provided above regarding claim 1.
Regarding claim 5, Joseph discloses, "Wherein the intermediate layer has a p-type or n-type conductivity type" (p. [0225] and Fig. 8, pt. 84).
Regarding claim 6, The combination of Joseph, Yoshikawa, and Tanaka does not explicitly disclose, "Wherein a thickness of the intermediate layer is an odd-number multiple of 1/4n of a light emitting wavelength of the semiconductor laser, wherein n is a refractive index." The examiner takes Official Notice of the fact that it was known in the art to dimension layers within a VCSEL and near a DBR reflector thereof to have a thickness of an odd integer multiple of the wavelength since such dimensioning allows the layer to additionally operate in concert with the DBR by providing a reflective function. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to dimension the intermediate layer to have a thickness that is an integer multiple of a quarter wavelength so as to additionally operate in concert with the DBR layer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 7, Joseph discloses, "A contact layer located on the fourth semiconductor structure" (p. [0230] and Fig. 8, pts. 88 and 89).
Regarding claim 10, Joseph discloses, "Wherein the base includes an undoped base layer" (p. [0222] and Fig. 8, pt. 81, where the substrate is not identified as doped).
Regarding claim 11, Joseph discloses, "Wherein at least one of the first semiconductor structure, the second semiconductor structure, the third semiconductor structure and the fourth semiconductor structure includes a distributed Bragg reflector structure" (p. [0224], [0226], [0229], and Fig. 8, pts. 83, 85, and 88).
Regarding claim 12, Joseph discloses, "Wherein each of the second semiconductor structure and the third semiconductor structure includes the distributed Bragg reflector structure" (p. [0224], [0226], and Fig. 8, pts. 83 and 85).
The combination of Joseph, Yoshikawa, and Tanaka does not explicitly disclose, "A number of pairs of the distributed Bragg reflector in the second semiconductor structure is smaller than a number of pairs of the distributed Bragg reflector in the third semiconductor structure." The examiner takes Official Notice of the fact that it was known in the art to adjust the number of layers in a multilayer reflector so as to adjust the reflectivity of that reflector. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the number of reflector pairs in the second and third semiconductor structures relative to one another so as to regulate how these layers reflect light within the cavity, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 13, Joseph discloses, "Wherein a surface of the base includes patterned surface structures" (p. [0282] and Fig. 17. pt. 171).
Regarding claim 14, The combination of Joseph and Yoshikawa does not explicitly disclose, "Wherein the base is a glass substrate." Tanaka discloses, "Wherein the base is a glass substrate" (p. [0045] and Fig. 2, pt. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Joseph and Yoshikawa with the teachings of Tanaka for the reasons provided above regarding claim 1.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Joseph, in view of Yoshikawa, in view of Tanaka, and further in view of Tan.
Regarding claim 8, The combination of Joseph, Yoshikawa, and Tanaka does not explicitly disclose, "A mirror layer located on the contact layer." Tan discloses, "A mirror layer located on the contact layer" (p. [0022] and Fig. 2, pts. 140 and 185, where the top layer of 140 corresponds to the contact layer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Joseph, Yoshikawa, and Tanaka with the teachings of Tan. In view of the teachings of Joseph regarding a VCSEL device, the additional inclusion of a mode selective reflector within the top electrode as taught by Tan would enhance the teachings of Joseph, Yoshikawa, and Tanaka by allowing the emission mode of the laser to be controlled.
Regarding claim 9, The combination of Joseph, Yoshikawa, and Tanaka does not explicitly disclose, "Wherein the mirror layer is embedded in the second electrode." Tan discloses, "Wherein the mirror layer is embedded in the second electrode" (p. [0022] and Fig. 2, pts. 150 and 185). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Joseph, Yoshikawa, and Tanaka with the teachings of Tan for the reasons provided above regarding claim 8.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Joseph in view of Yoshikawa.
Regarding claim 15, Joseph discloses, "A base, having a first surface and a second surface" (p. [0222] and Fig. 8, pt. 81). "The first surface being a light exiting surface" (p. [0220] and Fig. 14B). "An epitaxial stacked structure, located on the second surface of the base" (p. [0221]-[0230] and Fig. 8, pts. 81, 82, 83, 84, 85, 86, 87, 88, and 89). "A first semiconductor structure" (p. [0223] and Fig. 8, pt. 82). "A second semiconductor structure, located on the first semiconductor structure" (p. [0224] and Fig. 8, pts. 82 and 83). "An intermediate layer, located on the second semiconductor structure" (p. [0225] and Fig. 8, pts. 83 and 84). "A third semiconductor structure, located on the intermediate layer" (p. [0226] and Fig. 8, pts. 84 and 85). "A fourth semiconductor structure, located on the third semiconductor structure" (p. [0229] and Fig. 8, pts. 85 and 88). "An active structure, located between the third semiconductor structure and the fourth semiconductor structure" (p. [0227] and Fig. 8, pts. 85, 86, and 88). "A first recess region and a second recess region formed in the epitaxial stacked structure and passes through the fourth semiconductor structure, the active structure, and the third semiconductor structure to reach the intermediate layer" (p. [0225], [0235], [0238], and Figs. 8, 10A, and 10B, pts. 84, 1001, and 1004). "The first recess region and the second recess region are mutually separated and are not in mutual communication" (p. [0235], [0238], and Figs. 10A, and 10B, pts. 1001 and 1004). "A first electrode structure located on the fourth semiconductor structure and in the second recess region" (p. [0229], [0254] and Figs. 8, 10B, and 13, pts. 88, 1001, and 1302). "[The first electrode structure] connected to the intermediate layer" (p. [0225], [0254] and Figs. 8 and 13, pts. 84 and 1302). "A second electrode structure located on the fourth semiconductor structure and connected to the fourth semiconductor structure" (p. [0229], [0255] and Figs. 8 and 13, pts. 88 and 1303). "A protection structure located between the first electrode structure and the epitaxial stacked structure" (p. [0253] and Fig. 13, pts. 1301 and 1303). "[The protection structure] between the second electrode structure and the epitaxial stacked structure" (p. [0253] and Fig. 13, pts. 1301 and 1302). Joseph does not explicitly disclose, "Wherein the first recess region surrounds at least one light emitting hole and define a location of the light emitting hole." Yoshikawa discloses, "Wherein the first recess region surrounds at least one light emitting hole and define a location of the light emitting hole" (p. [0029], [0030], and Figs. 1 and 2, pts. 106A, 110A, 114, and 122). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joseph with the teachings of Yoshikawa for the reasons provided above regarding claim 1.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Joseph, in view of Yoshikawa, in view of Tanaka, and further in view of Sirbu et al. (Sirbu, US Pub. 2019/0312413).
Regarding claim 16, The combination of Joseph, Yoshikawa, and Tanaka does not explicitly disclose, "Wherein conductivities of the first semiconductor structure and the second semiconductor structure are different." Sirbu discloses, "Wherein conductivities of the first semiconductor structure and the second semiconductor structure are different" (p. [0030], [0037], and Fig. 1, pts. 22 and 32). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Joseph, Yoshikawa, and Tanaka with the teachings of Sirbu. In view of the teachings of Joseph regarding a VCSEL in which the lower DBR layer is present both below and within the post, the additional inclusion of an undoped DBR layer directly atop the substrate as taught by Sirbu would enhance the teachings of Joseph, Yoshikawa, and Tanaka by providing additional layers for providing the required reflection and thereby allowing for either a higher reflectivity or a reduced overall thickness.
Regarding claim 17, The combination of Joseph, Yoshikawa, and Tanaka does not explicitly disclose, "Wherein the first semiconductor structure is an un-doped distributed Bragg reflector (DBR)." Sirbu discloses, "Wherein the first semiconductor structure is an un-doped distributed Bragg reflector (DBR)" (p. [0030] and Fig. 1, pt. 22). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Joseph, Yoshikawa, and Tanaka with the teachings of Sirbu for the reasons provided above regarding claim 16.
Conclusion
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/SEAN P HAGAN/Examiner, Art Unit 2828
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