DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The previous provisional non-statutory double patenting rejection of claims 1-9 and 21-27 have been withdrawn based on the Applicant’s amendments to claims 1 and 21.
Claim Rejections - 35 USC § 112
The Examiner acknowledges that the Applicant’s amendments to claim 8 have overcome the previous rejection of claim 8 under 35 USC 112(b). Therefore, the previous rejection of claim 8 under 35 USC 112(b) has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2020/0279855) hereinafter “Tran” in view of Greenlee et al. (US 2023/0055422) hereinafter “Greenlee” and in further view of Zhang et al. (US 2023/0099107) hereinafter “Zhang”.
Regarding claim 1, Fig. 19 of Tran teaches a semiconductor device, comprising: a peripheral circuit region comprising a plurality of complementary metal-oxide-semiconductor components (Paragraph 0034); a substrate on the peripheral circuit region comprising: a conductively doped poly silicon layer (Item 19; Paragraph 0012) on the peripheral circuit region; an oxide layer (Item 31) on the conductively doped poly silicon layer (Item 19); and a conductive layer (Item 17) on the oxide layer (Item 31), where the conductive layer (Item 17) comprises tungsten (Paragraph 0025 where the select gates may comprise semiconductive or tungsten or a combination of the two and Paragraph 0024 where multiple configurations of select gates are anticipated by the Applicant); and an array region on the substrate comprising: a plurality of gate structures (Top four Items 29) and a plurality of insulating layers (Items 24) alternately stacked on the conductive layer (Item 17), wherein a bottommost gate structure (Fourth from the top Item 29) of the gate structures (Top four Items 29) and the conductive layer (Item 17) together serve as a plurality ground select lines (Items 14 and 21; Paragraph 0014) of the semiconductor device, and a ratio of a thickness of the conductive layer (Item 17) to a thickness of each of the gate structures (Top four Items 29) is about 2 (Paragraph 0037); and a vertical channel structure (Combination of Items 30,32,34 and 36) penetrating the gate structures (Top four Items 29) and the insulating layers (Items 24) and extending into the conductively doped poly silicon layer (Item 19).
Tran does not explicitly teach where the conductively doped polysilicon layer is an N-type doped poly silicon layer.
Greenlee teaches where a conductively doped semiconductor layer (Items 42 or 43) is n-doped polysilicon (Paragraph 0011).
It would have been obvious to one having ordinary skill in the art before thee effective filing date of the claimed invention to have the conductively doped polysilicon layer be an N-type doped poly silicon layer because n-type dopant introduced into polysilicon is known to yield a conductor material in a device (Greenlee Paragraph 0011).
Tran does not explicitly teach where a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4.
Zhang teaches where a select gate conductive tier (Item 118) has a thickness in the range from 30 to 200 nm (Paragraph 0062) and gate structures (Item 246) in a stack have a thickness between 20 to 50 nm (Paragraph 0076).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a ratio of a thickness of the conductive layer to a thickness of each of the gate structures be about 3 to 4 because this allows the layer to be used as a select gate (Zhang Paragraph 0062).
Regarding claim 2, the combination of Tran, Greenlee and Zhang teaches all of the elements of the claimed invention as stated above.
Tran does not explicitly state where the thickness of the conductive layer is smaller than a thickness of the N-type doped poly silicon layer.
Fig. 9 of Greenlee further teaches where the thickness of a conductive layer (Item 47) is smaller than an N-type doped polysilicon layer (Item 42).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the thickness of the conductive layer be smaller than a thickness of the N-type doped poly silicon layer because this allows for the conductive layer to act as a select gate (Greenlee Paragraph 0014).
Regarding claim 3, Fig. 19 of Tran further teaches where a portion of a channel layer (Item 36) of the vertical channel structure (Combination of Items 30, 32, 34 and 36) is in contact (direct physical) with the conductively doped polysilicon layer (Item 19; N-type doped when combined with Greenlee as stated in the rejection of claim 1 above).
Regarding claim 4, the combination Tran, Greenlee and Zhang teaches all of the elements of the claimed invention as stated above.
Tran further teaches where a storage layer (Item 32) of the vertical channel structure (Combination of Items 30, 32, 34 and 36) comprises an upper segment surrounding a top of the channel layer (Item 36) and a lower segment surrounding a bottom of the channel layer (Item 36).
Tran does not teach the portion of the channel layer of the vertical channel structure is between the upper segment and the lower segment.
Fig. 22 of Greenlee teaches where wherein a storage layer (Item 32) of the vertical channel structure (Combination of Items 30, 32, 34 and 36) comprises an upper segment surrounding a top of the channel layer (Item 36) and a lower segment surrounding a bottom of the channel layer (Item 36), and the portion of the channel layer (Item 36) of the vertical channel structure (that directly physically contacts a doped polysilicon layer Item 42) is between the upper segment and the lower segment.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the portion of the channel layer of the vertical channel structure is between the upper segment and the lower segment because this allows for greater physical and electrical contact between the channel layer and the N-type doped polysilicon layer (Greenlee Paragraph 0021).
Regarding claim 5, Fig. 19 of Tran further teaches where the oxide layer (Item 31) comprises a first portion (See Picture 1 below) surrounding the upper segment of the storage layer (Item 32) and a second portion (See Picture 1 below) connecting to the first portion, wherein a thickness of the first portion is smaller than a thickness of the second portion.
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Picture 1 (Labeled version of Tran Fig. 19)
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2020/0279855) hereinafter “Tran” in view of Greenlee et al. (US 2023/0055422) hereinafter “Greenlee” and Zhang et al. (US 2023/0099107) hereinafter “Zhang” and in further view of Lee (US 2021/0217468) hereinafter “Lee”.
Regarding claim 6, the combination of Tran, Greenlee and Zhang teaches all of the elements of the claimed invention as stated above.
Tran does not teach where a bottom surface of the upper segment of the storage layer is substantially coplanar with a bottom surface of the first portion of the oxide layer.
Lee teaches a bottom surface of an upper segment (Item DL2) of a storage layer (Item DL) is substantially coplanar with a bottom surface of a first portion (Item P1) of an oxide layer (Item P1/P2).
It would have been obvious to one having ordinary skill in the at before the effective filing date of the claimed invention to have a bottom surface of the upper segment of the storage layer is substantially coplanar with a bottom surface of the first portion of the oxide layer because this configuration adequately allows for contact between a channel layer and a doped polysilicon layer (Lee Paragraph 0039).
Examiner’s Note: The Examiner notes that the term “substantially coplanar” allows for the bottom surface of the upper segment of the storage layer to be slightly above the bottom surface of the first oxide layer.
Regarding claim 7, the combination of Tran, Greenlee and Zhang teaches all of the elements of the claimed invention as stated above except where a bottom surface of the upper segment of the storage layer is higher than a bottommost surface of the oxide layer.
Lee teaches where a bottom surface of an upper segment (Item DL2) of a storage layer (Item DL) is higher than a bottommost surface of an oxide layer (Item P1/P2).
It would have been obvious to one having ordinary skill in the at before the effective filing date of the claimed invention to have a bottom surface of the upper segment of the storage layer be higher than a bottommost surface of the oxide layer because this configuration adequately allows for contact between a channel layer and a doped polysilicon layer (Lee Paragraph 0039).
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2020/0279855) hereinafter “Tran” in view of Greenlee et al. (US 2023/0055422) hereinafter “Greenlee” and Zhang et al. (US 2023/0099107) hereinafter “Zhang” and in further view of Barasakar et al. (US 9,779,948) hereinafter “Barasakar”.
Regarding claim 8, the combination of Tran, Greenlee and Zhang teaches all of the elements of the claimed invention as stated above except a common source line penetrating the array region and extending into the substrate, and an isolation spacer surrounding the common source line.
Fig. 10J of Barasakar teaches a common source line (Item 344) penetrating an array region (the stack starting at DL2) and extending into a substrate (All of the Item SGS and below), and an isolation spacer (Item 1044) surrounding the common source line (Item 344).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a common source line penetrating the array region and extending into the substrate, and an isolation spacer surrounding the common source line because the common source line may serve as an interconnect (Barasakar Column 4, Lines 35-37).
Regarding claim 9, the combination of Tran, Greenlee and Zhang teaches all of the elements of the claimed invention as stated above except where a bottom surface of the isolation spacer is below a top surface of the N-type doped poly silicon layer.
Fig. 10J of Barasakar teaches where a bottom surface of the isolation spacer (Item 1044) is below a top surface of a conductively doped semiconductor layer (Item DL1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a bottom surface of the isolation spacer is below a top surface of the N-type doped poly silicon layer because this allows for adequate electrical isolation between the surrounding gate stack and the common source line (Barasakar Column 17, Lines 21-25).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2020/0279855) hereinafter “Tran” in view of Greenlee et al. (US 2023/0055422) hereinafter “Greenlee”, Zhang et al. (US 2023/0099107) hereinafter “Zhang” and Barasakar et al. (US 9,779,948) hereinafter “Barasakar” and in further view of Lee (US 2021/0407585) hereinafter “Lee2”.
Regarding claim 10, the combination of Tran, Greenlee, Zhang and Barasakar teaches all of the elements of the claimed invention as stated above except where a distance between the common source line and the conductive layer is smaller than a distance between the common source line and the gate structures.
Fig. 5N of Lee2 teaches where a distance between the common source line (Item 181) and a conductive layer (Item 109) is smaller than a distance between the common source line (Item 181) and gate structures (Items 151).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a distance between the common source line and the conductive layer is smaller than a distance between the common source line and the gate structures because this allows for adequate electrical isolation between the common source line and the gate structures (Lee2 Paragraph 0102).
Claims 21-25 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2020/0279855) hereinafter “Tran” in view of Greenlee et al. (US 2023/0055422) hereinafter “Greenlee”.
Regarding claim 21, Fig. 19 of Tran teaches a semiconductor device, comprising: a substrate comprising a plurality of complementary metal-oxide-semiconductor components (Paragraph 0034); a conductively doped poly silicon layer (Item 19; Paragraph 0012) on the complementary metal-oxide-semiconductor components; an oxide layer (Item 31) on the conductively doped poly silicon layer (Item 19); and a conductive layer (Item 17) on the oxide layer (Item 31), where the conductive layer (Item 17) comprises tungsten (Paragraph 0025 where the gates may comprise semiconductive or tungsten or a combination of the two and Paragraph 0024 where multiple configurations of select gates are anticipated by the Applicant); a plurality of gate structures (Top four Items 29) and a plurality of insulating layers (Combination of Items 24 All Items 53 above Item 17) alternately stacked on the conductive layer (Item 17), wherein a bottommost gate structure (Fourth from the top Item 29) of the gate structures (Top four Items 29) and the conductive layer (Item 17) together serve as a plurality ground select lines (Items 14 and 21; Paragraph 0014) of the semiconductor device, and a thickness of the conductive layer (Item 17) is greater than a thickness of each of the gate structures (Top four Items 29) (Paragraph 0037 where a thickness of the conductive layer to a thickness of each of the gate structures is above 2), and a vertical channel structure (Combination of Items 30,32,34 and 36) penetrating the gate structures (Top four Items 29) and the insulating layers (Items 24) and terminating at the conductively doped poly silicon layer (Item 19).
Tran does not explicitly teach where the conductively doped polysilicon layer is an N-type doped poly silicon layer.
Greenlee teaches where a conductively doped semiconductor layer (Items 42 or 43) is n-doped polysilicon (Paragraph 0011).
It would have been obvious to one having ordinary skill in the art before thee effective filing date of the claimed invention to have the conductively doped polysilicon layer be an N-type doped poly silicon layer because n-type dopant introduced into polysilicon is known to yield a conductor material in a device (Greenlee Paragraph 0011).
Regarding claim 22, the combination of Tran and Greenlee teaches all of the elements of the claimed invention as stated above.
Tran does not explicitly state where the thickness of the conductive layer is smaller than a thickness of the N-type doped poly silicon layer.
Fig. 9 of Greenlee further teaches where the thickness of a conductive layer (Item 47) is smaller than an N-type doped polysilicon layer (Item 42).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the thickness of the conductive layer be smaller than a thickness of the N-type doped poly silicon layer because this allows for the conductive layer to act as a select gate (Greenlee Paragraph 0014).
Regarding claim 23, the combination of Tran and Greenlee teaches all of the elements of the claimed invention as stated above.
Tran does not teach where a portion of a sidewall of a channel layer of the vertical channel structure is directly in contact with the N-type doped poly silicon layer.
Fig. 22 of Greenlee teaches where a portion of a sidewall of a channel layer (Item 36) of a vertical channel structure is directly in contact with a conductively doped poly silicon layer (Item 42).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a portion of a sidewall of a channel layer of the vertical channel structure be directly in contact with the N-type doped poly silicon layer because this allows for better electrical contact between the channel layer and the conductively doped polysilicon layer (Greenlee Paragraph 0022).
Regarding claim 24, the combination Tran and Greenlee teaches all of the elements of the claimed invention as stated above.
Tran further teaches where a storage layer (Item 32) of the vertical channel structure (Combination of Items 30, 32, 34 and 36) comprises an upper segment surrounding a top of the channel layer (Item 36) and a lower segment surrounding a bottom of the channel layer (Item 36).
Tran does not teach the portion of the channel layer of the vertical channel structure is between the upper segment and the lower segment.
Fig. 22 of Greenlee teaches where wherein a storage layer (Item 32) of the vertical channel structure (Combination of Items 30, 32, 34 and 36) comprises an upper segment surrounding a top of the channel layer (Item 36) and a lower segment surrounding a bottom of the channel layer (Item 36), and the portion of the channel layer (Item 36) of the vertical channel structure (that directly physically contacts a doped polysilicon layer Item 42) is between the upper segment and the lower segment.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the portion of the channel layer of the vertical channel structure is between the upper segment and the lower segment because this allows for greater physical and electrical contact between the channel layer and the N-type doped polysilicon layer (Greenlee Paragraph 0021).
Regarding claim 25, Fig. 19 of Tran further teaches where the oxide layer (Item 31) comprises a first portion (See Picture 1 above) surrounding the upper segment of the storage layer (Item 32) and a second portion (See Picture 1 above) connecting to the first portion, wherein a thickness of the first portion is smaller than a thickness of the second portion.
Regarding claim 28, Fig. 19 of Tran further teaches where a bottommost insulating layer (Item 53) of the insulating layers is between the bottommost gate structures (Fourth from the top Item 29) and the conductive layer (Item 17).
Claims 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 2020/0279855) hereinafter “Tran” in view of Greenlee et al. (US 2023/0055422) hereinafter “Greenlee” and in further view of Lee (US 2021/0217468) hereinafter “Lee”.
Regarding claim 26, the combination of Tran and Greenlee teaches all of the elements of the claimed invention as stated above.
Tran does not teach where a bottom surface of the upper segment of the storage layer is substantially coplanar with a bottom surface of the first portion of the oxide layer.
Lee teaches a bottom surface of an upper segment (Item DL2) of a storage layer (Item DL) is substantially coplanar with a bottom surface of a first portion (Item P1) of an oxide layer (Item P1/P2).
It would have been obvious to one having ordinary skill in the at before the effective filing date of the claimed invention to have a bottom surface of the upper segment of the storage layer is substantially coplanar with a bottom surface of the first portion of the oxide layer because this configuration adequately allows for contact between a channel layer and a doped polysilicon layer (Lee Paragraph 0039).
Examiner’s Note: The Examiner notes that the term “substantially coplanar” allows for the bottom surface of the upper segment of the storage layer to be slightly above the bottom surface of the first oxide layer.
Regarding claim 27, the combination of Tran and Greenlee teaches all of the elements of the claimed invention as stated above except where a bottom surface of the upper segment of the storage layer is higher than a bottommost surface of the oxide layer.
Lee teaches where a bottom surface of an upper segment (Item DL2) of a storage layer (Item DL) is higher than a bottommost surface of an oxide layer (Item P1/P2).
It would have been obvious to one having ordinary skill in the at before the effective filing date of the claimed invention to have a bottom surface of the upper segment of the storage layer be higher than a bottommost surface of the oxide layer because this configuration adequately allows for contact between a channel layer and a doped polysilicon layer (Lee Paragraph 0039).
Response to Arguments
Applicant's arguments filed 04/18/2025 have been fully considered but they are not persuasive.
The Applicant argues that Tran does not teach where the conductive layer (identified by the Examiner as Item 17 of Tran) comprises tungsten.
More specifically, the Applicant points to the teaching in paragraph 0024 in Tran of Item 17 being polysilicon and states that the polysilicon is used such that there is etch selectivity to the material of the wordline tiers and the select gate tiers. While the Examiner agrees that paragraph 0024 teaches that item 17 is polysilicon, the Examiner avers that the Tran reference, specifically in paragraphs 0014 and 0015, recognizes that the conductively doped semiconductive material is merely one example of a material of item 17. In actuality, while not all embodiments are shown explicitly in the drawings, paragraph 0014 offers many different embodiments in which the select gate structure SGS has many different configurations of the semiconductive material and conductive metal material (tungsten). Paragraph 0014 specifically states “Regardless, in one embodiment stack 15 comprises both conductive metal material and conductively-doped semiconductive material (e.g., conductively-doped polysilicon) in different ones of the select gate tiers in a finished circuitry construction. In one embodiment, the conductive metal material is above the conductively-doped semiconductive material in the finished circuitry construction, and in another embodiment the conductive metal material is below the conductively-doped semiconductive material in the finished circuitry construction. If there are three or more select gate tiers (not shown in FIG. 1), the conductive metal material may be both above and below the conductively-doped semiconductive material in the finished circuitry construction and/or the conductively-doped semiconductive material may be both above and below the conductive metal material.” Further, paragraph 0015 also reinforces the idea that Tran recognizes that either of a semiconductive material or metal material (tungsten) may be used for the select gate tiers. Further, the method recited in paragraph 0024 is only one means by which the layers are etch. As the claims are not directed to a method but are directed to a device, and the possibility of other methods exist such that, should a tungsten be used as Item 17, other methods would be available to form the device, the use of tungsten would not render the device unable to function an intended. The Applicant also points to the teaching in paragraph 0025 where the select gate tier 14 is made of tungsten and/or semiconductive material and does not explicitly state that Item 17 is tungsten. As stated above, the semiconductive material being the material for Item 17 is merely one example of the material that could be used. Further, as highlighted above, Paragraph 0024 states that many different configurations of a semiconductive material and conducting metal (tungsten) are anticipated by Tran such that one having ordinary skill in the art would recognize that in some embodiments item 17 would comprise tungsten. As such, the Examiner does not find the Applicant’s arguments persuasive and maintains the reliance on Tran to teach and render obvious the conductive layer, Item 17, being tungsten.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891