DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/13/2026 has been entered.
Response to Amendment
This office action is responsive to amendment filed on 04/23/2026. Claims 1-10 and 12-20 are pending. The amendment have overcome the specification objection, drawing objection, rejection under 35 U.S.C. 112(a) and 112(b) as set forth in the previous office action.
Response to Arguments
In response to Applicant’s argument regarding rejection under 35 U.S.C. 101 on page 15-17 that the claimed invention improves upon conventional function of a computer, or upon conventional technology or technological processes as described in [0002] and [0017] of the specification, and applicant submits that one of ordinary skill in the art would understand that optimizing processing improves technology such that it conserves computing resources that would have otherwise been consumed in view of the conventional format conversion techniques can result in increased converted data size and/or require a redundant buffer especially with effects of alignment required for accelerators.
Examiner respectfully disagrees because any arguably improvements, such as reducing converted data size or redundant buffer, are a direct consequence of performing the mathematical concept as recited in the claim or described in figure 2. [0002] describes “conventional format conversion techniques can result in increased converted data size and/or require a redundant buffer especially with effects of alignment required for accelerators. Accordingly, there is a need for an improved format conversion technique for accelerators.” Thus, any arguably improvement is a result of performing the format conversion technique or the mathematical algorithm to convert data format to a format that compatible with hardware accelerator. MPEP 2106.05(a) recites “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements”. In other words, an improved format conversion technique or a mathematical algorithm to convert data shape and format alone cannot provide the improvement.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-10 and 12-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Claim 1 recites a computer implemented method for converting data.
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites a method for converting a shape and a format of tensor data to meet a specific data format comprising: calculating an n-dimension modified shape of the input tensors by (a) setting S1; (b) setting S2; (c) setting S3 to ((Xn x Xn-1 x Xn-2 x ... x X1) / (S1 x S2)); and (d) returning the n-dimension modified shape as < S3 x S2 x S1 >; wherein each of the input tensors comprises a data format of < X x Y x Z >, and wherein each of the input tensors further comprising an n-dimension input tensor shape as < Xn x Xn-1 x Xn-2 x ... x X1 > ; changing the n-dimension input tensor shape of the input tensors to the n-dimension modified shape to obtain shape modified input tensors; converting a data format of the shape modified input tensors from <X x Y x Z> to < X x (Y ceildiv D) x (Z ceildiv D) x D x D > to obtain format and shape converted input tensors having the specific data format, where D is a constant value of a last dimension Z of the input tensors, and executing target operations on the format and shape converted input tensors to obtain result tensors. Such limitations cover mathematical calculations, relationship, and/or formula (e.g., calculating an n-dimension modified shape by performing steps a-d, changing and converting data format and perform target element-wise operations to obtain result as recited in the claims or steps illustrated in figures 2-4 [0035-0053]). Therefore, the claim includes limitations that fall within the “Mathematical Concepts” groupings of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim recites the additional elements a computer-implemented method and a hardware accelerator. However, these elements are recited at a high level of generality, i.e., as computer components performing computer functions of processing data. Accordingly, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer elements. The claim additionally recites steps of receiving input tensors and storing the n-dimension input tensor shape. However, such steps are recited at a high level of generality and at most considered as insignificant extra solution activity because such steps amount to mere data gathering (see MPEP 2106.05(g)). The claim further recites S1 and S2 are values selected such that input tensors are compatible with the hardware accelerator and converting data format to enable use of the hardware accelerator, such limitation merely recite a result of performing the abstract idea, such as calculating an n-dimension modified shape that includes setting S1 and S2 to generate result that is compatible with the hardware accelerator and converting data. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a generic component. The same conclusion is reached in step 2B, i.e., mere instruction to apply an exception on a computer element cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The step of receiving data and storing data are considered to be insignificant extra-solution activity in step 2A, and are determined to be well-understood, routine, conventional activity in the field. Court decisions cited in MPEP 2106.05(d)(II) section (i), indicate that mere receiving or transmitting data over a network, and (iv) storing data are well-understood, routing, conventional function when they are claimed in a merely generic manner. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 further recites converting the result tensors from < X x (Y ceildiv D) x (Z ceildiv D) x D x D > to <X x Y x Z> to obtain format converted result tensors; and recovering the stored n-dimension input tensor shape for the format converted result tensors to obtain original shaped format converted result tensors. Such limitations cover mathematical calculations, relationship, and/or formula (converting the converted data back to the original format for further processing). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 3-4 further recites the format converted result tensors have a format compatible with a central processing unit and incompatible with the hardware accelerator, and processing, by the central processing unit, the format converted result tensors. Such limitation merely describes the format of the converted result tensors to have a specific format and process the format converted result tensors, which covers the mathematical calculations, relationship, and/or formula under step 2A prong one. The claim further recites a central processing unit and the hardware accelerator. However, such additional elements are recited at a high level of generality, e.g., computer components performing computer function of processing data having a compatible format. Thus, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer elements. Accordingly, The claims do not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claim 5 further recites wherein the converting the data format converts the data format to have a same number of constituent elements. Such limitations cover mathematical calculations, relationship, and/or formula (converting data to have a same number of elements). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101
Claims 6-8 further recites wherein the hardware accelerator is a graphics processing unit, or the hardware accelerator is comprised in a central processing unit, or the hardware accelerator is a tensor processing unit. Such additional elements are recited at a high level of generality, i.e., as a computer component performing a computer function of processing data. thus, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer elements. Therefore, the claims do not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claims are not patent-eligible under 35 U.S.C. 101.
Claims 9 and 13 further recites wherein a last input tensor and a second to last input tensor is comprised in a sequence of tensors or wherein an input tensor of the input tensors is a last input tensor. Such limitations cover mathematical calculations, relationship, and/or formula, such as describing the input tensors are in sequence. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 10 further recites a number of data elements in each of the input tensors and each of the result tensors are equal. Such limitations cover mathematical calculations, relationship, and/or formula, such as describing number of elements input data and output data are equal. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 12 further recites the hardware accelerator is constrained to only handle constant size arrays. Such additional element is recited at a high level of generality, e.g., computer components performing computer functions and the component would have constrained to handle certain data size. Thus, such additional element fails to provide a meaningful limitation on the claim invention, and amounts to no more than mere instructions to apply the exception using computer element, and also fails to integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 14-19 recite product claims having similar limitations as the method claims 1-6. Thus, they are rejected for the same reasons. Claim 14 further recites a computer program product, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method, the claim further recites a central processing unit (CPU). However, such additional elements are recited at a high level of generality, e.g., computer components performing computer functions of storing and executing program instructions to perform mathematical operations. Thus, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer element. Therefore; The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 20 recites an apparatus claim that would practice the method claim 1. Thus, it is rejected for the same reasons. Claim 20 further recites a computer processing system, comprising: a memory device for storing program code; a central processing unit operatively coupled to the memory device for running the program code; and a hardware accelerator operatively coupled to the memory device and the central processing unit. However, such additional elements are recited at a high level of generality, e.g., computer components performing computer functions of storing and executing program instructions to perform mathematical operations. Thus, such additional elements fail to provide a meaningful limitation on the claim invention, and amount to no more than mere instructions to apply the exception using computer element. Therefore; The claim does not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
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