Prosecution Insights
Last updated: October 27, 2026
Application No. 17/528,733

MULTI-LAYER INTERCONNECT COMPRISING LOW RESISTIVITY FIRST METAL LAYER BETWEEN SECOND METAL LAYER AND THIS METAL LAYER

Final Rejection §103
Filed
Nov 17, 2021
Examiner
MALSAWMA, LALRINFAMKIM HMAR
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
1013 granted / 1121 resolved
+22.4% vs TC avg
Moderate +8% lift
Without
With
+8.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
29 currently pending
Career history
1151
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
43.1%
+3.1% vs TC avg
§102
35.8%
-4.2% vs TC avg
§112
10.2%
-29.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1121 resolved cases

Office Action

§103
CTFR 17/528,733 CTFR 77428 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1-13, 18-20, 22 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2012/0313063 A1; hereinafter, “ Wang ”) . Regarding claim 1: Wang discloses a memory device including: a three dimensional crosspoint memory array (Fig. 1, [0036]) comprising a plurality of memory cells 112 (Fig. 1 and [0036]) and a plurality of access lines 102/204 (Fig. 4A, [0036], [0045]) coupled to the plurality of memory cells, wherein an access line of the plurality of access lines comprises a first metal layer 204B (Fig. 4A, [0049]) between and in contact with a second metal layer 204C (Fig. 4A, [0049]) and a third metal layer 204A (Fig. 4A, [0049]), wherein the first metal layer 204B ( e.g., comprising aluminum, [0058, lines 27-30] ) has a resistivity that is lower than a resistivity of the second metal layer 204C ( e.g., tungsten, [0056] ) and a resistivity of the third metal layer 204A ( e.g., tungsten, [0053] ), wherein the second 204C and third 204A metal layers have thicknesses greater than 1 nanometer and less than 10 nanometers [0.5 nanometer and less than 3 nanometers] [0054, 0056] and wherein the first metal layer 204B has a thickness greater than 10 nanometers and less than 200 nanometers nanometers [0.5 nanometer and less than 3 nanometers] [0059]. Wang discloses ranges in thickness that fall within the claimed ranges. Although Wang does not disclose the entire range(s) claimed, the current claim is deemed obvious because one of ordinary skill in the art would have been able to increase the ranges in thickness without extensive experimentation, wherein thicker layers would ensure that each of the layers will sufficiently covers an underlying layer. Regarding claims 2-13, 18-20, 22 and 23: re claim 2, Wang discloses the memory device of claim 1, wherein the first metal layer 204B comprises aluminum ( aluminum, [0058, lines 27-30] ); re claim 3, Wang discloses the memory device of claim 2, wherein the second metal layer 204C and the third metal layer 204A are tungsten [0053, 0059]; accordingly, when the layers are tungsten, at least 99% of atoms of the second metal layer and the third metal layer will be tungsten; re claim 4, Wang discloses the memory device of claim 1, wherein the second metal layer 204C and the third metal layer 204A comprises one of ruthenium, tantalum, or iridium [0053, 0056]; re claim 5, Wang discloses the memory device of claim 2, wherein the second metal layer 204C and the third metal layer 204A comprises ruthenium [0053, 0056], accordingly, when the layers are ruthenium, at least 99% of atoms of the second metal layer and the third metal layer will be ruthenium; re claim 6, Wang discloses the memory device of claim 1, wherein the first metal layer, second metal layer, and third metal layer are etchable ( i.e., the materials disclosed by Wang are etchable ); re claim 7, Wang discloses the memory device of claim 1, wherein the first metal layer 204B includes a metal ( e.g., “tantalum” in tantalum-oxide, [0058] ) that is soluble to a metal of the second metal layer 204A and third metal layer 204C ( e.g., both layers can be titanium, [0053, 0056] ), wherein less than 5% of atoms of the first metal layer ( e.g., tantalum ) form an intermetallic with the second metal layer ( e.g., titanium, i.e., tantalum is highly soluble to titanium but doesn’t form an intermetallic with titanium ); re claim 8, Wang discloses the memory device of claim 1, wherein a thickness of the first metal layer 204B [could be readily chosen to be] greater than a thickness of the second metal layer 204C and a thickness of the third metal layer 204B ( Wang discloses thickness ranges for each of the three layers that one of ordinary skill in the art would have been able to easily implement as desired; accordingly, specifically incorporating a larger thickness for the first metal layer 204B is deemed to be an obvious matter of finding an optimum or workable range in thicknesses that one of ordinary skill in the art would have been able to determine without extensive experimentation ); re claim 9, Wang discloses the memory device of claim 1, wherein the access line is a bitline or a wordline (Fig. 1 and [0036]); re claim 10, Wang discloses the memory device of claim 1, further comprising a plurality of memory chips [0036] ( e.g., array 100 may be part of a larger device or integrated circuit ), wherein a first memory chip comprises the three dimensional crosspoint memory array; re claim 11, Wang discloses the memory device of claim 10, further comprising a memory controller to communicate with the plurality of memory chips ( i.e., a system of chip will comprise a controller, [0036] ); and re claims 12 and 13, Solid state drives and dual in-line memory modules were very well known in the art at the time of the current invention; accordingly, it would have be obvious to one of ordinary skill in the art to incorporate Wang’s memory device into a solid state drive or a dual in-line memory module; re claims 18, 22 and 23, Initially, the current claims are similar to claim 5 ( which has been addressed in detail hereinbefore ), except that the current claims are essentially broader in scope than claim 5. Wang discloses all limitations in the current claims except for explicitly disclosing at least 99% of the second metal layer and the third metal layer are one of tungsten, ruthenium, tantalum, or iridium. However, Wang discloses the second metal layer 204C and the third metal layer 204A can be one of tungsten, ruthenium, tantalum, or iridium [0053, 0056] among other metals. Therefore, it would have been obvious to one of ordinary skill in the art to specifically incorporate essentially pure layers of tungsten, ruthenium, tantalum, or iridium because Wang discloses such metals, and specifically incorporating such metal in pure form could reduce process complexity and cost in comparison to forming alloys of such metals. re claims 19 and 20, Initially, the current claims are essentially directed to a common apparatus (e.g., a smart TV) that incorporates resistive memory devices; accordingly, the current claims are deemed obvious because Wang’s resistive memory device is well suited for such an apparatus. Therefore, it would have been obvious to one of ordinary skill in the art to incorporate Wang’s resistive memory device in a smart TV to provide the memory capacity required by such an apparatus . 07-21-aia AIA Claim (s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Reznicek et al. (US 2019/0189918 A1; hereinafter, “ Reznicek ”) . Wang renders obvious claim 18 but is silent as to whether or not the interconnect comprises a BEOL interconnect. Reznicek discloses there is a need for resistive memory devices, similar to that of Wang, that are compatible with BEOL structures and techniques. It would have been obvious to one of ordinary skill in the art to specifically incorporate Wang’s interconnect as a BEOL interconnect because Reznicek teaches the is a need for resistive memory devices to be compatible with BEOL structures and techniques. Remarks The objection to the title is withdrawn in view of the amendment. Claims 14-17 remain withdrawn from consideration. Applicant’s remarks/arguments have been carefully reviewed and considered; however, they are moot in view of the new grounds of rejections. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEX H MALSAWMA/Primary Examiner, Art Unit 2892 Application/Control Number: 17/528,733 Page 2 Art Unit: 2892 Application/Control Number: 17/528,733 Page 3 Art Unit: 2892 Application/Control Number: 17/528,733 Page 4 Art Unit: 2892 Application/Control Number: 17/528,733 Page 5 Art Unit: 2892 Application/Control Number: 17/528,733 Page 6 Art Unit: 2892 Application/Control Number: 17/528,733 Page 7 Art Unit: 2892 Application/Control Number: 17/528,733 Page 8 Art Unit: 2892
Read full office action

Prosecution Timeline

Nov 17, 2021
Application Filed
Oct 17, 2022
Response after Non-Final Action
Jun 18, 2025
Non-Final Rejection mailed — §103
Nov 18, 2025
Response Filed
Oct 06, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772680
DISPLAY DEVICE
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DISPLAY APPARATUS
3y 2m to grant Granted Oct 20, 2026
Patent 12765188
DISPLAY APPARATUS
2y 11m to grant Granted Oct 13, 2026
Patent 12757383
MEMORY CELL WITH REDUCED PARASITIC CAPACITANCE AND METHOD OF MANUFACTURING THE SAME
2y 6m to grant Granted Oct 06, 2026
Patent 12757384
MEMORY CELL WITH REDUCED PARASITIC CAPACITANCE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+8.1%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1121 resolved cases by this examiner. Grant probability derived from career allowance rate.

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