DETAILED ACTION
This action is in response to the application filed 11/17/2021. Claims 1-20 are pending and have been examined.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/02/2025 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: “parallel processors configured to: … selectively loading a plurality of synaptic weights”. “selectively loading” should be “selectively load”. Appropriate correction is required.
Claim 3 is objected to because of the following informalities: “the plurality of parallel processors are further configured” should be “the plurality of parallel processors is further configured”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap" in its fourth limitation. There is insufficient antecedent basis for “the bitmap” in the claim. This rejection is inherited by dependent claims 2-9. ‘the bitmask’ and ‘the bitmap’ are interpreted as being interchangeable.
Claim 16 recites the limitation “wherein reading a plurality of synaptic weights from memory further comprises”. There’s no ‘reading a plurality of synaptic weights’ defined prior to this, thus there’s insufficient antecedent basis in the claim. This is interpreted as referring to “selectively loading a plurality of synaptic weights” from the parent claim 10.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed inventions are directed to non-statutory subject matter without significantly more.
Claim 1
Step 1: The claim recites “A device”, and is therefore directed to the statutory category of article of manufacture
Step 2A Prong 1: The claim recites the following judicial exception(s)
compute a time delta vector based on a post-synaptic timestamp vector and a pre-synaptic spike timestamp: This can be performed as a mental process. One can simply subtract the scalar pre-synaptic spike timestamp from the vector of post-synaptic timestamps.
calculate a long-term depression (LTD) value based on the time delta vector: This utilizes a mathematical concept. One can simply derive a negative value from one of the time delta vector entries.
generate a bitmask based on an evaluation of the time delta vector: This can be performed as a mental process. One can merely observe the time delta vector and imagine a bitmask corresponding to it.
compute a second time delta vector based on a pre-synaptic timestamp vector and the pre-synaptic spike timestamp: This can be performed as a mental process. One can simply subtract the scalar pre-synaptic spike timestamp from the vector of pre-synaptic timestamps.
calculate a long-term potentiation (LTP) value based on the second time delta vector: This utilizes a mathematical concept. One can simply derive a positive value from one of the second time delta vector entries.
adjust a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector: This can be performed as a mental process. One can simply add the LTD and LTP values to the synaptic weight vector.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the following additional element(s)
A device comprising: parallel processors configured to: This is mere instruction to apply the recited judicial exceptions with generic parallel computing hardware (MPEP 2106.05(f)).
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap: This amounts to mere reception of data and is insignificant extra-solution activity (MPEP 2106.05(g)).
write the updated synaptic weight vector to the memory or another memory or storage device: This amounts to mere data storage and is insignificant extra-solution activity (MPEP 2106.05(g)).
Step 2B: The following additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
A device comprising: parallel processors configured to: This is mere instruction to apply the recited judicial exceptions with generic parallel computing hardware (MPEP 2106.05(f)).
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap: This is an instance of retrieving information from memory, a limitation known to be well-understood, routine, and conventional (MPEP 2106.05(d) II. iv.)
write the updated synaptic weight vector to the memory or another memory or storage device: This is an instance of storing information in memory, a limitation known to be well-understood, routine, and conventional (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93).
Claim 2
Step 1: The claim recites an article of manufacture, as in claim 1
Step 2A Prong 1: The claim recites no further judicial exception(s)
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the further additional element(s)
the pre-synaptic spike timestamp is received via one of a response to a dedicated instruction or via a broadcast operation: This amounts to mere data transmission and is insignificant extra-solution activity (MPEP 2106.05(g)).
Step 2B: The further additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
the pre-synaptic spike timestamp is received via one of a response to a dedicated instruction or via a broadcast operation: This is an instance of retrieving information from memory, a limitation known to be well-understood, routine, and conventional limitation (MPEP 2106.05(d) II. iv.).
Claim 3
Step 1: The claim recites an article of manufacture, as in claim 1
Step 2A Prong 1: The claim recites the following further judicial exception(s)
wherein the plurality of parallel processors are further configured to use the time delta vector as an enabling gate for computing the second time delta vector and the LTP value can be performed as a mental process. One can selectively calculate second time delta entries corresponding to positive values in the first time delta vector.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the further additional element(s)
wherein the plurality of parallel processors are configured to use the time delta vector as an enabling gate for the second time delta vector and the LTP value: This constitutes mere instruction to apply judicial exceptions with generic computer hardware (MPEP 2106.05(f)).
Step 2B: The further additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
wherein the plurality of parallel processors are configured to use the time delta vector as an enabling gate for the second time delta vector and the LTP value: This constitutes mere instruction to apply judicial exceptions with generic computer hardware (MPEP 2106.05(f)).
Claim 4
Step 1: The claim recites an article of manufacture, as in claim 1
Step 2A Prong 1: The claim recites the following further judicial exception(s)
calculating the LTD value comprises computing the LTD value according to:
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wherein
t
∆
comprises the time delta vector and
A
_
and
τ
_
are constant utilizes a mathematical concept, claiming the usage of a specific formula.
calculating the LTP value comprises computing the L TP value according to:
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wherein
t
∆
comprises the second time delta vector and
A
+
and
τ
+
are constant utilizes a mathematical concept, claiming the usage of a specific formula.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the additional element(s).
Step 2B: The additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s).
Claim 5
Step 1: The claim recites an article of manufacture, as in claim 4
Step 2A Prong 1: The claim recites no further judicial exception(s)
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the further additional element(s)
wherein calculating the LTD value comprises issuing a single single-instruction multiple data (SIMD) instruction: This is mere instruction to execute a judicial exception with a generic SIMD instruction (MPEP 2106.05(f)).
Step 2B: The further additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
wherein calculating the LTD value comprises issuing a single single-instruction multiple data (SIMD) instruction: This is mere instruction to execute a judicial exception with a generic SIMD instruction (MPEP 2106.05(f)).
Claim 6
Step 1: The claim recites an article of manufacture, as in claim 1
Step 2A Prong 1: The claim recites no further judicial exception(s)
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the further additional element(s)
calculating the LTD value comprises issuing a plurality of SIMD instructions: This is mere instruction to execute a judicial exception with generic SIMD instructions (MPEP 2106.05(f)).
Step 2B: The further additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
calculating the LTD value comprises issuing a plurality of SIMD instructions: This is mere instruction to execute a judicial exception with generic SIMD instructions (MPEP 2106.05(f)).
Claim 7
Step 1: The claim recites an article of manufacture, as in claim 1
Step 2A Prong 1: The claim recites no further judicial exception(s)
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the further additional element(s)
wherein selectively loading a plurality of synaptic weights from memory further comprises selective loading the plurality of synaptic weights using both the time delta vector and a stored bitmask: Selectively loading weights still amounts to mere reception of data and is insignificant extra-solution activity (MPEP 2106.05(g)).
Step 2B: The further additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
wherein selectively loading a plurality of synaptic weights from memory further comprises selective loading the plurality of synaptic weights using both the time delta vector and a stored bitmask: Selectively loading weights is still an instance of retrieving information from memory, a limitation known to be well-understood, routine, and conventional (MPEP 2106.05(d) II. iv.).
Claim 8
Step 1: The claim recites an article of manufacture, as in claim 1
Step 2A Prong 1: The claim recites the following further judicial exception(s)
wherein LTD and LTP values are calculated based on additional synaptic parameters including a current synaptic weight value: This is still utilizing a mathematical concept. One could simply calculate a linear combination of a time delta value, a current synaptic weight value, and some other numerical synaptic parameter.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the additional element(s).
Step 2B: The additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s).
Claim 9
Step 1: The claim recites an article of manufacture, as in claim 1
Step 2A Prong 1: The claim recites the following further judicial exception(s)
wherein adjusting a current synaptic weight vector comprises:
adjusting the current synaptic weight vector based on the LTP value to generate a first adjusted synaptic weight vector: This can be performed as a mental process. One can simply add the LTP value to the synaptic weight vector.
adjusting the first adjusted synaptic weight vector based on the LTD value to generate the updated synaptic weight vector: This can be performed as a mental process. One can simply add the LTD value to the first adjusted synaptic weight vector.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the further additional element(s)
accumulating synaptic currents based on a membrane potential vector and the first adjusted synaptic weight vector amounts to mere data gathering and is insignificant extra-solution activity (MPEP 2106.05(g)).
Step 2B: The further additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
accumulating synaptic currents based on a membrane potential vector and the first adjusted synaptic weight vector is an instance of retrieving information from memory, a limitation known to be well-understood, routine, and conventional (MPEP 2106.05(d) II. iv.)
Claim 10
Step 1: The claim recites “A method”, and is therefore directed to the statutory category of process
Step 2A Prong 1: The claim recites the following judicial exception(s)
computing a time delta vector based on a post-synaptic timestamp vector and a pre-synaptic spike timestamp: This can be performed as a mental process. One can simply subtract the scalar pre-synaptic spike timestamp from the vector of post-synaptic timestamps.
calculating a long-term depression (LTD) value based on the time delta vector: This utilizes a mathematical concept. One can simply derive a negative value from one of the time delta vector entries.
generating a bitmask based on an evaluation of the time delta vector: This can be performed as a mental process. One can merely observe the time delta vector and imagine a bitmask corresponding to it.
computing a second time delta vector based on a pre-synaptic timestamp vector and the pre-synaptic spike timestamp: This can be performed as a mental process. One can simply subtract the scalar pre-synaptic spike timestamp from the vector of pre-synaptic timestamps.
calculating a long-term potentiation (LTP) value based on the second time delta vector: This utilizes a mathematical concept. One can simply derive a positive value from one of the second time delta vector entries.
adjusting a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector: This can be performed as a mental process. One can simply add the LTD and LTP values to the synaptic weight vector.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the following additional element(s)
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap: This amounts to mere reception of data and is insignificant extra-solution activity (MPEP 2106.05(g)).
writing the updated synaptic weight vector to the memory or another memory or storage device: This amounts to mere data storage and is insignificant extra-solution activity (MPEP 2106.05(g)).
Step 2B: The following additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap: This is an instance of retrieving information from memory, a limitation known to be well-understood, routine, and conventional (MPEP 2106.05(d) II. iv.)
writing the updated synaptic weight vector to the memory or another memory or storage device: This is an instance of storing information in memory, a limitation known to be well-understood, routine, and conventional (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93).
Claims 11-18
Step 1: Claims 11-18 recite a process, as in claim 10
Step 2A Prong 1: Claims 11-18 recite the same judicial exception(s) as claims 2-9, respectively.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through any additional elements. The analysis of claims 11-18 at this step mirrors that of claims 2-9, respectively, with the exception that claims 2-9 are directed to a “device comprising: parallel processors configured to [perform operations]”, said operations mirroring those of claims 11-18. This is a mere instruction to apply the exceptions using generic computer equipment (MPEP 2106.05(f)).
Step 2B: The additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s). The analysis of claims 11-18 at this step mirrors that of claims 2-9, with the exception that claims 2-9 are directed to a “device comprising: parallel processors configured to [perform operations]”, said operations mirroring those of claims 11-18. This is mere instruction to apply the exceptions using generic computer equipment (MPEP 2106.05(f)).
Claim 19
Step 1: The claim recites “A non-transitory computer-readable storage medium”, and is therefore directed to the statutory category of article of manufacture
Step 2A Prong 1: The claim recites the following judicial exception(s)
computing a time delta vector based on a post-synaptic timestamp vector and a pre-synaptic spike timestamp: This can be performed as a mental process. One can simply subtract the scalar pre-synaptic spike timestamp from the vector of post-synaptic timestamps.
calculating a long-term depression (LTD) value based on the time delta vector: This utilizes a mathematical concept. One can simply derive a negative value from one of the time delta vector entries.
generating a bitmask based on an evaluation of the time delta vector: This can be performed as a mental process. One can merely observe the time delta vector and imagine a bitmask corresponding to it.
computing a second time delta vector based on a pre-synaptic timestamp vector and the pre-synaptic spike timestamp: This can be performed as a mental process. One can simply subtract the scalar pre-synaptic spike timestamp from the vector of pre-synaptic timestamps.
calculating a long-term potentiation (LTP) value based on the second time delta vector: This utilizes a mathematical concept. One can simply derive a positive value from one of the second time delta vector entries.
adjusting a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector: This can be performed as a mental process. One can simply add the LTD and LTP values to the synaptic weight vector.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through the following additional element(s)
A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor: This constitutes mere instruction to apply a judicial exception with a generic computer (MPEP 2106.05(f)).
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap: This amounts to mere reception of data and is insignificant extra-solution activity (MPEP 2106.05(g)).
writing the updated synaptic weight vector to the memory or another memory or storage device: This amounts to mere data storage and is insignificant extra-solution activity (MPEP 2106.05(g)).
Step 2B: The following additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s)
A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor: This constitutes mere instruction to apply a judicial exception with a generic computer (MPEP 2106.05(f)).
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap: This is an instance of retrieving information from memory, a limitation known to be well-understood, routine, and conventional (MPEP 2106.05(d) II. iv.)
writing the updated synaptic weight vector to the memory or another memory or storage device: This is an instance of storing information in memory, a limitation known to be well-understood, routine, and conventional (Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93).
Claim 20
Step 1: Claim 20 recites an article of manufacture, as in claim 19
Step 2A Prong 1: Claim 20 recites the same judicial exception(s) as claim 18.
Step 2A Prong 2: The judicial exception(s) are not integrated into a practical application through any additional elements. The analysis of claim 20 at this step mirrors that of claim 18, with the exception that claim 20 is directed to “A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor”, said instructions mirroring those of claim 18. This is a mere instruction to apply the exceptions using generic computer equipment (MPEP 2106.05(f)).
Step 2B: The additional element(s) of the claim, taken alone or in combination, do not amount to significantly more than the recited judicial exception(s). The analysis of claim 20 at this step mirrors that of claim 18, with the exception that claim 20 is directed to “A non-transitory computer-readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor”, said instructions mirroring those of claim 18. This is mere instruction to apply the exceptions using generic computer equipment (MPEP 2106.05(f)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness
Claims 1, 3-4, 7, 9-10, 12-13, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Taherkhani et al. (A review of learning in biologically plausible spiking neural networks, published 2020, Neural Networks 122 (2020) 253–272), hereafter referred to as Taherkhani, in view of Arthur et al. (TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION, published 2014, US 2014/0180984 A1), hereafter referred to as Arthur.
Regarding claim 1, Taherkhani teaches a method for a computer to:
compute a time delta vector based on a post-synaptic timestamp vector and a pre-synaptic spike timestamp: “If the time interval between the pre- and postsynaptic spike is
t
(time delta)
=
t
p
o
s
t
(post-synaptic timestamp)
-
t
p
r
e
(pre-synaptic spike timestamp) and t > 0 then the synaptic weight will be potentiated” (Taherkhani, page 255, Left column, paragraph 4).
calculate a long-term depression (LTD) value based on the time delta vector: “[I]f a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
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(long-term depression value), where A_ represents the maximum depression” (Taherkhani, page 255, Left column, paragraph 5). This value is dependent on t, the time delta.
compute a second time delta vector based on a pre-synaptic timestamp vector and the pre-synaptic spike timestamp: “If the time interval between the pre- and postsynaptic spike is
t
(time delta)
=
t
p
o
s
t
(current timestamp)
-
t
p
r
e
(pre-synaptic timestamp) and t > 0 then the synaptic weight will be potentiated” (Taherkhani, page 255, Left column, paragraph 4).
calculate a long-term potentiation (LTP) value based on the second time delta vector: “The magnitude of the potentiation is a function of t (time delta) which decays exponentially with a time constant τ+ and can be calculated by
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(long-term potentiation value)” (Taherkhani, page 255, Left column, paragraph 5).
adjust a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
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(LTP value), where A+ is the maximum synaptic change. Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
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(LTD value), where A− represents the maximum depression, and τ− is a time constant” (Taherkhani, page 255, Left column, paragraph 5).
Taherkhani relates to spiking neural networks and is analogous to the claimed invention.
While Taherkhani fails to disclose the further limitations of the claim, Arthur teaches [a] device comprising: parallel processors: “The processors 150 of the neurosynaptic module 100 run in parallel.” (Arthur, [0037])
The parallel processors configured to:
generate a bitmask based on an evaluation of the time delta vector:
“Each synapse 31 has a synaptic weight. The synaptic weights of the synapses 31 of the core circuit 10 may be represented by a weight matrix W (stored bitmask), wherein an element
W
i
j
of the matrix W represents a synaptic weight of a synapse 31 located at a row/axon path i and a column/dendrite path j of the crossbar 12. In one embodiment, the synapses 31 are binary memory devices. Each synapse 31 can have a weight "0" indicating that said synapse 31 is non-conducting, or a weight "1" indicating that said synapse 31 is conducting.” (Arthur, [0032])
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004])
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap; … and write the updated synaptic weight vector to the memory or another memory or storage device:
“Synaptic weights may be read from, and written to, the memory array 160, in both horizontal and vertical directions for enhanced learning operation. The synaptic weights maintained may be updated based on a learning rule, and/or the firing activity of a corresponding neuron 11.” (Arthur, [0064])
“Each synapse 31 has a synaptic weight. The synaptic weights of the synapses 31 of the core circuit 10 may be represented by a weight matrix W (stored bitmask), wherein an element
W
i
j
of the matrix W represents a synaptic weight of a synapse 31 located at a row/axon path i and a column/dendrite path j of the crossbar 12. In one embodiment, the synapses 31 are binary memory devices. Each synapse 31 can have a weight "0" indicating that said synapse 31 is non-conducting, or a weight "1" indicating that said synapse 31 is conducting. A learning rule such as spike-timing dependent plasticity (STDP) may be applied to update the synaptic weights of the synapses 31.” (Arthur, [0032]). The bitmask keeps track of which synaptic weights have conducted in a given time step.
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004])
Arthur relates to neuromorphic neural networks and is analogous to the claimed invention. Taherkhani teaches a method of performing STDP calculations. The claimed invention improves upon this method by executing it on real hardware with selective loading of synaptic weights based on a bitmask and a time delta. Arthur teaches the use of neuromorphic computer hardware to selectively load and update synaptic weights based on each weight’s conductance time relative to a given timestep (tracked with a bitmask), applicable to Taherkhani’s device. A person of ordinary skill in the art would have recognized that selectively loading weights using bitmasks would lead to the predictable result of fewer load operations, and would improve the known device by saving power consumption and cycles associated with the transfer and loading of data, particularly when the conducting weights are sparse. (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 3, the rejection of claim 1 in view of Taherkhani and Arthur is incorporated. Taherkhani further teaches a method, wherein the plurality of parallel processors are further configured to use the time delta vector as an enabling gate for computing the second time delta vector and the LTP value: “According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t (time delta) = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
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(LTP value) ... Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
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” (Taherkhani, page 255, Left column, paragraph 5). Potentiation occurs only when the time delta is greater than zero. Thus, the time delta is used as an enabling gate for computing the LTP value.
Regarding claim 4, the rejection of claim 1 in view of Taherkhani and Arthur is incorporated. Taherkhani further teaches a method, wherein
calculating the LTD value comprises computing the LTD value according to
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wherein
τ
∆
comprises the time delta vector and A_ and
τ
_ are constant: “[I]f a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
, where A_ represents the maximum depression” (Taherkhani, page 255, Left column, paragraph 5).
calculating the LTP value comprises computing the LTP value according to:
PNG
media_image6.png
60
80
media_image6.png
Greyscale
wherein
τ
∆
comprises the second time delta vector and
A
+
and
τ
+
are constant: “The magnitude of the potentiation is a function of t (time delta) which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
, where A+ is the maximum synaptic change” (Taherkhani, page 255, Left column, paragraph 5).
Regarding claim 7, the rejection of claim 1 in view of Taherkhani and Arthur is incorporated. Arthur further teaches a method, wherein selectively loading a plurality of synaptic weights from memory further comprises selective loading the plurality of synaptic weights using both the time delta vector and a stored bitmask:
“Each synapse 31 has a synaptic weight. The synaptic weights of the synapses 31 of the core circuit 10 may be represented by a weight matrix W (stored bitmask), wherein an element
W
i
j
of the matrix W represents a synaptic weight of a synapse 31 located at a row/axon path i and a column/dendrite path j of the crossbar 12. In one embodiment, the synapses 31 are binary memory devices. Each synapse 31 can have a weight "0" indicating that said synapse 31 is non-conducting, or a weight "1" indicating that said synapse 31 is conducting. A learning rule such as spike-timing dependent plasticity (STDP) may be applied to update the synaptic weights of the synapses 31.” (Arthur, [0032]). The bitmask keeps track of which synaptic weights have conducted in a given time step.
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004])
Arthur relates to neuromorphic neural networks and is analogous to the claimed invention. Taherkhani teaches a method of performing STDP calculations. The claimed invention improves upon this method by executing it on real hardware with selective loading of synaptic weights based on a bitmask and a time delta. Arthur teaches the use of neuromorphic computer hardware to selectively load and update synaptic weights based on each weight’s conductance time relative to a given timestep (tracked with a bitmask), applicable to Taherkhani’s method. A person of ordinary skill in the art would have recognized that selectively loading weights using bitmasks would lead to the predictable result of fewer load operations, and would improve the known device by saving power consumption and cycles associated with the transfer and loading of data, particularly when the conducting weights are sparse. (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 9, the rejection of claim 1 in view of Taherkhani and Arthur is incorporated. Taherkhani further teaches a method, wherein adjusting a current synaptic weight vector comprises:
adjusting the current synaptic weight vector based on the LTP value to generate a first adjusted synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(LTP value), where A+ is the maximum synaptic change” (Taherkhani, page 255, Left column, paragraph 5).
accumulating synaptic currents based on a membrane potential vector and the first adjusted synaptic weight vector: “The LIF is a one dimensional spiking neural model with low computation cost (Gerstner et al., 2014), that is commonly adopted in the literature. The sub threshold dynamics of the LIF neuron are defined by the following equation:
PNG
media_image7.png
57
369
media_image7.png
Greyscale
where
v
m
(
t
)
is the membrane potential, ... and I(t) is the sum of the current supplied by the input synapses (synaptic currents)” (Taherkhani, page 254, Right column, paragraph 3).
adjusting the first adjusted synaptic weight vector based on the LTD value to generate the updated synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated ... Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
(LTD value), where A− represents the maximum depression, and τ− is a time constant” (Taherkhani, page 255, Left column, paragraph 5).
Regarding claim 10, Taherkhani teaches [a] method comprising:
computing a time delta vector based on a post-synaptic timestamp vector and a pre-synaptic spike timestamp: “If the time interval between the pre- and postsynaptic spike is
t
(time delta)
=
t
p
o
s
t
(post-synaptic timestamp)
-
t
p
r
e
(pre-synaptic spike timestamp) and t > 0 then the synaptic weight will be potentiated” (Taherkhani, page 255, Left column, paragraph 4).
calculating a long-term depression (LTD) value based on the time delta vector: “[I]f a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
(long-term depression value), where A_ represents the maximum depression” (Taherkhani, page 255, Left column, paragraph 5). This value is dependent on t, the time delta.
computing a second time delta vector based on a pre-synaptic timestamp vector and the pre-synaptic spike timestamp: “If the time interval between the pre- and postsynaptic spike is
t
(time delta)
=
t
p
o
s
t
(current timestamp)
-
t
p
r
e
(pre-synaptic timestamp) and t > 0 then the synaptic weight will be potentiated” (Taherkhani, page 255, Left column, paragraph 4).
calculating a long-term potentiation (LTP) value based on the second time delta vector: “The magnitude of the potentiation is a function of t (time delta) which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(long-term potentiation value)” (Taherkhani, page 255, Left column, paragraph 5).
adjusting a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(LTP value), where A+ is the maximum synaptic change. Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
(LTD value), where A− represents the maximum depression, and τ− is a time constant” (Taherkhani, page 255, Left column, paragraph 5).
Taherkhani relates to spiking neural networks and is analogous to the claimed invention.
While Taherkhani fails to disclose the further limitations of the claim, Arthur teaches a method, comprising:
generating a bitmask based on an evaluation of the time delta vector:
“Each synapse 31 has a synaptic weight. The synaptic weights of the synapses 31 of the core circuit 10 may be represented by a weight matrix W (stored bitmask), wherein an element
W
i
j
of the matrix W represents a synaptic weight of a synapse 31 located at a row/axon path i and a column/dendrite path j of the crossbar 12. In one embodiment, the synapses 31 are binary memory devices. Each synapse 31 can have a weight "0" indicating that said synapse 31 is non-conducting, or a weight "1" indicating that said synapse 31 is conducting.” (Arthur, [0032])
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004])
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector; … and writing the updated synaptic weight vector to the memory or another memory or storage device:
“Synaptic weights may be read from, and written to, the memory array 160, in both horizontal and vertical directions for enhanced learning operation. The synaptic weights maintained may be updated based on a learning rule, and/or the firing activity of a corresponding neuron 11.” (Arthur, [0064])
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004]).
Arthur relates to neuromorphic neural networks and is analogous to the claimed invention. Taherkhani teaches a method of performing STDP calculations. The claimed invention improves upon this method by executing it on real hardware with selective loading of synaptic weights based on a bitmask and a time delta. Arthur teaches the use of neuromorphic computer hardware to selectively load and update synaptic weights based on each weight’s conductance time relative to a given timestep (tracked with a bitmask), applicable to Taherkhani’s method. A person of ordinary skill in the art would have recognized that selectively loading weights using bitmasks would lead to the predictable result of fewer load operations, and would improve the known device by saving power consumption and cycles associated with the transfer and loading of data, particularly when the conducting weights are sparse. (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 12, the rejection of claim 10 in view of Taherkhani and Arthur is incorporated. Taherkhani discloses a method, further comprising using the time delta vector as an enabling gate for computing the second time delta vector and the LTP value: “According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t (time delta) = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(LTP value) ... Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
” (Taherkhani, page 255, Left column, paragraph 5). Potentiation occurs only when the time delta is greater than zero. Thus, the time delta is used as an enabling gate for computing the LTP value.
Regarding claim 13, the rejection of claim 10 in view of Taherkhani and Arthur is incorporated. Taherkhani further teaches a method, wherein
calculating the LTD value comprises computing the LTD value according to
PNG
media_image5.png
50
80
media_image5.png
Greyscale
wherein
τ
∆
comprises the time delta vector and A_ and
τ
_ are constant: “[I]f a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
, where A_ represents the maximum depression” (Taherkhani, page 255, Left column, paragraph 5).
calculating the LTP value comprises computing the LTP value according to:
PNG
media_image6.png
60
80
media_image6.png
Greyscale
wherein
τ
∆
comprises the second time delta vector and
A
+
and
τ
+
are constant: “The magnitude of the potentiation is a function of t (time delta) which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
, where A+ is the maximum synaptic change” (Taherkhani, page 255, Left column, paragraph 5).
Regarding claim 16, the rejection of claim 10 in view of Taherkhani and Arthur is incorporated. Arthur further teaches a method, wherein reading a plurality of synaptic weights from memory further comprises selective loading the plurality of synaptic weights using both the time delta vector and a stored bitmask:
“Each synapse 31 has a synaptic weight. The synaptic weights of the synapses 31 of the core circuit 10 may be represented by a weight matrix W (stored bitmask), wherein an element
W
i
j
of the matrix W represents a synaptic weight of a synapse 31 located at a row/axon path i and a column/dendrite path j of the crossbar 12. In one embodiment, the synapses 31 are binary memory devices. Each synapse 31 can have a weight "0" indicating that said synapse 31 is non-conducting, or a weight "1" indicating that said synapse 31 is conducting. A learning rule such as spike-timing dependent plasticity (STDP) may be applied to update the synaptic weights of the synapses 31.” (Arthur, [0032]). The bitmask keeps track of which synaptic weights have conducted in a given time step.
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004])
Arthur relates to neuromorphic neural networks and is analogous to the claimed invention. Taherkhani teaches a method of performing STDP calculations. The claimed invention improves upon this method by executing it on real hardware with selective loading of synaptic weights based on a bitmask and a time delta. Arthur teaches the use of neuromorphic computer hardware to selectively load and update synaptic weights based on each weight’s conductance time relative to a given timestep (tracked with a bitmask), applicable to Taherkhani’s method. A person of ordinary skill in the art would have recognized that selectively loading weights using bitmasks would lead to the predictable result of fewer load operations, and would improve the known device by saving power consumption and cycles associated with the transfer and loading of data, particularly when the conducting weights are sparse. (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 18, the rejection of claim 10 in view of Taherkhani and Arthur is incorporated. Taherkhani further teaches a method, wherein adjusting a current synaptic weight vector comprises:
adjusting the current synaptic weight vector based on the LTP value to generate a first adjusted synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(LTP value), where A+ is the maximum synaptic change” (Taherkhani, page 255, Left column, paragraph 5).
accumulating synaptic currents based on a membrane potential vector and the first adjusted synaptic weight vector: “The LIF is a one dimensional spiking neural model with low computation cost (Gerstner et al., 2014), that is commonly adopted in the literature. The sub threshold dynamics of the LIF neuron are defined by the following equation:
PNG
media_image7.png
57
369
media_image7.png
Greyscale
where
v
m
(
t
)
is the membrane potential, ... and I(t) is the sum of the current supplied by the input synapses (synaptic currents)” (Taherkhani, page 254, Right column, paragraph 3).
adjusting the first adjusted synaptic weight vector based on the LTD value to generate the updated synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated ... Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
(LTD value), where A− represents the maximum depression, and τ− is a time constant” (Taherkhani, page 255, Left column, paragraph 5).
Regarding claim 19, Taherkhani teaches a method, comprising:
computing a time delta vector based on a post-synaptic timestamp vector and a pre-synaptic spike timestamp: “If the time interval between the pre- and postsynaptic spike is
t
(time delta)
=
t
p
o
s
t
(post-synaptic timestamp)
-
t
p
r
e
(pre-synaptic spike timestamp) and t > 0 then the synaptic weight will be potentiated” (Taherkhani, page 255, Left column, paragraph 4).
calculating a long-term depression (LTD) value based on the time delta vector: “[I]f a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
(long-term depression value), where A_ represents the maximum depression” (Taherkhani, page 255, Left column, paragraph 5). This value is dependent on t, the time delta.
computing a second time delta vector based on a pre-synaptic timestamp vector and the pre-synaptic spike timestamp: “If the time interval between the pre- and postsynaptic spike is
t
(time delta)
=
t
p
o
s
t
(current timestamp)
-
t
p
r
e
(pre-synaptic timestamp) and t > 0 then the synaptic weight will be potentiated” (Taherkhani, page 255, Left column, paragraph 4).
calculating a long-term potentiation (LTP) value based on the second time delta vector: “The magnitude of the potentiation is a function of t (time delta) which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(long-term potentiation value)” (Taherkhani, page 255, Left column, paragraph 5).
adjusting a current synaptic weight vector based on the LTD value and LTP value to generate an updated synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(LTP value), where A+ is the maximum synaptic change. Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
(LTD value), where A− represents the maximum depression, and τ− is a time constant” (Taherkhani, page 255, Left column, paragraph 5).
Taherkhani relates to spiking neural networks and is analogous to the claimed invention.
While Taherkhani fails to disclose the further limitations of the claim, Arthur teaches a method, comprising:
generating a bitmask based on an evaluation of the time delta vector:
“Each synapse 31 has a synaptic weight. The synaptic weights of the synapses 31 of the core circuit 10 may be represented by a weight matrix W (stored bitmask), wherein an element
W
i
j
of the matrix W represents a synaptic weight of a synapse 31 located at a row/axon path i and a column/dendrite path j of the crossbar 12. In one embodiment, the synapses 31 are binary memory devices. Each synapse 31 can have a weight "0" indicating that said synapse 31 is non-conducting, or a weight "1" indicating that said synapse 31 is conducting.” (Arthur, [0032])
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004])
selectively loading a plurality of synaptic weights from memory based on at least the time delta vector; … and writing the updated synaptic weight vector to the memory or another memory or storage device:
“Synaptic weights may be read from, and written to, the memory array 160, in both horizontal and vertical directions for enhanced learning operation. The synaptic weights maintained may be updated based on a learning rule, and/or the firing activity of a corresponding neuron 11.” (Arthur, [0064])
“The synaptic conductance changes with time as a function of the relative spike times (time delta[s]) of pre-synaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires, and decreases the conductance of a synapse if the order of the two firings is reversed.” (Arthur, [0004]).
Arthur relates to neuromorphic neural networks and is analogous to the claimed invention. Taherkhani teaches a method of performing STDP calculations. The claimed invention improves upon this method by executing it on real hardware with selective loading of synaptic weights based on a bitmask and a time delta. Arthur teaches the use of neuromorphic computer hardware to selectively load and update synaptic weights based on each weight’s conductance time relative to a given timestep (tracked with a bitmask), applicable to Taherkhani’s method. A person of ordinary skill in the art would have recognized that selectively loading weights using bitmasks would lead to the predictable result of fewer load operations, and would improve the known device by saving power consumption and cycles associated with the transfer and loading of data, particularly when the conducting weights are sparse. (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 20, the rejection of claim 19 in view of Taherkhani and Arthur is incorporated. Taherkhani further teaches a method, wherein adjusting a current synaptic weight vector comprises:
adjusting the current synaptic weight vector based on the LTP value to generate a first adjusted synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated. The magnitude of the potentiation is a function of t which decays exponentially with a time constant τ+ and can be calculated by
PNG
media_image4.png
33
104
media_image4.png
Greyscale
(LTP value), where A+ is the maximum synaptic change” (Taherkhani, page 255, Left column, paragraph 5).
accumulating synaptic currents based on a membrane potential vector and the first adjusted synaptic weight vector: “The LIF is a one dimensional spiking neural model with low computation cost (Gerstner et al., 2014), that is commonly adopted in the literature. The sub threshold dynamics of the LIF neuron are defined by the following equation:
PNG
media_image7.png
57
369
media_image7.png
Greyscale
where
v
m
(
t
)
is the membrane potential, ... and I(t) is the sum of the current supplied by the input synapses (synaptic currents)” (Taherkhani, page 254, Right column, paragraph 3).
adjusting the first adjusted synaptic weight vector based on the LTD value to generate the updated synaptic weight vector: “Spike Timing Dependent Plasticity (STDP) is a variant of the Hebbian unsupervised learning algorithm. This rule is proposed to describe the changes of a synaptic weight according to the relative timing of pre and postsynaptic spikes. According to STDP, a synaptic weight is potentiated if a presynaptic spike comes shortly before a postsynaptic spike. If the time interval between the pre- and postsynaptic spike is t = tpost − tpre and t > 0 then the synaptic weight will be potentiated ... Alternatively, if a pre synaptic spike occurs shortly after the postsynaptic spike, then the synaptic efficacy is decreased. The magnitude of the decrease can be calculated by
PNG
media_image3.png
32
89
media_image3.png
Greyscale
(LTD value), where A− represents the maximum depression, and τ− is a time constant” (Taherkhani, page 255, Left column, paragraph 5).
Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Taherkhani et al. (A review of learning in biologically plausible spiking neural networks, published 2020, Neural Networks 122 (2020) 253–272), hereafter referred to as Taherkhani, in view of Arthur et al. (TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION, published 2014, US 2014/0180984 A1), hereafter referred to as Arthur, and further in view of Trivedi et al. (Trusted Timer Service, published 2018, US 2018/0189464 A1), hereafter referred to as Trivedi.
Regarding claim 2, the rejection of claim 1 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Chen fail to disclose the further limitations of the claim, Trivedi teaches a method, wherein the pre-synaptic spike timestamp is received via one of a response to a dedicated instruction or via a broadcast operation: “In Example 1, a system comprises a processor; a memory coupled to the processor, where the memory is configured to establish ... a real-time clock configured to provide a current timestamp only in response to receiving a microcode instruction to get the current timestamp (pre-synaptic spike timestamp)” (Trivedi, [0114]). As shown in paragraphs [0225-0227] and [0247] of the instant Application, a current timestamp can be synonymous with the pre-synaptic timestamp for LTD.
Trivedi relates to low-level computer software and is analogous to the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Taherkhani and Chen to receive a timestamp via a dedicated instruction, as disclosed by Trivedi. Doing so would enable applications whose functionality depends on real-time, with a dedicated channel that prevents malicious interceptions and attacks. See Trivedi, [0002] and [0013].
Regarding claim 11, the rejection of claim 10 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Arthur fail to disclose the further limitations of the claim, Trivedi teaches a method, wherein the pre-synaptic spike timestamp is received via one of a response to a dedicated instruction or via a broadcast operation: “In Example 1, a system comprises a processor; a memory coupled to the processor, where the memory is configured to establish ... a real-time clock configured to provide a current timestamp only in response to receiving a microcode instruction to get the current timestamp (pre-synaptic spike timestamp)” (Trivedi, [0114]). As shown in paragraphs [0225-0227] and [0247] of the instant Application, a current timestamp can be synonymous with the pre-synaptic timestamp for LTD.
Trivedi relates to low-level computer software and is analogous to the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Taherkhani and Arthur to receive a timestamp via a dedicated instruction, as disclosed by Trivedi. Doing so would enable applications whose functionality depends on real-time, with a dedicated channel that prevents malicious interceptions and attacks. See Trivedi, [0002] and [0013].
Claims 5-6 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Taherkhani et al. (A review of learning in biologically plausible spiking neural networks, published 2020, Neural Networks 122 (2020) 253–272), hereafter referred to as Taherkhani, in view of Arthur et al. (TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION, published 2014, US 2014/0180984 A1), hereafter referred to as Arthur, and further in view of Linares-Barranco et al. (NEURON CIRCUIT, SYSTEM, AND METHOD WITH SYNAPSE WEIGHT LEARNING, published 2019, US 2019/0138900 A1), hereafter referred to as Linares-Barranco.
Regarding claim 5, the rejection of claim 4 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Arthur fail to disclose the further limitations of the claim, Linares-Barranco discloses a method, wherein calculating the LTD value comprises issuing a single single-instruction multiple data (SIMD) instruction:
“the STDP learning block may include a potentiating learning processor (LTP processor) for performing long-term potentiation and a depressing learning processor (LTD processor) for performing depressing learning” (Linares-Barranco, [0252]);
“the depressing learning processor 743 may perform a depressing learning process on all of the synapses in the synaptic weight memory 710. Alternatively, the depressing learning processor 743 may perform a depressing learning process on synapses in the synaptic weight memory 710 on which a potentiating learning process has not been performed.” (Linares-Barranco, [0159])
“The … potentiating learning processor 742, depressing learning processor 743… that perform the operations described in this application are implemented by hardware components configured to perform the operations described in this application that are performed by the hardware components … hardware component may have any one or more of different processing configurations, examples of which include … single-instruction multiple-data (SIMD) multiprocessing” (Linares-Barranco, [0299])
Linares-Barranco relates to neuromorphic neural networks and is analogous to the claimed invention. The combination of Taherkhani and Arthur teaches a method and device for executing STDP on a neuromorphic neural network. The claimed invention improves upon this method by running LTD operations with SIMD instructions. Linares-Barranco teaches a method of running LTD operations with SIMD instructions, applicable to the existing combination. A person of ordinary skill in the art would have recognized that performing LTD operations with SIMD would lead to the predictable result of parallelizing LTD operations over multiple data inputs, and would improve the known device by improving application performance through decreasing total needed calculation time (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 6, the rejection of claim 1 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Arthur fail to disclose the further limitations of the claim, Linares-Barranco teaches a method, wherein calculating the LTD value comprises issuing a plurality of SIMD instructions:
“the STDP learning block may include a potentiating learning processor (LTP processor) for performing long-term potentiation and a depressing learning processor (LTD processor) for performing depressing learning” (Linares-Barranco, [0252]);
“the depressing learning processor 743 may perform a depressing learning process on all of the synapses in the synaptic weight memory 710. Alternatively, the depressing learning processor 743 may perform a depressing learning process on synapses in the synaptic weight memory 710 on which a potentiating learning process has not been performed.” (Linares-Barranco, [0159])
“The … potentiating learning processor 742, depressing learning processor 743… that perform the operations described in this application are implemented by hardware components configured to perform the operations described in this application that are performed by the hardware components … hardware component may have any one or more of different processing configurations, examples of which include … multiple-instruction multiple-data (MIMD) multiprocessing (plurality of SIMD instructions)” (Linares-Barranco, [0299])
Linares-Barranco relates to neuromorphic neural networks and is analogous to the claimed invention. The combination of Taherkhani and Arthur teaches a method and device for executing STDP on a neuromorphic neural network. The claimed invention improves upon this method by running LTD operations with multiple SIMD instructions. Linares-Barranco teaches a method of running LTD operations with MIMD instructions, applicable to the existing combination. A person of ordinary skill in the art would have recognized that performing LTD operations with MIMD would lead to the predictable result of parallelizing LTD operations over multiple data inputs, and would improve the known device by improving application performance through decreasing total needed calculation time (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 14, the rejection of claim 13 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Arthur fail to disclose the further limitations of the claim, Linares-Barranco discloses a method, wherein calculating the LTD value comprises issuing a single single-instruction multiple data (SIMD) instruction:
“the STDP learning block may include a potentiating learning processor (LTP processor) for performing long-term potentiation and a depressing learning processor (LTD processor) for performing depressing learning” (Linares-Barranco, [0252]);
“the depressing learning processor 743 may perform a depressing learning process on all of the synapses in the synaptic weight memory 710. Alternatively, the depressing learning processor 743 may perform a depressing learning process on synapses in the synaptic weight memory 710 on which a potentiating learning process has not been performed.” (Linares-Barranco, [0159])
“The … potentiating learning processor 742, depressing learning processor 743… that perform the operations described in this application are implemented by hardware components configured to perform the operations described in this application that are performed by the hardware components … hardware component may have any one or more of different processing configurations, examples of which include … single-instruction multiple-data (SIMD) multiprocessing” (Linares-Barranco, [0299])
Linares-Barranco relates to neuromorphic neural networks and is analogous to the claimed invention. The combination of Taherkhani and Arthur teaches a method and device for executing STDP on a neuromorphic neural network. The claimed invention improves upon this method by running LTD operations with SIMD instructions. Linares-Barranco teaches a method of running LTD operations with SIMD instructions, applicable to the existing combination. A person of ordinary skill in the art would have recognized that performing LTD operations with SIMD would lead to the predictable result of parallelizing LTD operations over multiple data inputs, and would improve the known device by improving application performance through decreasing total needed calculation time (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Regarding claim 15, the rejection of claim 10 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Arthur fail to disclose the further limitations of the claim, Linares-Barranco teaches a method, wherein calculating the LTD value comprises issuing a plurality of SIMD instructions:
“the STDP learning block may include a potentiating learning processor (LTP processor) for performing long-term potentiation and a depressing learning processor (LTD processor) for performing depressing learning” (Linares-Barranco, [0252]);
“the depressing learning processor 743 may perform a depressing learning process on all of the synapses in the synaptic weight memory 710. Alternatively, the depressing learning processor 743 may perform a depressing learning process on synapses in the synaptic weight memory 710 on which a potentiating learning process has not been performed.” (Linares-Barranco, [0159])
“The … potentiating learning processor 742, depressing learning processor 743… that perform the operations described in this application are implemented by hardware components configured to perform the operations described in this application that are performed by the hardware components … hardware component may have any one or more of different processing configurations, examples of which include … multiple-instruction multiple-data (MIMD) multiprocessing (plurality of SIMD instructions)” (Linares-Barranco, [0299])
Linares-Barranco relates to neuromorphic neural networks and is analogous to the claimed invention. The combination of Taherkhani and Arthur teaches a method and device for executing STDP on a neuromorphic neural network. The claimed invention improves upon this method by running LTD operations with multiple SIMD instructions. Linares-Barranco teaches a method of running LTD operations with MIMD instructions, applicable to the existing combination. A person of ordinary skill in the art would have recognized that performing LTD operations with MIMD would lead to the predictable result of parallelizing LTD operations over multiple data inputs, and would improve the known device by improving application performance through decreasing total needed calculation time (MPEP 2143 I. (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results).
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Taherkhani et al. (A review of learning in biologically plausible spiking neural networks, published 2020, Neural Networks 122 (2020) 253–272), hereafter referred to as Taherkhani, in view of Arthur et al. (TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION, published 2014, US 2014/0180984 A1), hereafter referred to as Arthur, and further in view of Gilson et al. (Stability versus Neuronal Specialization for STDP: Long-Tail Weight Distributions Solve the Dilemma, published 2011, PLoS ONE Volume 6 Issue 10), hereafter referred to as Gilson.
Regarding claim 8, the rejection of claim 1 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Arthur fail to disclose the further limitations of the claim, Gilson teaches a method, wherein LTD and LTP values are calculated based on additional synaptic parameters including a current synaptic weight value:
“[W]e use the Fokker-Planck formalism to study the probability density P(J) of a population of weights J (synaptic weight value) that are modified by many plasticity updates” (Gilson, page 2, Right column, paragraph 3).
“Here we present the mathematical description of ‘log-STDP’. In this phenomenological model, the change in the synaptic weight induced by pre- and postsynaptic spikes at respective times
t
p
r
e
and
t
p
o
s
t
is given by
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... Depending on the relative timing of the spike pair
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the learning window W(J; u) represented in Fig. 1B leads to potentiation (LTP) or depression (LTD), respectively
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419
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” (Gilson, page 3, Right column, paragraph 1). Each function of the piecewise W corresponds to LTP and LTD, respectively. They’re based partly on weight value (J).
Gilson relates to STDP for spiking neural networks and is analogous to the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Taherkhani and Arthur to include a current synaptic weight value in STDP calculations, as disclosed by Gilson. Weight dependence is a crucial feature to obtain realistic and functionally efficient STDP models. See Gilson, page 13, Right column, paragraph 2.
Regarding claim 17, the rejection of claim 10 in view of Taherkhani and Arthur is incorporated. While Taherkhani and Arthur fail to disclose the further limitations of the claim, Gilson teaches a method, wherein LTD and LTP values are calculated based on additional synaptic parameters including a current synaptic weight value:
“[W]e use the Fokker-Planck formalism to study the probability density P(J) of a population of weights J (synaptic weight value) that are modified by many plasticity updates” (Gilson, page 2, Right column, paragraph 3).
“Here we present the mathematical description of ‘log-STDP’. In this phenomenological model, the change in the synaptic weight induced by pre- and postsynaptic spikes at respective times
t
p
r
e
and
t
p
o
s
t
is given by
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26
302
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Greyscale
... Depending on the relative timing of the spike pair
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media_image9.png
21
123
media_image9.png
Greyscale
the learning window W(J; u) represented in Fig. 1B leads to potentiation (LTP) or depression (LTD), respectively
PNG
media_image10.png
117
419
media_image10.png
Greyscale
” (Gilson, page 3, Right column, paragraph 1). Each function of the piecewise W corresponds to LTP and LTD, respectively. They’re based partly on weight value (J).
Gilson relates to STDP for spiking neural networks and is analogous to the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Taherkhani and Arthur to include a current synaptic weight value in STDP calculations, as disclosed by Gilson. Weight dependence is a crucial feature to obtain realistic and functionally efficient STDP models. See Gilson, page 13, Right column, paragraph 2.
Response to Arguments
The following responses address arguments and remarks made in the instant remarks dated 12/02/2025.
Objections
Upon further search and consideration, new objections to the claims have been made.
112 Rejections
Previous rejections under 35 U.S.C. 112(b) have been withdrawn in light of the instant amendments. However, in light of the instant amendments, new rejections have been made.
101 Rejections
On pages 5-10 of the instant remarks, the Applicant argues that the claimed invention improves on existing parallel processing technology:
“
The Office rejects claims 1–20 under 35 U.S.C. § 101 as being directed to an abstract idea. Applicant respectfully disagrees and traverses. When considered as a whole, recite patent-eligible subject matter that integrates any judicial exceptions into a practical application by providing a specific technological improvement to the functioning of parallel processors implementing neuromorphic computing systems.
…
Even assuming arguendo that the claims recite a judicial exception at Prong One, the claims integrate any such exception into a practical application at Prong Two by improving the functioning of parallel processors implementing neuromorphic computing operations. The August 2025 memorandum emphasizes that the Step 2A Prong Two analysis must consider the claim as a whole and evaluate how additional elements use or interact with any exception. The memorandum specifically identifies the “improvements consideration” under MPEP §§ 2106.04(d)(1) and 2106.05(a) as supporting a finding of patent eligibility when claims reflect an improvement to the functioning of a computer or to another technology or technical field.
The recent Appeals Review Panel decision in Ex parte Desjardins (Appeal 2024-000567, decided September 26, 2025) provides directly relevant guidance for evaluating AI-related inventions. That decision recognized that “much of the advancement made in computer technology consists of improvements to software that, by their very nature, may not be defined by particular physical features but rather by logical structures and processes,” citing Enfish, LLC v. Microsoft Corp., 822 F.3d 1327, 1339 (Fed. Cir. 2016). The panel emphasized that the eligibility determination should focus on whether claims are directed to an improvement in computer functionality versus being directed to an abstract idea.
The claims here recite specific architectural features that provide concrete technological improvements to parallel processing systems implementing neuromorphic learning. The sequence of operations—computing time deltas via SIMD subtraction, generating bitmasks based on evaluation of those time deltas, and selectively loading synaptic weights conditioned on the generated bitmasks—represents an integrated architectural approach where computed timing relationships directly control memory access patterns. This selective access pattern provides specific technical benefits described in ¶ 171 of the specification, where “upon generating a bitmask for a delay bucket, the SIMD processor executing the method can start accessing relevant weights corresponding to all set bits in the bitmask.” By accessing only weights requiring modification based on spike timing relationships, the architecture reduces unnecessary memory bandwidth consumption and improves processing efficiency.
The specification describes at ¶ 172 how the synaptic weights are allocated in a specific pattern to make their access suitable for SIMD operations predicated by the bitmasks, and notes that “since the bitmasks are generally sparse (e.g., only 5-10% of set bits in a bitmask), in some embodiments, the method may reduce an area requirement on a SIMD processor by having fewer FMA compute units.” These are concrete improvements to how parallel processing hardware operates when implementing neuromorphic learning algorithms, not merely automating a known process using generic computer components.
The Office Action characterizes the parallel processors as “mere instruction to apply judicial exceptions with a generic computing device” under MPEP § 2106.05(f). However, this analysis oversimplifies the claim limitations and fails to account for their specific technological implementation. The August 2025 memorandum cautions that examiners should not oversimplify claim limitations and should carefully evaluate whether technological limitations are being used as tools to improve a recited judicial exception or whether the claim as a whole provides an improvement to technology or a technical field. The memorandum notes that these considerations often overlap and that claims determined to improve computer capabilities support a finding that the claim integrates a judicial exception into a practical application.
The claims recite more than simply using a computer to perform calculations. They recite a specific coordination of SIMD vector operations, bitmask generation from time delta evaluation, and selective memory access predicated on those bitmasks. As described in ¶ 303 of the specification, “the pipeline uses the bitmask (V1) loaded at time 3 (block 808A) and the post-synaptic timestamp differences computed at time 1 (block 804A) as enabling bitmasks,” demonstrating how multiple computed values are architecturally linked in a pipelined implementation to control subsequent operations. This represents a particular technological solution to the problem of efficiently implementing STDP learning on parallel processing hardware, not merely the idea of implementing STDP.
The Ex parte Desjardins decision is particularly instructive in evaluating whether claims cover a particular solution or merely claim the idea of a solution. That decision identified a specific claim limitation “adjust the first values of the plurality of parameters to optimize performance of the machine learning model on the second machine learning task while protecting performance of the machine learning model on the first machine learning task” as reflecting an improvement to how the machine learning model itself operates. Similarly here, the limitation “selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmask” reflects a specific architectural approach where computed timing relationships control which weights are accessed from memory, improving the efficiency of parallel processing hardware implementing neuromorphic operations.
The August 2025 memorandum emphasizes that examiners should consider the extent to which claims cover a particular solution to a problem or a particular way to achieve a desired outcome, as opposed to merely claiming the idea of a solution or outcome. The claims here recite the former. They specify that computing time delta vectors comprises using SIMD operations, that bitmasks are generated based on evaluation of those vectors, and that memory loading is conditioned on those bitmasks. These limitations describe how the solution is accomplished through specific parallel processing operations, not merely what result is desired.
MPEP § 2106.04(d) explains that an indication that claimed invention provides an improvement can include a discussion in the specification that identifies a technical problem and explains the details of an unconventional technical solution expressed in the claim. The specification identifies the technical problem of efficiently implementing STDP learning on parallel processing hardware and explains how the claimed architecture addresses this problem through coordinated SIMD operations, bitmask-controlled execution, and selective memory access. The claims reflect this technical solution through their recitation of specific processing operations and data structures that control hardware behavior.
The Office Action’s reliance on the “apply it” consideration under MPEP § 2106.05(f) is misplaced because the claims do not merely instruct application of an abstract idea on generic computer equipment. As the August 2025 memorandum explains, the “apply it” consideration often overlaps with the improvements consideration, and examiners should evaluate whether claims invoke computers merely as tools to perform an existing process or whether claims purport to improve computer capabilities. The claims here fall into the latter category by reciting specific parallel processing operations that improve how neuromorphic learning is implemented on hardware.
The combination of SIMD-based time delta computation, bitmask generation from time delta evaluation, and bitmask-conditioned memory access represents an integrated technological approach where each element contributes to the overall improvement in parallel processing efficiency. This is not analogous to cases where generic computer components merely automate abstract ideas, but rather reflects the type of technological advancement in software-defined processing that Enfish recognized as patent-eligible. As that court held, software can make non-abstract improvements to computer technology through logical structures and processes, and the claims here recite such improvements.”
Regarding the Applicant’s argument that the claims of the instant application should be allowed under 35 U.S.C. 101 due to their purported similarity to the claims of US Patent No. 16/319,040 (Desjardins), the Examiner respectfully disagrees, as discussed below.
In response to applicant's argument that the recited judicial exceptions of the claimed invention are integrated into a practical application through improving technology, it is noted that the specific SIMD calculations, bitmask memory retrieval, and weight memory architecture, upon which the Applicant relies (as detailed in paragraphs [0171-0172] and [303]) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As noted in MPEP 2106.05(a), it’s insufficient to merely detail how the material of a specification could be used to improve on technology, the Applicant must ensure the limitations that allow for these improvements are represented in the claims: “After the examiner has consulted the specification and determined that the disclosed invention improves technology, the claim must be evaluated to ensure the claim itself reflects the disclosed improvement in technology. Intellectual Ventures I LLC v. Symantec Corp., 838 F.3d 1307, 1316, 120 USPQ2d 1353, 1359 (Fed. Cir. 2016) (patent owner argued that the claimed email filtering system improved technology by shrinking the protection gap and mooting the volume problem, but the court disagreed because the claims themselves did not have any limitations that addressed these issues). That is, the claim must include the components or steps of the invention that provide the improvement described in the specification.”
As discussed in arguments above and further detailed in the 101 rejections section, the claimed invention recites its limitations at a much higher level of generality than those described by the instant specification. For example, claim 5 discloses “The device of claim 4, wherein calculating the LTD value comprises issuing a single single-instruction multiple data (SIMD) instruction”. This is much more general than computing time deltas via SIMD subtraction, configuring weight memory for SIMD operations, generating bitmasks from SIMD output deltas, or reducing FMA compute units through sparse bitmasks. Similar arguments are applicable to other limitations of the claims regarding their generalization of limitations purported to improve on existing technology detailed in the instant specification.
Thus, the Examiner does not find improvements on existing technology or a technological field to be represented in the claims, and no rejections are withdrawn on this basis.
On pages 5-7 of the instant remarks, the Applicant argues that the claimed invention does not recite judicial exceptions:
“The Office Action identifies several claim limitations as reciting judicial exceptions, specifically mathematical concepts and mental processes. With respect to the mathematical concepts, the Office Action characterizes limitations such as “calculate a long-term depression (LTD) value based on the time delta vector” and “calculate a long-term potentiation (LTP) value based on the second time delta vector” as mathematical calculations that can be performed mentally. However, this characterization overlooks the specific technological context in which these operations are performed and the concrete architectural implementation recited in the claims.
The recent USPTO memorandum dated August 4, 2025, provides important guidance on evaluating claims in software-related arts, including machine learning and artificial intelligence. The memorandum emphasizes that examiners must distinguish between claims that merely involve a judicial exception and claims that recite a judicial exception. As stated in MPEP § 2106.04(II)(A)(1), a claim must “set forth or describe” a judicial exception to fall within Prong One. The memorandum further clarifies that claim limitations encompassing AI in a way that cannot be practically performed in the human mind do not fall within the mental process grouping.
The claims here recite operations performed by parallel processors using SIMD operations on vector data structures. These are not abstract mathematical relationships described using mathematical symbols or formulas, but rather concrete operations tied to specific hardware architectures. The limitation “computing the time delta vector comprises subtracting the pre-synaptic spike timestamp from the post-synaptic timestamp vector using single-instruction multiple data (SIMD) operations” describes a specific parallel processing technique where multiple data elements are processed simultaneously across parallel lanes. As described in ¶¶ 224–227 of the specification, this involves broadcasting a scalar timestamp value across multiple SIMD lanes and performing parallel subtraction operations on a vector of timestamps loaded into vector registers.
The mental process analysis under MPEP § 2106.04(a)(2)(III) requires consideration of whether claim limitations can practically be performed in the human mind. The human mind is not equipped to perform SIMD vector operations where multiple independent calculations occur simultaneously in parallel processing lanes. The specification describes at ¶ 102 how bits are loaded into bit-vector registers associated with each lane, and at ¶¶ 127–129 how SIMD lanes perform operations in parallel. These are hardware-specific operations that cannot be practically performed mentally, even with the aid of pen and paper. The August 2025 memorandum specifically cautions examiners not to expand the mental process grouping to encompass claim limitations that cannot practically be performed in the human mind.
Moreover, the claims do not simply recite mathematical relationships in the abstract. The limitation “generate a bitmask based on an evaluation of the time delta vector” describes creating a concrete data structure that controls subsequent processing operations. As described in ¶¶ 137, 229, and 246 of the specification, these bitmasks are stored in vector registers and serve as enabling gates that determine which SIMD lanes execute subsequent operations. This is fundamentally different from merely evaluating whether a time difference is positive or negative for determining LTP versus LTD, as suggested by the Office Action’s reliance on Taherkhani’s theoretical STDP principles.”
In response to the applicant’s arguments, it is noted that the specific parallelized SIMD scheme (described in paragraphs [102], [127-129], and [224-224] of the instant specification) and SIMD bitmask gating scheme (described in paragraphs [137], [229], [246]) upon which the Applicant relies and the specific SIMD enabling gate are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Mathematical calculations can be performed as mental processes, as noted by MPEP 2106.04(a)(2)(III)(B): “The use of a physical aid (e.g., pencil and paper or a slide rule) to help perform a mental step (e.g., a mathematical calculation) does not negate the mental nature of the limitation, but simply accounts for variations in memory capacity from one person to another”.
Additionally noted by MPEP 2106.04(a)(2)(III), the courts don’t distinguish between mental processes performed entirely in the human mind and mental processes performed on a computer: “The courts do not distinguish between mental processes that are performed entirely in the human mind and mental processes that require a human to use a physical aid (e.g., pen and paper or a slide rule) to perform the claim limitation. See, e.g., Benson, 409 U.S. at 67, 65, 175 USPQ at 674-75, 674 … Nor do the courts distinguish between claims that recite mental processes performed by humans and claims that recite mental processes performed on a computer. As the Federal Circuit has explained, "[c]ourts have examined claims that required the use of a computer and still found that the underlying, patent- ineligible invention could be performed via pen and paper or in a person’s mind." Versata Dev. Group v. SAP Am., Inc., 793 F.3d 1306, 1335, 115 USPQ2d 1681, 1702 (Fed. Cir. 2015)”
The claims recite limitations amounting to mathematical calculations performed on generic computer hardware. For example, claim 1 recites the mathematical concepts “calculate a long-term depression (LTD) value based on the time delta vector” and “calculate a long-term potentiation (LTP) value based on the second time delta vector”, each performed by “parallel processors”. A generic parallelized computer executing these operations doesn’t render them not mentally performable or disqualify them as mathematical concepts. Similarly, a highly generic application of SIMD computation to these operations, as recited in dependent claims 5-6, amounts to mere instruction to apply and is not sufficient to make these claims amount to significantly more than their recited judicial exceptions.
The Examiner asserts that the claims, as amended, recite mathematical concepts, and maintains rejections on this basis. See the 101 rejections section for more detail.
103 Rejections
On page 1 of the instant remarks, the Applicant argues that the relied upon prior art fails to disclose the amended claims, particularly generation of a bitmask:
“Specifically, the combination fails to teach or suggest the specific architectural features now recited in the claims, particularly the generation of a bitmask based on evaluation of the time delta vector and the selective loading of synaptic weights conditioned on that bitmask.”
Following further search and consideration, new combinations of prior art are currently relied upon.
While Taherkhani fails to disclose “generate a bitmask based on an evaluation of the time delta vector; selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap; selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap”, as recited in amended claim 1, this deficiency is remedied by Arthur. Arthur discloses a bitmask where each element denotes whether a synaptic weight is ‘conducting’ or not in a given time step (Arthur, [0032]). This bitmask is used in STDP calculations, where conducting synapses are selectively selected to be depressed or potentiated depending on their relative spike times (Arthur, [0004]).
All claims are fully disclosed in view of Taherkhani, Arthur, Linares-Barranco, Trivedi, and Gilson. See the 103 rejections section for more detail. Thus, no rejections are withdrawn on this basis.
On pages 1-2 of the instant remarks, the Applicant argues that Taherkhani fails to disclose the STDP SIMD operations of the invention:
“The claims recite a device with parallel processors configured to compute a time delta vector by subtracting the pre-synaptic spike timestamp from the post-synaptic timestamp vector using SIMD operations, generate a bitmask based on an evaluation of the time delta vector, and selectively load a plurality of synaptic weights from memory based on the bitmask. This specific sequence of operations—computing time deltas via SIMD subtraction, evaluating those deltas to generate a bitmask, and using that bitmask to conditionally control memory access—represents a concrete architectural solution that is absent from both Taherkhani and Chen, individually or in combination.
Taherkhani describes STDP learning at a theoretical and algorithmic level. The reference discusses how synaptic weights change based on spike timing relationships, stating that “If the time interval between the pre- and postsynaptic spike is t = t_post − t_pre and t > 0 then the synaptic weight will be potentiated” and describing exponential decay functions for weight modifications (Taherkhani, page 255, left column, paragraph 5). However, Taherkhani’s discussion remains focused on the mathematical principles of STDP rather than implementation architectures. The reference does not describe SIMD operations, vector subtraction across parallel processing lanes, bitmask generation from time delta evaluation, or conditional memory access patterns based on computed bitmasks.
The Office Action contends that Taherkhani’s scalar operations are equivalent to vector operations because “a scalar-valued variable can equivalently be considered a vector-valued variable of size one.” This interpretation conflates the mathematical concept that scalars are one-element vectors with the architectural distinction between scalar processing and SIMD vector processing. The claims specifically recite subtracting the pre-synaptic spike timestamp from the post-synaptic timestamp vector using SIMD operations. SIMD architecture processes multiple data elements simultaneously across parallel lanes, which fundamentally differs from sequential scalar operations. Taherkhani’s description of computing t = t_post − t_pre for individual synapse pairs does not teach or suggest broadcasting a scalar timestamp value across multiple SIMD lanes and performing parallel subtraction operations on a vector of post-synaptic timestamps, as specified in the specification at ¶¶ 224–227.
Furthermore, Taherkhani does not describe generating a bitmask based on evaluation of computed time deltas. The reference discusses when potentiation or depression occurs based on the sign of the time difference (positive or negative), but this conceptual determination differs substantially from the claimed bitmask generation. The specification describes at ¶¶ 137, 229, and 246 how time delta vectors are evaluated to produce bitmasks that serve as enabling gates for subsequent operations. These bitmasks are concrete data structures stored in vector registers that control which SIMD lanes execute subsequent operations. Taherkhani’s theoretical discussion of STDP conditions (t > 0 for LTP, t < 0 for LTD) does not teach constructing such architectural control structures.”
In response to applicant's arguments above, it is noted that the specific SIMD calculations, parallelization scheme, and bitmask generation algorithm upon which the Applicant relies (as described in paragraphs [137], [224-229] of the instant specification) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As discussed in the above responses to 101 rejection arguments, the claimed invention recites its limitations at a much higher level of generality than those described by the instant specification. For example, claim 5 discloses “The device of claim 4, wherein calculating the LTD value comprises issuing a single single-instruction multiple data (SIMD) instruction”. This is much more general than computing time deltas via SIMD subtraction across parallel processing lanes or generating bitmasks from SIMD output deltas. Similar arguments are applicable to other limitations of the claims regarding their generalization of limitations argued at a finer level of detail based on the instant specification.
The only limitations that recite SIMD usage are “wherein calculating the LTD value comprises issuing a single single-instruction multiple data (SIMD) instruction“ and “wherein calculating the LTD value comprises issuing a plurality of SIMD instructions”. While Taherkhani fails to disclose these limitations, this deficiency is remedied by Linares-Barranco. Linares-Barranco discloses using SIMD or MIMD multiprocessing to perform LTD calculations, at a scope commensurate with the claim language (Linares-Barranco, [0299]).
As discussed in previous arguments, while Taherkhani fails to disclose generating a bitmask, this deficiency is remedied by Arthur.
Thus, no rejections are withdrawn on these grounds.
On page 3 of the instant remarks, the Applicant argues that Chen fails to remedy the deficiencies of Taherkhani:
“The Office Action relies on Chen to remedy Taherkhani’s deficiencies regarding parallel processing and memory operations. Chen describes a neuromorphic computing system and mentions that “portions of operational diagram may be executed in parallel” (Chen, ¶ 98). However, Chen’s generic reference to parallel execution does not bridge the gap to the specific claimed architecture. Chen does not describe computing time delta vectors through SIMD subtraction operations, generating bitmasks from time delta evaluation, or using those bitmasks to selectively control memory access.
The selective loading limitation is particularly significant. The claims require selectively loading a plurality of synaptic weights from memory based on the bitmask generated from time delta evaluation. The specification describes at ¶¶ 171, 248, and 285 that weights are loaded only when corresponding bitmask bits are set, implementing conditional memory access: “if V1[k]==1, which can indicate that there is a pre-synaptic spike for kth synapse (for LTD computation and synaptic integration) or V3[k]==1 which can indicate that there was a post-synaptic spike in the previous time step (for LTP computation), then the method can load the conductance values or weights.” This selective access pattern, driven by bitmasks derived from time delta evaluation, provides architectural benefits by reducing unnecessary memory bandwidth consumption and accessing only weights requiring modification based on spike timing.
Chen describes that “Synapse memory may store synapse weight and synapse destination” (Chen, ¶ 93) and that “During operation, synapse weights of synapses may be selected, modified, or adjusted” (Chen, ¶ 94). However, Chen does not describe the specific mechanism claimed here: generating a bitmask through evaluation of SIMD-computed time delta vectors and using that bitmask to predicate which weights are loaded from memory. Chen’s general statements about weight storage and modification do not teach conditional loading based on bitmask evaluation derived from time delta computations.”
In response to applicant's arguments above, it is noted that the specific method of storing bitmasks with each element corresponding to conductance of a pre-synaptic or post-synaptic spike in some time step upon which the Applicant relies (as described in paragraphs [171], [248], and [285]) of the instant specification) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As discussed in previous arguments, Arthur discloses “generate a bitmask based on an evaluation of the time delta vector; selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap; selectively loading a plurality of synaptic weights from memory based on at least the time delta vector based on the bitmap”. Thus, no rejections are withdrawn on these grounds.
On pages 4 of the instant remarks, the Applicant argues that Xu and Mital fail to disclose the bitmask generation of the claimed invention:
“The Office Action references additional prior art including Xu and Mital in the rejection of dependent claim 7. However, these references address different implementations. The Office Action maps Xu’s ideal binary masking for speech separation to the claimed selective loading, but Xu describes masking in the context of time-frequency analysis for audio processing. Xu states: “In the embodiment of the present disclosure, the ideal binary masking (IBM) is used, when a pulse is released within a certain time span of a neuron, the corresponding information masking unit is set as 1, otherwise the information masking unit is set as 0” (Xu, ¶ 113). This describes determining which time-frequency units contain target speech, which differs from generating bitmasks through evaluation of SIMD-computed time delta vectors for controlling synaptic weight memory access in STDP processing.
The combination would require modifying Taherkhani’s theoretical STDP framework to implement SIMD vector operations with time delta computation, adding bitmask generation based on time delta evaluation, and implementing conditional memory access patterns controlled by those bitmasks. Neither Taherkhani nor Chen describes this integrated architectural approach where the computed time delta vectors directly control memory access through generated bitmasks. The specification describes at ¶ 303 that “the pipeline uses the bitmask (V1) loaded at time 3 (block 808A) and the post-synaptic timestamp differences computed at time 1 (block 804A) as enabling bitmasks,” demonstrating how time delta computations and bitmask-controlled operations are architecturally linked in a pipelined implementation.
The claimed architecture provides specific technical advantages not recognized in the cited references. By generating bitmasks from time delta evaluation and using those bitmasks to selectively load weights, the architecture accesses only synaptic weights requiring modification based on spike timing relationships. As described at ¶ 171, “upon generating a bitmask for a delay bucket, the SIMD processor executing the method can start accessing relevant weights corresponding to all set bits in the bitmask.” This selective access reduces memory bandwidth requirements compared to loading all weights indiscriminately. Additionally, the SIMD implementation with bitmask-controlled operations enables efficient parallel processing where multiple synaptic connections are evaluated and updated simultaneously, with memory operations predicated on computed timing relationships.”
In response to applicant's arguments above, it is noted that the generation algorithm of bitmasks and the combination of bitmasks and SIMD upon which the Applicant relies (as described in paragraphs [171] and [303] of the instant specification) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding “selectively loading reading a plurality of synaptic weights from memory further comprises selective loading the plurality of synaptic weights using both the time delta vector and a stored bitmask”, as recited in claim 7, Arthur discloses a bitmask where each element denotes whether a synaptic weight is ‘conducting’ or not in a given time step (Arthur, [0032]). This bitmask is used in STDP calculations, where conducting synapses are selectively selected to be depressed or potentiated depending on their relative spike times (Arthur, [0004]).
Thus, no rejections are withdrawn on these grounds.
On page 5 of the instant remarks, the Applicant argues that the relied upon prior art doesn’t disclose the claimed invention:
“The combination of Taherkhani and Chen, even with the additional references cited for dependent claims, does not render obvious the specific architectural integration claimed: computing time deltas via SIMD operations on timestamp vectors, generating bitmasks based on evaluation of those time deltas, and selectively loading synaptic weights conditioned on the generated bitmasks. This integrated approach, where time delta computation directly drives selective memory access through bitmask-based conditional loading, represents a specific architectural solution not taught or suggested by the cited references.
For these reasons, Applicant asserts that the cited art fails to teach or suggest each and every element of claim 1. Further, the remaining independent recite similar elements and are thus allowable over the cited art for at least the same reasons. Finally, the dependent claims are allowable over the cited art for at least the reasons set forth with respect to the independent claims.
As a result, the cited prior art, alone or in combination, fails to disclose, teach, or suggest all elements of the claims, and thus Applicant respectfully requests the withdrawal of the rejection.”
In response to applicant's arguments above, it is noted that computing time deltas with SIMD on timestamp vectors and generating bitmasks based on evaluation of time delts upon which the Applicant relies are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As argued previously and discussed at length in the 103 rejections section, all limitations of the claimed invention are disclosed between Taherkhani, Arthur, Linares-Barranco, Trivedi, and Gilson. Thus, no rejections are withdrawn on these grounds.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chinya et al. (ACCELERATED LOADING OF UNSTRUCTURED SPARSE DATA IN MACHINE LEARNING ARCHITECTURES, published 2/11/2021, US 20210042617 A1) discloses a method of representing sparse weights in a neural network with bitmaps.
Hunzinger et al. (US 2013/0226851A1) teaches a method of performing STDP with leaky membranes on computer hardware.
Bichler et al. (Extraction of temporally correlated features from dynamic vision sensors with spike-timing-dependent plasticity, 2012, Neural Networks Volume 32, August 2012, Pages 339-348) teaches a method of gating LTP calculation with the delta used for LTD calculation.
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/AG/Examiner, Art Unit 2148
/MICHELLE T BECHTOLD/Supervisory Patent Examiner, Art Unit 2148