DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is final and is in response to the claims filed 01/21/2026. Claims 1, 3-6, 8, 10-13 and 15-24 are currently pending, of which claims 1, 3-6, 8, 10-13 and 15-24 are currently rejected.
Response to Arguments
Applicant’s arguments filed on 06/18/2026 have been fully considered but they are not persuasive.
Drawing Objection: Drawing objection has been withdrawn necessitated by amendments.
35 U.S.C. 103: Applicant’s arguments regarding the 35 U.S.C. 103 have been fully considered.
Applicant argues in pages 10-11 that Vantrease in view of Ullah in view of Zhang do not teach amended claim 1. Applicant specifically argues each of the cited references individually not teaching the limitations of amended claim 1.
Examiner respectfully disagrees. Applicant argues each reference individually. However, Applicant does not address the combination of Vantrease in view of Ullah in view of Zhang not disclosing the limitations of claim 1. Still, see new grounds of rejection under 35 U.S.C. 103 necessitated by amendments below.
Applicant further argues in page 11 how Ullah does not teach the limitation of amended claim 1. Applicant specifically argues “Ullah contains no programmable component that "is configured to selectively perform one of the multiple different post- processing operations based on a control signal," in accordance with amended claim 1.”
Examiner respectfully disagrees. Examiner does not rely on Ullah to teach this limitation. Examiner explains how Zhang in combination with Vantrease and Ullah teach the limitation “is configured to selectively perform one of the multiple different post- processing operations based on a control signal,” See Non-final rejection mailed on 02/12/2026.
Applicant further argues the combination proposed by Examiner created an explicit engineering contradiction that changes the principle of operation of the cited references. Applicant specifically argues:
Ullah's core architectural contribution relies on extracting complex logic out of
individual array cells to minimize the physical area, routing footprint, and critical delay paths of the internal processing elements. Ullah specifically notes that its optimization succeeds by "factoring out this repeated dedicated pre-pressing logic from the PEs and place there at the inputs." Zhang's flexible multi-precision data layout, on the other hand, demands heavily intensive, complex hardware infrastructures, including multiple dynamic masks, dynamic alignment shifters, and leading-zero anticipator trees. Forcing Zhang's complex, variable multi- precision hardware switchboards into every individual repeatable cell of Ullah's layout would run completely counter to Ullah's structural design goals. Rather than achieving cell simplification, such a combination overloads the local internal cells with extensive logic and routing lines, creating area overheads and clock-skew boundaries that undermine the scalability of a distributed systolic array grid.
Examiner respectfully disagrees. Ullah does not explicitly teach each post-processing operation in the post dedicated logic. However, Zhang teaches a Flexible Multiple Precision Multiply Accumulate Unit that performs floating-point and fixed point post processing operations (i.e., rounding, normailizing, truncating) after performing multiplication and accumulation in each PE. Zhang further enhances the model of Vantrease in view of Ullah because "further energy reduction can be achieved when each operation step can use its minimum required precision instead of being forced to use a uniform precision for all steps." (Zhang: Section 1 Introduction, third paragraph). See 35 U.S.C. 103 rejection below for motivation to perform the combination of Vantrease in view of Ullah in view of Zhang.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “each cell further comprises a local control register linked to a control wire that propagates the control signal sequentially between adjacent cells in the systolic array grid” feature disclosed in claim 24 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3-6, 8, 10-13 and 15-24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation “wherein the post-processing component is configured to dynamically execute a conditional selection to adjust the accumulated value inside the cell, such that the post- processing component selects and performs the rounding of the accumulated value in response to receiving a first control signal, and selects and performs the activation function using the accumulated value in response to receiving a second control signal, prior to routing the post- processed value to the output register.” There is no description in the original disclosure supporting this limitation. Closest description is found in paragraph 0053 of the specification, which discloses:
“In this example, the post-processing component 312 can be controlled to either round accumulated values, e.g., to one of multiple possible lower precision forms, or to pass the higher precision accumulated values directly. Control signals can be used to change the post-processing operation performed by a programmable post-processing component 312. Continuing the previous example, the post-processing component 312 can round accumulated values to a first lower precision format in response to receiving a first control signal, can round accumulated values to a second lower precision format in response to receiving a second control signal, or to not round at all in response to receiving a third control signal. In another example, the post-processing component 312 can perform a given activation function of a set of possible activation functions of the post-processing component 312 based on the control signal.”
This description does not support the dynamically executing a conditional selection involving selecting and performing rounding the accumulated value in response to a first control signal and selecting and performing an activation function in the accumulated value in response to a second control signal prior to routing the post-processed value to the output register. Instead, paragraph 0053 discloses performing rounding and activation operation in response to control signal, but does not disclose how the post-processing component is configured to dynamically execute a conditional selection.
Independent Claims 8 and 15 recite the same limitation, and are rejected for the same reasons therein.
Claims 3-6 and 21-24 inherit the same deficiency as claim 1 by reason of dependence. They are rejected for the same reasons therein.
Claims 10-13 inherit the same deficiency as claim 8 by reason of dependence. They are rejected for the same reasons therein.
Claims 16-20 inherit the same deficiency as claim 15 by reason of dependence. They are rejected for the same reasons therein.
Claim 23 recites the limitations “the post-processing component comprises a fused activation and quantization circuit layout”. There is no description in the original disclosure supporting this limitation describing any fused activation and quantization circuit layout.
Claim 23 further recites “when selectively executing the activation function, the rectified linear unit circuitry evaluates the accumulated value and outputs an integer value of zero if the accumulated value is negative or zero, and routes a positive accumulated value directly to the rounding circuitry”. There is no description in the original disclosure supporting this limitation. Closest description is found in paragraph 0051 of the specification, which discloses:
The post-processing component 312 can include a ReLU in combination with rounding or truncating circuitry.
This description does not support routing the activation function positive output directly to the rounding circuitry. Instead, paragraph 0051 describes how the post processing component can include a ReLU function in combination with the rounding circuitry, but does no disclose how the activation function positive output is directly routed to the rounding circuitry.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 15-22 are rejected under 35 U.S.C. 103 as being unpatentable over Vantrease et al. (U.S. Patent Application Publication No: US 20190294413 A1) cited in IDS on 7/22/2022, hereinafter “Vantrease”, in view of Inayat Ullah in NPL: “Factored Radix-8 Systolic Array for Tensor Processing” cited in IDS on 7/22/2022, hereinafter “Ullah”, in view of Hao Zhang in NPL: “New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference” (https://ieeexplore.ieee.org/abstract/document/8825551), hereinafter “Zhang”, further in view of Huynh et al. (U.S. Patent Application Publication No.: US 20210097375 A1), hereinafter “Huynh”.
With regards to Claim 1, Vantrease teaches a system comprising:
a plurality of cells arranged in a systolic array (Fig. 6, e.g., Plurality of PEs (Cells) arranged in a systolic array; ¶0074-0075), wherein each cell comprises:
multiplication circuitry configured to determine a product of elements of input matrices (¶0077, e.g., Each PE contains multiplier 623; Fig. 6);
an accumulator configured to determine an accumulated value by accumulating a sum of the products output by the multiplication circuitry (¶0077, e.g., Each PE contains adder 625 which accumulates values from other PEs and the product from the multiplier 623);
… ; and
a post-processing component [outside the systolic array] configured to determine a post-processed value by performing one or more post-processing operations on the accumulated value (Fig. 5, e.g., Post-processor 528; ¶0080, e.g., post-processor 528 may include activation engine 528a to perform one or more activation functions (post-processing operations) to generate output data (post-processed value)), wherein the post- processing component is programmable (¶0127, e.g., processing logic 1102 (which may include neural network processor) may process instructions stored in the form of a computer program (programmable). Fig. 5, e.g., Neural network processor 502 includes Post-processor 528, hence Post processor 528 is considered programable) … and performing an activation function using the accumulated value (¶0080, e.g., Post-processor 528 includes activation engine 528a, which performs activation (non-linear) functions such as ReLu) …
…
Vantrease does not teach:
wherein each cell comprises: …
an output register configured to receive the post-processed value and shift the post-processed value out of the cell; and
a post-processing component configured to determine a post-processed value by performing one or more post-processing operations on the accumulated value, … and is configured to perform multiple different post-processing operations comprising rounding the accumulated value … , and wherein the post-processing component is configured to selectively perform one of the multiple different post-processing operations based on a control signal,
wherein the post-processing component is configured to dynamically execute a conditional selection to adjust the accumulated value inside the cell, such that the post- processing component selects and performs the rounding of the accumulated value in response to receiving a first control signal, and selects and performs the activation function using the accumulated value in response to receiving a second control signal, prior to routing the post- processed value to the output register.
However, in the same field of endeavor, Ullah teaches a systolic array where each PE, or cell, contains a post processing block in each cell to produce output Q. Ullah explains “The P -dedicated postprocessing takes the MAC output and produces Q” (See Section 3. Proposed design, subsection 3.1 A General Idea for Systolic Arrays; Fig. 2 (a)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the teaching of implementing Post-processing logic in each PE as taught by Ullah with the Post-processor and the PEs in the systolic array as taught by Vantrease. One would have been motivated to combine these references because both references disclose systolic arrays to be implemented in convolutional neural networks, and Ullah enhances the model of Vantrease by allowing for low latency in each post processing operation.
Vantrease in view of Ullah do not teach:
wherein each cell comprises: …
an output register configured to receive the post-processed value and shift the post-processed value out of the cell; and
… and is configured to perform multiple different post-processing operations comprising rounding the accumulated value … , and wherein the post-processing component is configured to selectively perform one of the multiple different post-processing operations based on a control signal,
wherein the post-processing component is configured to dynamically execute a conditional selection to adjust the accumulated value inside the cell, such that the post- processing component selects and performs the rounding of the accumulated value in response to receiving a first control signal, and selects and performs the activation function using the accumulated value in response to receiving a second control signal, prior to routing the post- processed value to the output register.
However, Zhang teaches:
wherein each cell comprises: …
… and is configured to perform multiple different post-processing operations comprising rounding the accumulated value (Fig. 2, e.g., shows normalization shifter, floating-point rounding, fixed-point rounding, and output processing blocks (multiple different post-processing operations), each block performs floating-point rounding), and wherein the post-processing component is configured to selectively perform one of the multiple post-processing operations based on a control signal (Section 3 The Proposed Flexible Multiple Precision Multiply Accumulate Unit, Paragraph under Table 2, e.g., 2-bit MODE signal (control signal) controls the precision mode and the operation to be performed (one of the multiple post-processing operations))
wherein the post-processing component is configured to dynamically execute a conditional selection to adjust the accumulated value inside the cell, such that the post- processing component selects and performs the rounding of the accumulated value in response to receiving a first control signal (Section 3.7 Rounding, e.g., rounding can be selected from floating-point mode, or fixed-point mode; Section 3 The Proposed Flexible Multiple Precision Multiply Accumulate Unit, Paragraph under Table 2, e.g., FPL signal selects floating-point mode, or fixed-point mode (first control signal)), …
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify post processing component as taught by Vantrease in view of Ullah to include the normalization shifter, floating-point rounding, fixed-point rounding, and output processing blocks as taught by Zhang. One would have been motivated to combine these references because both references disclose solving convolutional neural networks using Processing Elements, and Zhang enhances the model of Vantrease in view of Ullah because "further energy reduction can be achieved when each operation step can use its minimum required precision instead of being forced to use a uniform precision for all steps." (Zhang: Section 1 Introduction, third paragraph).
Zhang also teaches:
wherein each cell comprises: …
an output register configured to receive the post-processed value and shift the post-processed value out of the cell (Fig. 2, e.g., shows output registers at the end of each PE);
… prior to routing the post- processed value to the output register (Fig. 2, e.g., shows rounding outputting rounded results to output registers).
It would have also been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the post processing component as taught by Vantrease in view of Ullah to include the output registers as taught by Zhan. One would have been motivated to combine these references because both references disclose solving convolutional neural networks using Processing Elements, and Zhang enhances the model of Vantrease in view of Ullah by allowing for a fully-connected layer computation within the PE. See Fig. 2 and paragraph below Fig. 2.
Vantrease in view of Ullah in view of Zhang do not teach:
wherein the post-processing component is configured to dynamically execute a conditional selection to adjust the accumulated value inside the cell … and selects and performs the activation function using the accumulated value in response to receiving a second control signal, …
However, in the same field of endeavor, Huynh teaches using a controller to control the operations of an activation engine. Huynh explains “Accelerator 402 may include a controller 422 to control the operations of processing engine array 410, activation engine 416, and/or pooling engine 418” (Huynh: ¶0053). Additionally, Vantrease teaches the activation engine 528a may be skipped by the controller for certain convolution layers. Hence the activation engine 528a taught by Vantrease is already configured to receive signals from the controller.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the controlling of operations of the activation engine as taught by Huynh with the activation engine as taught by Vantrease. One would have been motivated to combine these references because both references disclose using activation engines for systolic arrays, and Huynh enhances the model of Vantrease in view of Ullah in view of Zhang by allowing for the controlling of operations by activation engine. See Huynh: ¶0053 and Fig. 4A. Hence, Vantrease in view of Ullah in view of Zhang in view of Huynh teach the rounding and activation engines to receive control signals to select operations.
With regards to Claim 3, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1, wherein at least one of the multiple different post-processing operations of the post-processing component comprises rounding the accumulated value from a higher precision number format to a lower precision number format (Zhang: Fig. 2, e.g., floating-point rounding block is included between the pipeline registers 2 and output registers (post-processing component) and receives sum output (accumulated value); Fig. 11, e.g., rounds from 48 bits to 16 bits).
The motivation to combine provided with respect to claim 1 applies equally to claim 3.
With regards to Claim 4, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1 wherein:
the post-processing component comprises rounding circuitry configured to round the accumulated value from a higher precision number format to a lower precision number format (Zhang: Fig. 2, e.g., floating-point rounding block is included between the pipeline registers 2 and output registers (post-processing component) and receives sum output (accumulated value); Fig. 11, e.g., rounds from 48 bits to 16 bits);
Zhang further teaches:
and each cell contains a number of output wires equal to a number of bits of the lower precision number format (Fig. 2, e.g., bit-width of the output register is 16 (lower precision number format)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the bit-width (output wires) to be the amount of the lower precision format as taught by Zhang with the PEs in the systolic array as taught by Vantrease in view of Ullah. One would have been motivated to combine these references because both references disclose solving convolutional neural networks, Zhang enhances the model of Vantrease in view of Ullah because it can "provide almost the same accuracy with much lower hardware cost." (Zhang: Section 4 Results and Analysis, Tenth paragraph).
With regards to Claim 5, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1, wherein at least one of the multiple different post-processing operations of the post-processing component comprises truncating the accumulated value from a higher precision number format to a lower precision number format (Zhang: Section 3 New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference, Subsection 3.8 Output Processing, First Paragraph, e.g., Truncates from a higher precision to a 16-bit result (lower precision number format)).
The motivation to combine provided with respect to claim 1 applies equally to claim 5.
With regards to Claim 6, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1, wherein the post-processing component comprises rectified linear unit (ReLU) circuitry (Vantrease: ¶0023, e.g., Each neuron applies a nonlinear function to the weighted sum; ¶0080, e.g., Post-processor 528 includes activation engine 528a, which performs activation (non-linear) functions such as ReLu) configured to:
output the accumulated value when the accumulated value is positive (Vantrease: ¶0032, e.g., Real-valued input (accumulated value) is threshold to zero, hence it is outputted if positive.); and
output a value of zero when the accumulated value is negative or zero (Vantrease: ¶0032, e.g., ReLu replaces negative values with zeros).
The motivation to combine provided with respect to claim 1 applies equally to claim 6.
With regards to Claims 8 and 10-13, they are similar to the claimed matrix multiplication unit above (claims 1 and 3-6 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, these claims are rejected for at least the same reasons therein.
Regarding claims 15-20, they are method claims practiced by the apparatus of claims 1-6. It is rejected for the same reasons as claims 1-6.
With regards to Claim 21, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1, wherein the multiple different post-processing operations comprise truncating the accumulated value (Zhang: Section 3 New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference, Subsection 3.8 Output Processing, First Paragraph, e.g., Truncates from a higher precision to a 16-bit result (lower precision number format)).
The motivation to combine provided with respect to claim 1 applies equally to claim 21.
With regards to Claim 22, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1, wherein the multiple different post-processing operations comprise multiple activation functions (Vantrease: Fig. 5, e.g., Post-processor 528 includes Activation engine 528a; ¶0032, e.g., several activation functions may be used)
With regards to Claim 23, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1, wherein:
the post-processing component comprises a fused activation and quantization circuit layout (Vantrease: Fig. 5, e.g., Post-processor 528 includes Activation engine 528a; ¶0085 floating-point values are quantized); and
when selectively executing the activation function, the rectified linear unit circuitry evaluates the accumulated value and outputs an integer value of zero if the accumulated value is negative or zero (Vantrease: ¶0032, e.g., ReLU function outputs a zero if values are zero or negative), and routes a positive accumulated value directly to the rounding circuitry to convert the positive accumulated value from a 32-bit high-precision format to a 16-bit lower- precision format prior to moving the post-processed value to the output register (Vantrease: ¶0032, e.g., ReLU function thresholds values above zero, hence positive values are not replaced with zero; Ullah: Round logic may naturally be placed at the outputs; Zhang: Fig. 2, e.g., shows floating-point rounding in the output of the PE, and further shows floating-point rounding block receiving 32-bit values (16 bit normalized value and 16 bit exponent), and output processing block outputs 16 bit value; Section 3.7 Rounding, first paragraph, e.g., rounding is fixed to the LSB position of the C operand)
The motivation to combine provided with respect to claim 1 applies equally to claim 23.
With regards to Claim 24, Vantrease in view of Ullah in view of Zhang in view of Huynh teach:
The matrix multiplication unit of claim 1, wherein:
each cell comprises a localized inter-cell output bus directly connecting the cell to an adjacent downstream cell in the systolic array grid (Vantrease: Fig. 6, e.g., shows PEs connected to downstream PEs), the localized inter-cell output bus containing a physical number of output wires restricted to match a bit-width of a lower precision number format (Zhang: Fig. 2, e.g., bit-width of the output register is 16 (lower precision number format));
wherein the post-processing component is structurally positioned at an output boundary of the cell immediately preceding the localized inter-cell output bus to perform the post- processing operations prior to shifting data out of the cell (Ullah: Section 3. Proposed design, subsection 3.1 A General Idea for Systolic Arrays and Fig. 2 (a), e.g., P -dedicated postprocessing takes the MAC output and produces Q); and
wherein each cell further comprises a local control register linked to a control wire that propagates the control signal sequentially between adjacent cells in the systolic array grid (Vantrease: ¶0078, e.g., each PE includes registers (local control register), and each PE comprises sequential logic circuitry that can be clocked by a clock signal (control signal)).
The motivation to combine provided with respect to claim 1 applies equally to claim 24.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
