DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed 01/21/2026. Claims 1-6, 8-13, and 15-22 are currently pending, of which claims 1-6, 8-13, and 15-22 are currently rejected.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/21/2026 has been entered.
Response to Arguments
Applicant’s arguments filed on 01/21/2026 have been fully considered but they are not persuasive.
Drawing Objection: Applicant’s arguments regarding the drawing objection have been fully considered, but they are not persuasive.
Applicant argues in page 7 of 9 that the drawing objection should be withdrawn because the post-processing component 312 allegedly includes a programable component. Applicant specifically argues:
Applicant respectfully disagrees because the "programmable component" is disclosed throughout the specification. For example, paragraph [0053] of Applicant's original specification recites "In some implementations, the post-processing component 312 is a programmable component that can perform multiple post-processing operations." Accordingly, Applicant respectfully requests reconsideration and withdrawal of this objection to the drawings.
Examiner respectfully disagrees. New figures 3 and 4 show a programmable component that was not disclosed in the original specification. Applicant points to paragraph 0053 disclosing a programmable component. While paragraph 0053 does say the post-processing component 312 is a programmable component, it does not disclose the post-processing component 312 including a programable component inside along with rounding circuitry, truncation circuitry, and rectified linear unit circuitry as shown in new figures 3 and 4. See Drawing objection below.
35 U.S.C. 112(b): Rejection under 35 U.S.C. 112(b) has been withdrawn necessitated by amendments.
35 U.S.C. 103: Applicant’s arguments regarding the 35 U.S.C. 103 have been fully considered, but they are not persuasive.
Applicant argues in pages 7-8 of 9 that neither cited reference teaches a single programmable post-processing component performs rounding and activation function of an accumulated value. Further, Applicant argues how Vantrease teaches a post-processing component outside the systolic array and not as being part of a cell of a systolic array. Applicant specifically argues:
However, neither reference teaches of suggests a single programmable post-processing component that is in each cell of a systolic array and that is configured to selectively perform one of "multiple different post-processing operations comprising rounding the accumulated value and performing an activation function using the accumulated value" based on a control signal. In addition, the post-processor of Vantrease which the Examiner relied on in the rejection of previous claim 21 is not disclosed as being part of a cell of a systolic array. Instead, FIG. 5 of Vantrease shows the post-processor as being connected to the output buffer that receives the output of systolic array of the computing engine 524.
Examiner respectfully disagrees. Vantrease alone teaches a post processor outside the systolic array that performs the activation function. However, as explained in the 35 U.S.C. 103 rejection, Vantrease in view of Ullah together teach the post-processor being included in each PE (cell) of a systolic array. Vantrease in view of Ullah in view of Zhang further teaches the post-processor performing rounding operations on floating-point numbers. See 35 U.S.C. 103 rejection below for motivation to perform the combination of Vantrease in view of Ullah in view of Zhang.
Drawings
The drawings were received on 09/18/2025. These drawings are not acceptable because both sheets (Figs. 3 and 4) include new subject matter not disclosed in the original disclosure. Both Figures 3 and 4 show the post-processing component 312 including a programmable component. This programmable component is not disclosed anywhere in the original disclosure, therefore these replacement sheets are not accepted and previous objection to the drawings is not withdrawn. See MPEP 608.02.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the rounding circuitry, truncation circuitry, and rectified linear unit circuitry must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-13, and 15-22 are rejected under 35 U.S.C. 103 as being unpatentable over Vantrease et al. (U.S. Patent Application Publication No: US 20190294413 A1) cited in IDS on 7/22/2022, hereinafter “Vantrease”, in view of Inayat Ullah in NPL: “Factored Radix-8 Systolic Array for Tensor Processing” cited in IDS on 7/22/2022, hereinafter “Ullah”, further in view of Hao Zhang in NPL: “New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference” (https://ieeexplore.ieee.org/abstract/document/8825551), hereinafter “Zhang”.
With regards to Claim 1, Vantrease teaches a system comprising:
a plurality of cells arranged in a systolic array (Fig. 6, e.g., Plurality of PEs (Cells) arranged in a systolic array; ¶0074-0075), wherein each cell comprises:
multiplication circuitry configured to determine a product of elements of input matrices (¶0077, e.g., Each PE contains multiplier 623; Fig. 6);
an accumulator configured to determine an accumulated value by accumulating a sum of the products output by the multiplication circuitry (¶0077, e.g., Each PE contains adder 625 which accumulates values from other PEs and the product from the multiplier 623); and
a post-processing component [outside the systolic array] configured to determine a post-processed value by performing one or more post-processing operations on the accumulated value (Fig. 5, e.g., Post-processor 528; ¶0080, e.g., post-processor 528 may include activation engine 528a to perform one or more activation functions (post-processing operations) to generate output data (post-processed value)), wherein the post- processing component is programmable (¶0127, e.g., processing logic 1102 (which may include neural network processor) may process instructions stored in the form of a computer program (programmable). Fig. 5, e.g., Neural network processor 502 includes Post-processor 528, hence Post processor 528 is considered programable) … and performing an activation function using the accumulated value (¶0080, e.g., Post-processor 528 includes activation engine 528a, which performs activation (non-linear) functions such as ReLu) …
Vantrease does not teach:
wherein each cell comprises: … a post-processing component configured to determine a post-processed value by performing one or more post-processing operations on the accumulated value, … and is configured to perform multiple different post-processing operations comprising rounding the accumulated value … , and wherein the post-processing component is configured to selectively perform one of the multiple different post-processing operations based on a control signal.
However, in the same field of endeavor, Ullah teaches a systolic array where each PE, or cell, contains a post processing block in each cell to produce output Q. Ullah explains “The P -dedicated postprocessing takes the MAC output and produces Q” (See Section 3. Proposed design, subsection 3.1 A General Idea for Systolic Arrays; Fig. 2 (a)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the teaching of implementing Post-processing logic in each PE as taught by Ullah with the Post-processor and the PEs in the systolic array as taught by Vantrease. One would have been motivated to combine these references because both references disclose systolic arrays to be implemented in convolutional neural networks, and Ullah enhances the model of Vantrease by allowing for low latency in each post processing operation.
Vantrease in view of Ullah do not teach:
and is configured to perform multiple different post-processing operations comprising rounding the accumulated value … , and wherein the post-processing component is configured to selectively perform one of the multiple different post-processing operations based on a control signal.
However, Zhang teaches:
and is configured to perform multiple different post-processing operations comprising rounding the accumulated value (Fig. 2, e.g., shows normalization shifter, floating-point rounding, fixed-point rounding, and output processing blocks (multiple different post-processing operations), each block performs floating-point rounding), and wherein the post-processing component is configured to selectively perform one of the multiple post-processing operations based on a control signal (Section 3 The Proposed Flexible Multiple Precision Multiply Accumulate Unit, Paragraph under Table 2, e.g., 2-bit MODE signal (control signal) controls the precision mode and the operation to be performed (one of the multiple post-processing operations)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify post processing component as taught by Vantrease in view of Ullah to include the normalization shifter, floating-point rounding, fixed-point rounding, and output processing blocks as taught by Zhang. One would have been motivated to combine these references because both references disclose solving convolutional neural networks using Processing Elements, and Zhang enhances the model of Vantrease in view of Ullah because "further energy reduction can be achieved when each operation step can use its minimum required precision instead of being forced to use a uniform precision for all steps." (Zhang: Section 1 Introduction, third paragraph)
With regards to Claim 2, Vantrease in view of Ullah in view of Zhang teach:
The matrix multiplication unit of claim 1, wherein each cell further comprises an output register configured to receive the post-processed value (Zhang: Fig. 2, e.g., Output registers receive data from the output processing block) and shift the post-processed value out of the cell (Zhang: Fig. 2, e.g., Output processing outputs (shifts) post-processed values outside of the MAC unit (Cells)).
The motivation to combine provided with respect to claim 1 applies equally to claim 2.
With regards to Claim 3, Vantrease in view of Ullah in view of Zhang teach:
The matrix multiplication unit of claim 1, wherein at least one of the multiple different post-processing operations of the post-processing component comprises rounding the accumulated value from a higher precision number format to a lower precision number format (Zhang: Fig. 2, e.g., floating-point rounding block is included between the pipeline registers 2 and output registers (post-processing component) and receives sum output (accumulated value); Fig. 11, e.g., rounds from 48 bits to 16 bits).
The motivation to combine provided with respect to claim 1 applies equally to claim 3.
With regards to Claim 4, Vantrease in view of Ullah in view of Zhang teach:
The matrix multiplication unit of claim 1 wherein:
the post-processing component comprises rounding circuitry configured to round the accumulated value from a higher precision number format to a lower precision number format (Zhang: Fig. 2, e.g., floating-point rounding block is included between the pipeline registers 2 and output registers (post-processing component) and receives sum output (accumulated value); Fig. 11, e.g., rounds from 48 bits to 16 bits);
Zhang further teaches:
and each cell contains a number of output wires equal to a number of bits of the lower precision number format (Fig. 2, e.g., bit-width of the output register is 16 (lower precision number format)).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the bit-width (output wires) to be the amount of the lower precision format as taught by Zhang with the PEs in the systolic array as taught by Vantrease in view of Ullah. One would have been motivated to combine these references because both references disclose solving convolutional neural networks, Zhang enhances the model of Vantrease in view of Ullah because it can "provide almost the same accuracy with much lower hardware cost." (Zhang: Section 4 Results and Analysis, Tenth paragraph).
With regards to Claim 5, Vantrease in view of Ullah in view of Zhang teach:
The matrix multiplication unit of claim 1, wherein at least one of the multiple different post-processing operations of the post-processing component comprises truncating the accumulated value from a higher precision number format to a lower precision number format (Zhang: Section 3 New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference, Subsection 3.8 Output Processing, First Paragraph, e.g., Truncates from a higher precision to a 16-bit result (lower precision number format)).
The motivation to combine provided with respect to claim 1 applies equally to claim 5.
With regards to Claim 6, Vantrease in view of Ullah in view of Zhang teach:
The matrix multiplication unit of claim 1, wherein the post-processing component comprises rectified linear unit (ReLU) circuitry (Vantrease: ¶0023, e.g., Each neuron applies a nonlinear function to the weighted sum; ¶0080, e.g., Post-processor 528 includes activation engine 528a, which performs activation (non-linear) functions such as ReLu) configured to:
output the accumulated value when the accumulated value is positive (Vantrease: ¶0032, e.g., Real-valued input (accumulated value) is threshold to zero, hence it is outputted if positive.); and
output a value of zero when the accumulated value is negative or zero (Vantrease: ¶0032, e.g., ReLu replaces negative values with zeros).
The motivation to combine provided with respect to claim 1 applies equally to claim 6.
With regards to Claims 8-13, they are similar to the claimed matrix multiplication unit above (claims 1-6 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, these claims are rejected for at least the same reasons therein.
Regarding claims 15-20, they are method claims practiced by the apparatus of claims 1-6. It is rejected for the same reasons as claims 1-6.
With regards to Claim 21, Vantrease in view of Ullah in view of Zhang teach:
The matrix multiplication unit of claim 1, wherein the multiple different post-processing operations comprise truncating the accumulated value (Zhang: Section 3 New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference, Subsection 3.8 Output Processing, First Paragraph, e.g., Truncates from a higher precision to a 16-bit result (lower precision number format)).
The motivation to combine provided with respect to claim 1 applies equally to claim 21.
With regards to Claim 22, Vantrease in view of Ullah in view of Zhang teach:
The matrix multiplication unit of claim 1, wherein the multiple different post-processing operations comprise multiple activation functions (Vantrease: Fig. 5, e.g., Post-processor 528 includes Activation engine 528a; ¶0032, e.g., several activation functions may be used)
Prior art made of record
US 12518167 B1 – teaches a processing engine array 740 that performs multiply-accumulate operations, where each input is held in registers inside the cell. See Fig. 7 and corresponding description.
Conclusion
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182