Office Action Predictor
Application No. 17/531,079

CARRIER CONFINEMENT IN LEDS BY VALENCE BAND ENGINEERING

Final Rejection §102
Filed
Nov 19, 2021
Examiner
KOLAHDOUZAN, HAJAR
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Meta Platforms Technologies, LLC
OA Round
2 (Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
99%
With Interview

Examiner Intelligence

74%
Career Allow Rate
263 granted / 356 resolved
Without
With
+36.4%
Interview Lift
avg trend
2y 10m
Avg Prosecution
22 pending
378
Total Applications
career history

Statute-Specific Performance

§103
57.6%
+17.6% vs TC avg
§102
32.4%
-7.6% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments in “Remarks – 06/10/2025- Applicant Arguments/Remarks Made in an Amendment”, with the “Amendment/Req. Reconsideration-After Non-Final Reject -06/10/2025", have been fully considered, but they are not persuasive, because of the following: Applicant’s amendment of claims 1-17 necessitated the shift in new grounds of rejection detailed above in section below. The shift in grounds of rejection renders Applicant’s arguments moot. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bour et al. (US 20170170360 A1; hereinafter Bour). Regarding Claim 1, Bour (Fig.19-20) discloses a micro-light emitting diode comprising: a substrate (growth substrate 102, temporary substrate 140 or layer 104); an n-type semiconductor layer (106; [0141]) on the substrate; a p-type semiconductor layer (110; [0141]); an active region (108; [0142]) between the n-type semiconductor layer (106) and the p-type semiconductor layer (110) and configured to emit red light ([0083]), the active region comprising: a barrier layer (109; [0147]) characterized by a first lattice constant; and a quantum well layer (107; [0147]) next to the barrier layer, the quantum well layer characterized by a second lattice constant greater than the first lattice constant and by an in-plane compressive strain ([0147]-[0149]), wherein the active region is characterized by a lateral linear dimension equal to or less than 10 um ([0140]); and a secondary optical component (112; Fig.19A; [0151]; 112 is a spreading layer which is an optical component containing phosphorus that results in emitting red light). Regarding Claim 2. (Original) The micro-light emitting diode of claim 1, Bour (Figs.19-20; [0131], [0147]) discloses wherein the substrate is characterized by a third lattice constant that matches the first lattice constant (Bour discloses that the substrate 104 and barrier layer are formed of (AlGa)0.5In0.5P which are lattice match over all possible Al and Ga ratios). Regarding Claim 3. (Original) The micro-light emitting diode of claim 1, Bour (Figs.19-20; [0147]- [0149]) discloses wherein: the quantum well layer (107) is characterized by an energy band structure including a heavy- hole band and a light-hole band in a valence band; and a top of the heavy-hole band is higher than a top of the light-hole band (Bour discloses that the quantum well is compressively strained which implies the desired energy band as recited). Regarding Claim 4. (Original) The micro-light emitting diode of claim 3, Bour (Figs.19-20; [0130], [0147]) discloses wherein a difference between the top of the heavy-hole band and the top of the light-hole band is greater than 0.075 eV at room temperature (Bour discloses that substrate 130 is GaAs, the quantum barrier is (Al0.7Ga0.3)0.5In0.5P and quantum well is (Al0.2Ga0.8)0.4In0.6P which results in a compressive strain of 0.75%. Regarding Claim 5. (Original) The micro-light emitting diode of claim 1, Bour (Figs.19-20; [0130], [0147]) discloses wherein: the substrate includes a GaAs substrate; the barrier layer includes a (AlxGa1-x)0.5In0.5P layer; and the quantum well layer includes a GayIn1-yP or (AlxGa1-x)yln1-yP layer, wherein y is less than 0.5. Regarding Claim 6. (Original) The micro-light emitting diode of claim 1, Bour (Figs.19-20; [0147]) discloses wherein a difference between the second lattice constant and the first lattice constant is greater than 1% of the first lattice constant. Regarding Claim 7. (Original) The micro-light emitting diode of claim 1, Bour (Figs.19-20; [0081]) discloses wherein the red light is characterized by a wavelength greater than 600 nm. Regarding Claim 8. (Original) The micro-light emitting diode of claim 1, Bour (Figs.19f; [0139]) discloses wherein the active region includes a plurality of quantum well layers (107) interleaved with a plurality of barrier layers (109), the plurality of quantum well layers including the quantum well layer. Regarding Claim 9. (Original) The micro-light emitting diode of claim 1, Bour (Figs.19e-f; [0139]-[0144]) discloses further comprising a passivation layer (intermixed region 1902 act as a current blocking layer) on sidewalls of the active region. Regarding Claim 10. (Original) The micro-light emitting diode of claim 1, Bour ([0144];[0147]) discloses wherein a thickness of the quantum well layer (107) is less than a thickness of the barrier layer (109). Regarding Claim 11, Bour (Figs.19-20; [0131], [0147]) discloses A device comprising: a substrate (growth substrate 102, temporary substrate 140 or layer 104); and an array of micro-light emitting diodes on the substrate, each micro-light emitting diode of the array of micro-light emitting diodes comprising a mesa structure (120; Fig.17; [0071], ) that comprises: an n-type semiconductor layer (106; [0141]); a p-type semiconductor layer (110; [0141]); an active region (108; [0142]) between the n-type semiconductor layer (106) and the p-type semiconductor layer (110) and configured to emit red light ([0083]), the active region comprising: a barrier layer (109; [0147]) characterized by a first lattice constant; and a quantum well layer (107; [0147]) next to the barrier layer, the quantum well layer characterized by a second lattice constant greater than the first lattice constant and by an in-plane compressive strain ([0147]-[0149]), wherein the active region is characterized by a lateral linear dimension equal to or less than 10 um ([0140]) and a secondary optical component (112; Fig.19A; [0151]; 112 is a spreading layer which is an optical component containing phosphorus that results in emitting red light). Regarding Claim 12. (Original) The micro-light emitting diode of claim 11, Bour (Figs.19-20; [0131], [0147]) discloses wherein the substrate is characterized by a third lattice constant that matches the first lattice constant (Bour discloses that the substrate 104 and barrier layer are formed of (AlGa)0.5In0.5P which are lattice match over all possible Al and Ga ratios). Regarding Claim 13. (Original) The micro-light emitting diode of claim 11, Bour (Figs.19-20; [0147]- [0149]) discloses wherein: the quantum well layer (107) is characterized by an energy band structure including a heavy- hole band and a light-hole band in a valence band; and a top of the heavy-hole band is higher than a top of the light-hole band (Bour discloses that the quantum well is compressively strained which implies the desired energy band as recited). Regarding Claim 14, (Original) The micro-light emitting diode of claim 13, Bour (Figs.19-20; [0130],[0147]) discloses wherein a difference between the top of the heavy-hole band and the top of the light-hole band is greater than 0.075 eV at room temperature (Bour discloses that substrate 130 is GaAs, the quantum barrier is (Al0.7Ga0.3)0.5In0.5P and quantum well is (Al0.2Ga0.8)0.4In0.6P which results in a compressive strain of 0.75%. Regarding Claim 15, (Original) The micro-light emitting diode of claim 11, Bour (Figs.19-20; [0130], [0147]) discloses wherein: the substrate includes a GaAs substrate; the barrier layer includes a (AlxGa1-x)0.5In0.5P layer; and the quantum well layer includes a GayIn1-yP or (AlxGa1-x)yln1-yP layer, wherein y is less than 0.5. Regarding Claim 16. (Original) The micro-light emitting diode of claim 11, Bour (Figs.19-20; [0147]) discloses wherein a difference between the second lattice constant and the first lattice constant is greater than 1% of the first lattice constant. Regarding Claim 17. (Original) The device of claim 11, Bour (Figs.17-20; abstract) discloses wherein the mesa structure is characterized by a vertical, conical, parabolic, inward-tilted, or outward-tilted shape (abstract discloses vertical). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Ojha can be reached on (571)272-8936. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAJAR KOLAHDOUZAN/ Examiner, Art Unit 2898 /AJAY OJHA/Supervisory Patent Examiner, Art Unit 2898 8/11/2025
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Prosecution Timeline

Nov 19, 2021
Application Filed
Mar 07, 2025
Non-Final Rejection — §102
Jun 10, 2025
Response Filed
Aug 05, 2025
Final Rejection — §102
Apr 13, 2026
Response after Non-Final Action

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+36.4%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 356 resolved cases by this examiner