Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is final and is in response to claims filed on 02/20/2026 via Amendment. Claims 1-20 are pending for examination. Claims 1, 9, and 17 are currently amended. Claims 2-8, 10-16, and 18-20 are as previously filed.
Response to Arguments
Rejections Under 35 U.S.C. 112
Applicant has amended the claims at issue and therefore the previous rejections have been withdrawn.
Rejections under 35 U.S.C. 103
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Rejections under 25 U.S.C. 101
Applicant’s arguments regarding the 35 U.S.C. 101 rejections have been fully considered. Applicant argues that “During the course of training a machine learning model, the reciprocal function and/or the reciprocal-square-root function may be computed a massive number of times (e.g., billions or trillions of times, or more, depending on the size and complexity of the model)”. See Remarks 13 filed 02/20/2026.
Examiner respectfully disagrees with Applicant’s arguments. The machine learning model is not recited in the claims. These purported improvements are not recited in the claims nor can they be explicitly observed from the claim language.
Applicant further argues “Embodiments of the present disclosure are directed to specific improvements in the implementation of the computations in FPGAs and not merely performing a mental process on a generic computer”. See Remarks 13.
Examiner respectfully disagrees with Applicant’s arguments. The FPGAs are recited at a high level of generality and is a clear “apply it” scenario using generic computer components. MPEP 2106.05(f). The integer multiplier does not denote any specific structure and is merely a generic circuit component performing the abstract ideas (multiplying the slope by the M-L bits, etc.).
Applicant further argues “Furthermore, the flexibility of an FPGA allows the integer multiplier to be implemented in the FPGA using only as many bits as necessary to multiply integers having these short bit lengths, thereby resulting in the savings in FPGA area, resulting in reduced power consumption for a given data path and allowing for increased density of data paths, such as multiple parallel data paths, to increase overall throughput of computations, with negligible impact on the output”. See Remarks 15.
Examiner respectfully disagrees with Applicant’s arguments. The FPGAs and integer multiplier recited at a high level of generality and is a clear “apply it” scenario using generic computer components. MPEP 2106.05(f). The integer multiplier does not denote any specific structure and is merely a generic circuit component performing the abstract ideas (multiplying the slope by the M-L bits, etc.).
It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception... However, it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology...”. See MPEP 2106.05(a).
Applicant further argues “the claimed embodiments do not recite a mental process at least because humans operate on numerical values represented in decimal (base 10), not binary (base 2), and that computations of reciprocals (or reciprocal square roots) would typically be based on performing long-division, not performing lookups in a lookup table”. See Remarks 16.
Examiner respectfully disagrees with Applicant’s arguments. What is typical for humans to do does not matter only that the claimed limitations are capable of being performed in the human mind with the aid of pen and paper. These limitations are capable of being performed in the human mind.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
With regards to claim 1, at Step 1, the claim is directed to a machine, which is a statutory category of invention.
At step 2A prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical calculations. The claim language has been reproduced below:
A field programmable gate array (FPGA) comprising a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a reciprocal function data path comprising: (mental process, evaluation)
a mantissa computation stage comprising a mantissa portion of the reciprocal function data path (mental process, evaluation), implemented by the logic blocks and the configurable interconnect fabric, configured to:
partition an M-bit mantissa component of an input floating-point value into L most- significant bits and M-L least significant bits (Mathematical calculations), wherein the input floating-point value is represented in a low-precision binary floating-point data format where M is less than 23; (mental process, evaluation; mathematical relationship)
lookup a slope value and an offset value, based on the L most significant bits, from a linear interpolation lookup table (mental process, evaluation; mathematical relationship) comprising a reciprocal lookup table having 2L entries and storing a plurality of pre-computed slope and offset values, (mental process, observation) each of the pre-computed slope values having a first bit length; (mental process, evaluation) and
compute an output mantissa component of an output floating-point value by multiplying, using an integer multiplier, the slope value having the first bit length by the M-L least significant bits having a second bit length different from the first bit length to compute a product and adding the offset value to the product, (mathematical calculations) the integer multiplier being configured to multiply a first integer having a first bit length by a second integer having the second bit length (mental process, evaluation; mathematical calculation) and to output the product as an integer having a bit length equal to the sum the first bit length and the second bit length, (mathematical calculation); and
an exponent computation stage comprising (mental process, evaluation) a plurality of adders, implemented by the logic blocks and the configurable interconnect fabric, configured to compute an output exponent component of the output floating-point value (mathematical calculations), the computing the output exponent component comprising negating an exponent component of the input floating-point value (mathematical calculations).
Each of the nonbolded limitations are mental processes and/or mathematical calculations. The “implement a reciprocal function” limitation is an evaluation mental process that can be performed by choosing what functions to calculate. The “a mantissa computation stage” limitation is an evaluation mental process that can be accomplished by choosing to calculate the mantissa by hand. The “partition an M-bit mantissa” limitations is a mathematical calculation, that can be done by one choosing the amount of most significant bits and then subtracting that from the total number of bits to find the least significant bits using pen and paper. The “wherein the input floating-point value is represented in a low-precision binary” limitation is an evaluation mental process and mathematical relationship, that can be performed by choosing the length of the inputs. The “lookup a slope value and offset value” limitation is an evaluation mental process and mathematical relationship, that can be performed by physically looking up the slope and offset from a table on paper. The “comprising a reciprocal” limitation is an observation mental process, that can be accomplished by choosing what is in a physical lookup table. The “each of the pre-computed slope values having a first bit length” limitation is an evaluation mental process that can be performed by choosing how many bits the slope values have. The “compute an output mantissa” limitation is a mathematical calculation that can be accomplished by multiplying the slope and adding the offset using pen and paper. The “the integer multiplier being configured to multiply” limitation is an evaluation mental process and mathematical calculation that can be performed by choosing what the integer multiplier is configured to do and performing the multiplication by hand using pen and paper. The “and to output the product as an integer” limitation is a mathematical calculation that can be performed by multiplying the numbers by hand using pen and paper and choosing how many bits to use to represent them. The “an exponent computation stage” limitation is an evaluation mental process that can be performed by choosing to calculate the exponent by hand. The “configured to compute an output exponent” limitation is a mathematical calculation, that can be accomplished by calculating the exponent using pen and paper. The “the computing the output exponent component” limitation is a mathematical calculation that can be accomplished by negating the exponent using pen and paper.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements are generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(g).
At step 2B, the claim does not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claims 9 and 17, they recite similar language to claim 1, and are rejected for at least the same reasons therein. Herein claims 9 and 17 are directed towards the statutory categories of an article of manufacture and method respectively, thus also satisfying step 1. Moreover, none of the additional elements regarding the generic computer components (i.e. computer storage media, a configuration file, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
With regards to claim 2, at Step 1, the claim is directed to a machine, which is a statutory category of invention.
At step 2A prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical calculations. The claim language has been reproduced below:
The FPGA of claim 1, wherein the configurable interconnect fabric and the logic blocks are further configured to implement a reciprocal-square-root function data path comprising: (mental process, evaluation)
a mantissa portion implemented (mental process, evaluation) by the logic blocks and the configurable interconnect fabric of the mantissa computation stage; and
an exponent portion implemented (mental process, evaluation) by the logic blocks and the configurable interconnect fabric of the exponent computation stage, and
wherein the mantissa computation stage and the exponent computation stage are configured to select between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value (mental process, evaluation).
Each of the nonbolded limitations are mental processes and/or mathematical calculations. The “are further configured to implement a reciprocal-square-root” limitation is an evaluation mental process that can be performed by choosing what kind of functions one wants to calculate. The “a mantissa portion implemented” limitation is an evaluation mental process that can be performed by choosing to calculate the mantissa by hand. The “an exponent portion implemented” limitation is an evaluation mental process that can be performed by choosing to calculate the exponent by hand. The “wherein the mantissa computation” limitation is an evaluation mental process, that can be performed by one choosing which function to perform.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements are generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
At step 2B, the claim does not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 10, it recites similar language to claim 2, and is rejected for at least the same reasons therein. Herein claim 10 is directed towards the statutory category of an article of manufacture thus also satisfying step 1. Moreover, none of the additional elements regarding the generic computer components (i.e. computer storage media, a configuration file, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
With regards to claims 3 and 11, they are directed to mathematical calculations. The “wherein the exponent” limitation can be performed by dividing the exponent by 2 and negating it using pen and paper. The “wherein the mantissa portion” limitation can be performed by calculating the linear interpolation using pen and paper. Under steps 2A Prong 2 and 2B, the claims do not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception. See MPEP 2106.05(f).
With regards to claims 4 and 12, they are directed to mathematical calculations. The “determine a parity” limitation can be performed by finding the parity of the exponent using pen and paper. The “compute an exponent sum” limitation can be performed by suing the parity to calculate an exponent sum using pen and paper. The “divide the exponent sum” limitation can be performed by dividing the exponent sum by two using pen and paper. Under steps 2A Prong 2 and 2B, the claims do not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception. See MPEP 2106.05(f).
With regards to claims 5 and 13, they are directed to mental processes and/or mathematical calculations. The “wherein the linear” limitation is an observation mental process, that can be accomplished by choosing what is in a physical lookup table. The “wherein the mantissa portion” limitation is an evaluation mental process and mathematical relationship, that can be performed by physically looking up the slope and offset from a table on paper. Under steps 2A Prong 2 and 2B, the claims do not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception. See MPEP 2106.05(f).
With regards to claims 6, 14, and 19, they are directed to an evaluation mental process. One can simply choose the domain of the entries of a physical lookup table. Under steps 2A Prong 2 and 2B, the claims do not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception. See MPEP 2106.05(f).
With regards to claims 7 and 15, they are directed to an evaluation mental process. One can choose to use the same adder and multiplier when performing different functions. Under steps 2A Prong 2 the additional elements are “an integer multiplier and an adder.” The additional element are generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f). At step 2B, the claim does not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 8, at Step 1, the claim is directed to a machine, which is a statutory category of invention.
At step 2A prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical calculations. The claim language has been reproduced below:
The FPGA of claim 2, wherein the mantissa computation stage is further configured to lookup the slope value and the offset value from the linear interpolation lookup table (mental process, evaluation; mathematical relationship), the linear interpolation lookup table further comprising a reciprocal-square-root lookup table (mental process, observation), based on the L most significant bits, the function selection input value, and a parity of the exponent component of the input floating-point value (mental process, evaluation; mathematical relationship), and
wherein the exponent computation stage is further configured to:
compute a reciprocal-square-root exponent adjustment value based on the parity of the exponent component of the input floating-point value and a most significant bit of an intermediate mantissa value computed by the mantissa computation stage (mathematical calculation);
compute a reciprocal exponent adjustment value based on the most significant bit of the intermediate mantissa value (mathematical calculation);
generate an exponent adjustment value selected from the reciprocal-square-root exponent adjustment value and the reciprocal exponent adjustment value based on the function selection input value (mental process, evaluation);
negate the exponent component of the input floating-point value based on the exponent adjustment value to compute an exponent sum value (mathematical calculation); and
divide the exponent sum value by two to compute the output exponent component of the output floating-point value when the function selection input value indicates a reciprocal-square-root function (mathematical calculation).
Each of the nonbolded limitations are mental processes and/or mathematical calculations. The “further configured to lookup the slope value and the offset value” limitation is an evaluation mental process and mathematical relationship, that can be performed by physically looking up the slope and offset from a table on paper. The “the linear interpolation lookup table further comprising” limitation is an observation mental process, that can be accomplished by choosing what is in a physical lookup table. The “based on the L most significant” limitation is an evaluation mental process and mathematical relationship, that can be performed physically looking up the slope and offset from a table on paper using the L most significant bits, the function selection input, and the parity of the input exponent. The “compute a reciprocal-square-root exponent adjustment” limitation is a mathematical calculation, that can be performed by calculating the adjustment value using the parity of the exponent and most significant bit of the intermediate mantissa using pen and paper. The “compute a reciprocal exponent adjustment” limitation is a mathematical calculation, that can be performed by calculating the adjustment value using the most significant bit of the intermediate mantissa and pen and paper. The “generate an exponent adjustment value” limitation is an evaluation mental process, that can be accomplished by choosing which adjustment value to use based on the calculation one is performing. The “negate the exponent” limitation is a mathematical calculation, that can be performed by negating the input exponent using the adjustment value and pen and paper. The “divide the exponent sum value” limitation is a mathematical calculation, that can be performed by dividing the exponent sum value by 2 using pen and paper.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements are generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
At step 2B, the claim does not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 16, it recites similar language to claim 8, and is rejected for at least the same reasons therein. Herein claims 16 is directed towards the statutory categories of an article of manufacture thus also satisfying step 1. Moreover, none of the additional elements regarding the generic computer components (i.e. computer storage media, a configuration file, etc.) are more than high level generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
With regards to claim 18, at Step 1, the claim is directed to a method, which is a statutory category of invention.
At step 2A prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical calculations. The claim language has been reproduced below:
The method of claim 17, wherein the configurable interconnect fabric and the logic blocks are further configured to implement a reciprocal-square-root function data path comprising: (mental process, evaluation)
a mantissa portion implemented (mental process, evaluation) by the logic blocks and the configurable interconnect fabric of the mantissa computation stage; and
an exponent portion implemented (mental process, evaluation) by the logic blocks and the configurable interconnect fabric of the exponent computation stage,
wherein the linear interpolation lookup table further comprises a reciprocal-square-root lookup table, and (mental process, evaluation)
wherein the method further comprises:
selecting between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value; (mental process, evaluation)
dividing the exponent component of the input floating point value by two when the function selection input value indicates a reciprocal-square-root function; and (mathematical calculation)
looking up the slope value and the offset value from the reciprocal-square-root lookup table, based on the L most significant bits and a parity of the exponent component of the input floating-point value when the function selection input value indicates a reciprocal- square-root function. (Mental process, evaluation; mathematical concept)
Each of the nonbolded limitations are mental processes and/or mathematical calculations. The “are further configured to implement a reciprocal-square-root” limitation is an evaluation mental process that can be performed by choosing what kind of functions one wants to calculate. The “a mantissa portion implemented” limitation is an evaluation mental process that can be performed by choosing to calculate the mantissa by hand. The “an exponent portion implemented” limitation is an evaluation mental process that can be performed by choosing to calculate the exponent by hand. The “wherein the linear interpolation lookup table” limitation is an evaluation mental process, that can be performed by one choosing what to include in the lookup table. The “selecting between the reciprocal function” limitation is an evaluation mental process that can be performed by choosing which function to calculate. The “dividing the exponent component” limitation is a mathematical calculation that can be performed by dividing the exponent by two using pen and paper. The “looking up the slope value and the offset value” limitation is an evaluation mental process that can be accomplished by looking up the values in a physical table.
At Step 2A Prong 2, the additional elements are bolded above. The additional elements are generic computer components that amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
At step 2B, the claim does not recite any additional elements that integrate the abstract ideas into a practical application, nor do they amount to significantly more than the judicial exception.
With regards to claim 20, at Step 1, the claim is directed to a method, which is a statutory category of invention.
At step 2A prong 1, the examiner notes that the claim is directed to mental processes and/or mathematical calculations. The claim language has been reproduced below:
The method of claim 18, further comprising training a machine learning model, comprising: receiving, by a machine learning model training application executed by a computing device comprising a processor, memory, and the FPGA, labeled training data;
supplying, by the machine learning model training application, the training data to a first layer of the machine learning model to compute a plurality of K first layer activations (mathematical calculations);
computing a plurality of second layer activations (mathematical calculations) of a second layer of the machine learning model, the computing the plurality of second layer activations comprising supplying the plurality of K first layer activations to the mantissa computation stage and the exponent computation stage of the FPGA, the plurality of second layer activations comprising K reciprocals of the K first layer activations or K reciprocal-square-roots of the K first layer activations (mental process, evaluation);
computing a plurality of normalized scores of the output (mathematical calculation) of the machine learning model in response to the training data;
updating the machine learning model based on the normalized scores; and (mental process, evaluation)
outputting the updated machine learning model as a trained machine learning model.
Each of the nonbolded limitations are mental processes and/or mathematical calculations. The “to compute a plurality of K” limitation is a mathematical calculation that can be performed by calculating the k activations using pen and paper. The “the plurality of second layer activations comprising” limitation can be performed by choosing what comprises the second layer activations. The “computing a plurality of normalized scores” limitation is a mathematical calculation that can be performed by normalizing the scores using pen and paper. The “updating the machine learning model based on the normalized scores” limitation is an evaluation mental process that can be performed by manually updating the model.
At Step 2A Prong 2, the additional elements are bolded above. The “receiving” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. For example, the ‘receiving’ in the context of the claim is encompasses mere data gathering used for the claimed calculating step. The “supplying” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. For example, the ‘supplying’ in the context of the claim is encompasses mere data gathering used for the claimed computing step. The “outputting” limitation, as claimed under BRI, is an additional element that is insignificant extra-solution activity. For example, the ‘outputting’ in the context of the claim is encompasses mere data gathering. See MPEP 2106.05(g). The remaining additional elements amount to no more than components comprising mere instructions to apply the exception and do not integrate the judicial exception into a practical application. See MPEP 2106.05(f).
At Step 2B, the claim recites “receiving, by a machine learning model training application executed by a computing device comprising,” “supplying, by the machine learning model training application, the training data to a first layer of the machine learning model,” and “outputting the updated machine learning model as a trained machine learning model” and, per MPEP 2106.05(d) (Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 9-13, 15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dhong et al. ( US Patent Application No. US 20060259745 A1) hereinafter Dhong in view of Arrow (“FPGA basics: Architecture, applications and uses”) further in view of Lutz et al. (US Patent Application No. US 20060184594 A1) hereinafter Lutz further in view of Schulte et al. (US 20080301213 A1) hereinafter Schulte further in view of Shankar et al. (WO 0045254 A1) hereinafter Shankar further in view of Mangnall et al. (US 20200293278 A1) hereinafter Mangnall.
With regards to claim 1, Dhong teaches implement a reciprocal function data path comprising: (Dhong [0021]: A preferred embodiment of the present intention is directed to a processor architecture and instruction set containing efficient instructions for estimating the values of particular floating-point functions. Specifically, a preferred embodiment of the present invention is directed to function estimate instructions for the reciprocal function)
a mantissa computation stage comprising a mantissa portion of the reciprocal function data path, [implemented by the logic blocks and the configurable interconnect fabric] configured to: (Dhong Fig. 3 and Fig. 4: show the mantissa computation stage)
partition an M-bit mantissa component of an input floating-point value into L most- significant bits (Dhong Fig. 3: shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits; Dhong [0029]: the five most significant bits of the mantissa of floating point number)
and M-L least significant bits; (Dhong Fig. 3: shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits; Dhong [0033]: the eighteen least significant bits 400 in the mantissa of X (floating point number 300))
lookup a slope value and an offset value, based on the L most significant bits, from a linear interpolation lookup table comprising a reciprocal lookup table having 2L entries and storing a plurality of pre-computed slope and offset values, (Dhong [0029]: the five most significant bits of the mantissa of floating point number 300 are used as an index to look up table 304, which contains base and slope values for each of the 32 different combinations of the five most significant bits of an arbitrary mantissa)
each of the pre-computed slope values having a first bit length; (Dhong fig. 4: shows that the slopes have a number of bits)
and compute an output mantissa component of an output floating-point value by multiplying, [using an integer multiplier], the slope value having the first bit length by the M-L least significant bits having a second bit length different from the first bit length to compute a product and adding the offset value to the product, (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it; Dhong [0030]: a 10-bit slope value 314; Dhong Fig. 3: shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits)
[the integer multiplier] being configured to multiply a first [integer] having the first bit length by a second [integer] having the second bit length (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it)
and to output the product [as an integer having a number of bits equal to the sum of the first bit length and the second bit length;] (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it)
and an exponent computation stage comprising a plurality of adders, (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300)
configured to compute an output exponent component of the output floating-point value (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300).
Dhong fails to teach the computing the output exponent component comprising negating an exponent component of the input floating-point value.
However, Lutz does teach the computing the output exponent component comprising negating an exponent component of the input floating-point value(Lutz [0024]: negating the exponent of the input value).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the exponent and mantissa computation stages as taught by Dhong with negating the exponent as taught by Lutz. One of ordinary skill in the art would have been motivated to make this combination because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
Dhong in view of Lutz fails to teach A field programmable gate array (FPGA) comprising a configurable interconnect fabric connecting a plurality of logic blocks.
Dhong in view of Lutz further fails to teach the configurable interconnect fabric and the logic blocks being configured to
Dhong in view of Lutz further fails to teach implemented by the logic blocks and the configurable interconnect fabric,
However, Arrow does teach A field programmable gate array (FPGA) (Arrow Section What is FPGA: Field Programmable Gate Array (FPGA))
comprising a configurable interconnect fabric (Arrow Section FPGA Architecture: surrounded by a system of programmable interconnects, called a fabric)
connecting a plurality of logic blocks (Arrow Section FPGA Architecture: configurable logic blocks (CLBs)).
the configurable interconnect fabric and the logic blocks being configured to (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric)
implemented by the logic blocks and the configurable interconnect fabric, ((Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this combination because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
Dhong in view of Lutz further in view of Arrow fails to teach an integer multiplier, the inputs being integers, outputting the product as an integer.
However, Shankar does teach an integer multiplier (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations)
the inputs being integers (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations
Outputting the product of Dhong in view of Lutz further in view of Arrow as an integer ((Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations)
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow with the integer multiplier, the inputs being integers, and outputting the product as an integer as taught by Shankar. One of ordinary skill in the art would have been motivated to make this combination because Integer multipliers can process more data faster than floating point multipliers because they do not have to deal with exponents, speeding up calculations.
Dhong in view of Lutz further in view of Arrow further in view of Shankar fails to teach the product [as an integer] having a number of bits equal to the sum of the first bit length and the second bit length.
However, Schulte does teach the product of Dhong in view of Lutz further in view of Arrow further in view of Shankar [as an integer] having a number of bits equal to the sum of the first bit length and the second bit length; (Schulte [0015]: Referring to FIG. 4, a particular embodiment of a rectangular floating point multiplier 430, corresponding to the multiplier 130 of FIG. 1 is illustrated. The rectangular floating-point multiplier is implemented in two pipeline stages as shown in FIG. 4. The first stage 402 includes of a 76-bit.times.27-bit multiplier which accepts a 76-bit feedback term in a redundant carry-save format and produces a 103-bit product in a redundant carry-save format).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar with the output length as taught by Schulte. One of ordinary skill in the art would have been motivated to make this combination because the division operations can be executed more efficiently at the multiplier 130 than with a multiplier that uses operands of equal sizes, while still achieving the desired level of precision for the quotient Q as taught by Schulte (Schulte [0017]).
Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte fails to teach wherein the input floating-point value is represented in a low-precision binary floating-point data format where M is less than 23.
However, Mangnall teaches wherein the input floating-point value is represented in a low-precision binary floating-point data format where M is less than 23 (Mangnall [0093]: in some examples, the floating point numbers may be expressed at a different precision level, e.g. in half (16 bit) precision).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte with the input format as taught by Mangnall. One of ordinary skill in the art would have been motivated to make this combination because it would increase the efficiency of system as the 16 bit numbers would require less resources to process. Also, it can be particularly efficient to cause the bit slices to be are of varying length, such that they can be handled by look up tables or estimation, depending on their significance as taught by Mangnall (Mangnall [0213]).
With regards to claim 2, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 1 above. Dhong further teaches wherein [the configurable interconnect fabric and the logic blocks are further configured] to implement a reciprocal-square-root function data path comprising: (Dhong [0021]: a preferred embodiment of the present invention is directed to function estimate instructions for the reciprocal function (1/x) and reciprocal square root function)
a mantissa portion implemented by [the logic blocks and the configurable interconnect fabric] of the mantissa computation stage; (Dhong Fig. 3 and Fig. 4 show the mantissa computation stage)
and an exponent portion implemented by the [logic blocks and the configurable interconnect fabric] of the exponent computation stage (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300).
Dhong fails to explicitly teach and wherein the mantissa computation stage and the exponent computation stage are configured to select between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value
However Lutz does explicitly teach and wherein the mantissa computation stage and the exponent computation stage are configured to select between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value (Lutz [0042]: which decodes the instruction and then dependent on the instruction sends appropriate control signals to other elements of the data processing apparatus to cause the operation specified by the instruction to be implemented).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the selection of the datapath as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change for at least the same reasons as claim 1 above as well as because it would reduce the size of the processor as there would not need to be a separate set of components for each data path.
Dhong in view of Lutz fails to teach the logic blocks and the configurable interconnect fabric.
However, Arrow does teach the logic blocks and the configurable interconnect fabric (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this combination because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
With regards to claim 3, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 2 above. Dhong further teaches and wherein the mantissa portion of the reciprocal-square-root function data path is configured to perform a linear interpolation of a reciprocal-square-root over a domain of the M-bit mantissa component of the input floating-point value (Dhong [0027]: the processor executes a second instruction on the previously obtained base value and slope, in which the processor uses the base value and slope to perform linear interpolation to obtain an estimate of the desired function evaluated at the value of the original operand).
Dhong fails to teach wherein the exponent portion of the reciprocal-square-root function data path is further configured to negate and divide the exponent component of the input floating- point value by two.
However, Lutz does teach wherein the exponent portion of the reciprocal-square-root function data path is further configured to negate and divide the exponent component of the input floating- point value by two; (Lutz [0059]: producing the exponent of the estimate of the result value by halving and negating the exponent).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the exponent and mantissa computation stages as taught by Dhong with negating the exponent and dividing by 2 as taught by Lutz. One of ordinary skill in the art would have been motivated to make this combination because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
With regards to claim 4, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 3 above. Dhong further teaches wherein the exponent portion of the reciprocal-square-root function data path is further configured to: determine a parity of the exponent component of the input floating-point value; (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd)
Dhong fails to teach and divide the exponent sum value by two to compute the output exponent component of the output floating-point value and compute an exponent sum value based on the parity of the exponent component.
However, Lutz does teach and divide the exponent sum value by two to compute the output exponent component of the output floating-point value (Lutz [0059]: producing the exponent of the estimate of the result value by halving and negating the exponent).
compute an exponent sum value based on the parity of the exponent component; (Lutz [0027]: the processing logic is operable to select as the modified input value the result of either an effective one bit or an effective two bit right shift of the significand of the input value, along with associated incrementing of the exponent of the input value, such that the modified input value has an exponent which is an even number).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the compute an exponent sum value based on the parity of the exponent component as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change for at least the same reasons as claim 1 above as well as because it would reduce the size of the processor as there would not need to be a separate set of components for each data path.
With regards to claim 5, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 4 above. Dhong further teaches wherein the linear interpolation lookup table further comprises a reciprocal-square-root lookup table, (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd)
and wherein the mantissa portion of the reciprocal-square-root function data path is further configured to: lookup the slope value and the offset value from the reciprocal-square-root lookup table, based on the L most significant bits and the parity of the exponent component of the input floating-point value (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd).
With regards to claim 7, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 2 above. Dhong further teaches wherein the mantissa computation stage comprises [the integer multiplier] and an adder, (Dhong [0008]: the interpolation step does not require a full general-purpose FPU. Instead, it can be executed with a multiplier of reduced size, an adder, and some additional logic).
Dhong does not teach the integer multiplier and the adder being shared by the mantissa portion of the reciprocal function data path and the mantissa portion of the reciprocal-square-root function data path.
However, Lutz does teach [the integer multiplier] and the adder being shared by the mantissa portion of the reciprocal function data path and the mantissa portion of the reciprocal-square-root function data path (Lutz [0040]: FIG. 7 is a diagram schematically illustrating elements provided within the data processing apparatus of FIG. 1 to implement the processes of FIG. 5 and 6; Fig. 5 and Fig. 6 showing the flow diagrams for the reciprocal and reciprocal square root function respectively).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the shared adder and multiplier as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
Dhong in view of Lutz fails to teach the integer multiplier.
However, Shankar does teach the integer multiplier (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the integer multiplier as taught by Shankar. One of ordinary skill in the art would have been motivated to make this combination because Integer multipliers can process more data faster than floating point multipliers because they do not have to deal with exponents, speeding up calculations.
With regards to claim 9, Dhong teaches Computer storage media storing (Dhong [0040]: stored in another computer memory, for example, in a hard disk drive, or in a removable memory such as an optical disk (for eventual use in a CD-ROM) or floppy disk (for eventual use in a floppy disk drive))
implementing: a mantissa computation stage comprising a mantissa portion of a reciprocal function data path, (Dhong [0021] : A preferred embodiment of the present intention is directed to a processor architecture and instruction set containing efficient instructions for estimating the values of particular floating-point functions. Specifically, a preferred embodiment of the present invention is directed to function estimate instructions for the reciprocal function; Dhong Fig. 3 and Fig. 4: Show the mantissa computation stage)
configured to: partition an M-bit mantissa component of an input floating-point value into L most- significant bits (Dhong Fig. 3: shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits; Dhong [0029]: the five most significant bits of the mantissa of floating point number)
and M-L least significant bits; (Dhong Fig. 3: Shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits; Dhong [0033]: the eighteen least significant bits 400 in the mantissa of X (floating point number 300))
lookup a slope value and an offset value, based on the L most significant bits, from a linear interpolation lookup table comprising a reciprocal lookup table having 2L entries and storing a plurality of pre-computed slope and offset values, (Dhong [0029]: the five most significant bits of the mantissa of floating point number 300 are used as an index to look up table 304, which contains base and slope values for each of the 32 different combinations of the five most significant bits of an arbitrary mantissa)
each of the pre-computed slope values having a first bit length; (Dhong fig. 4: shows that the slopes have a number of bits)
and compute an output mantissa component of an output floating-point value by multiplying, [using an integer multiplier], the slope value having the first bit length by the M-L least significant bits having a second bit length different from the first bit length to compute a product and adding the offset value to the product, (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it; Dhong [0030]: a 10-bit slope value 314; Dhong Fig. 3: shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits)
[the integer multiplier] being configured to multiply a first [integer] having the first bit length by a second [integer] having the second bit length (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it)
and to output the product [as an integer having a number of bits equal to the sum of the first bit length and the second bit length;] (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it)
and an exponent computation stage comprising a plurality of adders, (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300)
configured to compute an output exponent component of the output floating-point value (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300).
Dhong fails to teach the computing the output exponent component comprising negating an exponent component of the input floating-point value.
However, Lutz does teach the computing the output exponent component comprising negating an exponent component of the input floating-point value(Lutz [0024]: negating the exponent of the input value).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the exponent and mantissa computation stages as taught by Dhong with negating the exponent as taught by Lutz. One of ordinary skill in the art would have been motivated to make this combination because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
Dhong in view of Lutz fails to teach storing a configuration file, the configuration file specifying a configuration of a field programmable gate array (FPGA) comprising a configurable interconnect fabric and a plurality of logic blocks, where an FPGA configured based on the configuration file comprises logic blocks, connected by the configurable interconnect fabric.
Dhong in view of Lutz further fails to explicitly teach implemented by the logic blocks and the configurable interconnect fabric.
However, Arrow does teach a configuration file, (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
the configuration file specifying a configuration of a field programmable gate array (FPGA) (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
comprising a configurable interconnect fabric and a plurality of logic blocks, (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric)
where an FPGA configured based on the configuration file comprises logic blocks, (Arrow Section FPGA Architecture: configurable logic blocks (CLBs))
connected by the configurable interconnect fabric (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
configuration file comprises logic blocks, connected by the configurable interconnect fabric (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
implemented by the logic blocks and the configurable interconnect fabric ((Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this change because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
Dhong in view of Lutz further in view of Arrow fails to teach an integer multiplier, the inputs being integers, outputting the product as an integer.
However, Shankar does teach an integer multiplier (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations)
the inputs being integers (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations
Outputting the product of Dhong in view of Lutz further in view of Arrow as an integer ((Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations)
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow with the integer multiplier, the inputs being integers, and outputting the product as an integer as taught by Shankar. One of ordinary skill in the art would have been motivated to make this combination because Integer multipliers can process more data faster than floating point multipliers because they do not have to deal with exponents, speeding up calculations.
Dhong in view of Lutz further in view of Arrow further in view of Shankar fails to teach the product [as an integer] having a number of bits equal to the sum of the first bit length and the second bit length.
However, Schulte does teach the product of Dhong in view of Lutz further in view of Arrow further in view of Shankar [as an integer] having a number of bits equal to the sum of the first bit length and the second bit length; (Schulte [0015]: Referring to FIG. 4, a particular embodiment of a rectangular floating point multiplier 430, corresponding to the multiplier 130 of FIG. 1 is illustrated. The rectangular floating-point multiplier is implemented in two pipeline stages as shown in FIG. 4. The first stage 402 includes of a 76-bit.times.27-bit multiplier which accepts a 76-bit feedback term in a redundant carry-save format and produces a 103-bit product in a redundant carry-save format).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar with the output length as taught by Schulte. One of ordinary skill in the art would have been motivated to make this combination because the division operations can be executed more efficiently at the multiplier 130 than with a multiplier that uses operands of equal sizes, while still achieving the desired level of precision for the quotient Q as taught by Schulte (Schulte [0017]).
Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte fails to teach wherein the input floating-point value is represented in a low-precision binary floating-point data format where M is less than 23.
However, Mangnall teaches wherein the input floating-point value is represented in a low-precision binary floating-point data format where M is less than 23 (Mangnall [0093]: in some examples, the floating point numbers may be expressed at a different precision level, e.g. in half (16 bit) precision).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte with the input format as taught by Mangnall. One of ordinary skill in the art would have been motivated to make this combination because it would increase the efficiency of system as the 16 bit numbers would require less resources to process. Also, it can be particularly efficient to cause the bit slices to be are of varying length, such that they can be handled by look up tables or estimation, depending on their significance as taught by Mangnall (Mangnall [0213]).
With regards to claim 10, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 9 above. Dhong further teaches wherein [the configuration file further specifies the configuration of the configurable interconnect fabric and the logic blocks of the FPGA to] implement a reciprocal-square-root function data path comprising: (Dhong [0021]: a preferred embodiment of the present invention is directed to function estimate instructions for the reciprocal function (1/x) and reciprocal square root function)
a mantissa portion implemented by [the logic blocks and the configurable interconnect fabric] of the mantissa computation stage; (Dhong Fig. 3 and Fig. 4 show the mantissa computation stage)
and an exponent portion implemented by the [logic blocks and the configurable interconnect fabric] of the exponent computation stage (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300).
Dhong fails to teach and wherein the mantissa computation stage and the exponent computation stage are configured to select between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value
However Lutz does teach and wherein the mantissa computation stage and the exponent computation stage are configured to select between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value (Lutz [0042]: which decodes the instruction and then dependent on the instruction sends appropriate control signals to other elements of the data processing apparatus to cause the operation specified by the instruction to be implemented).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the selection of the datapath as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change for at least the same reasons as claim 1 above as well as because it would reduce the size of the processor as there would not need to be a separate set of components for each data path.
Dhong in view of Lutz fails to teach the configuration file further specifies the configuration of the configurable interconnect fabric and the logic blocks of the FPGA to and the logic blocks and the configurable interconnect fabric.
However, Arrow does teach the configuration file further specifies the configuration of the configurable interconnect fabric and the logic blocks of the FPGA to (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
the logic blocks and the configurable interconnect fabric (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this combination because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
With regards to claim 11, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 10 above. Dhong further teaches and wherein [the configuration file further configures] the mantissa portion of the reciprocal- square-root function data path to perform a linear interpolation of a reciprocal-square-root over a domain of the M-bit mantissa component of the input floating-point value (Dhong [0027]: the processor executes a second instruction on the previously obtained base value and slope, in which the processor uses the base value and slope to perform linear interpolation to obtain an estimate of the desired function evaluated at the value of the original operand).
Dhong fails to teach wherein the configuration file further configures the exponent portion of the reciprocal-square-root function data path to negate and divide the exponent component of the input floating-point value by two.
However, Lutz does teach wherein [the configuration file further configures] the exponent portion of the reciprocal-square-root function data path to negate and divide the exponent component of the input floating-point value by two; (Lutz [0059]: producing the exponent of the estimate of the result value by halving and negating the exponent).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the exponent and mantissa computation stages as taught by Dhong with negating the exponent and dividing by 2 as taught by Lutz. One of ordinary skill in the art would have been motivated to make this combination because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
Dhong in view of Lutz fails to teach that the configuration file further configures.
However, Arrow does teach the configuration file further configures (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this combination because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
With regards to claim 12, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 11 above. Dhong further teaches wherein [the configuration file further configures] the exponent portion of the reciprocal-square-root function data path to: determine a parity of the exponent component of the input floating-point value; (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd).
Dhong fails to teach compute an exponent sum value based on the parity of the exponent component and and divide the exponent sum value by two to compute the output exponent component of the output floating-point value.
However, Lutz does teach compute an exponent sum value based on the parity of the exponent component; (Lutz [0027]: the processing logic is operable to select as the modified input value the result of either an effective one bit or an effective two bit right shift of the significand of the input value, along with associated incrementing of the exponent of the input value, such that the modified input value has an exponent which is an even number)
and divide the exponent sum value by two to compute the output exponent component of the output floating-point value (Lutz [0059]: producing the exponent of the estimate of the result value by halving and negating the exponent).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the compute an exponent sum value based on the parity of the exponent component as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change for at least the same reasons as claim 9 above as well as because it would reduce the size of the processor as there would not need to be a separate set of components for each data path.
Dhong in view of Lutz fails to teach that the configuration file further configures.
However, Arrow does teach the configuration file further configures (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this combination because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
With regards to claim 13, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 12 above. Dhong further teaches wherein [the configuration file further configures] the linear interpolation lookup table to further comprise a reciprocal-square-root lookup table, (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd)
and wherein [the configuration file further configures] the mantissa portion of the reciprocal- square-root function data path to: lookup the slope value and the offset value from the reciprocal-square-root lookup table, based on the L most significant bits and the parity of the exponent component of the input floating-point value (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd).
Dhong fails to teach that the configuration file further configures.
However, Arrow does teach the configuration file further configures (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this combination because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
With regards to claim 15, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 10 above. Dhong further teaches wherein [the configuration file further configures] the mantissa computation stage to comprise [the integer multiplier] and an adder, (Dhong [0008]: the interpolation step does not require a full general-purpose FPU. Instead, it can be executed with a multiplier of reduced size, an adder, and some additional logic).
Dhong does not explicitly teach the integer multiplier and the adder being shared by the mantissa portion of the reciprocal function data path and the mantissa portion of the reciprocal-square-root function data path.
However, Lutz does teach [the integer multiplier] and the adder being shared by the mantissa portion of the reciprocal function data path and the mantissa portion of the reciprocal-square-root function data path (Lutz [0040]: FIG. 7 is a diagram schematically illustrating elements provided within the data processing apparatus of FIG. 1 to implement the processes of FIG. 5 and 6; Fig. 5 and Fig. 6 showing the flow diagrams for the reciprocal and reciprocal square root function respectively).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the exponent and mantissa computation stages as taught by Dhong with negating the exponent as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
Dhong in view of Lutz fails to teach that the configuration file further configures.
However, Arrow does teach the configuration file further configures (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the shared adder and multiplier as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
Dhong in view of Lutz fails to teach the integer multiplier.
However, Shankar does teach the integer multiplier (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the integer multiplier as taught by Shankar. One of ordinary skill in the art would have been motivated to make this combination because Integer multipliers can process more data faster than floating point multipliers because they do not have to deal with exponents, speeding up calculations.
With regards to claim 17, Dhong teaches the method comprising: partitioning, by a mantissa computation stage an M-bit mantissa component of an input floating-point value into L most-significant bits (Dhong Fig. 3 and Fig. 4: Show the mantissa computation stage; Dhong Fig. 3: Shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits)
and M-L least significant bits; (Dhong Fig. 3: Shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits)
looking up, by the mantissa computation stage, a slope value and an offset value, based on the L most significant bits, from a linear interpolation lookup table comprising a reciprocal lookup table having 2L entries and storing a plurality of pre-computed slope and offset values, (Dhong [0029]: the five most significant bits of the mantissa of floating point number 300 are used as an index to look up table 304, which contains base and slope values for each of the 32 different combinations of the five most significant bits of an arbitrary mantissa)
each of the pre-computed slope values having a first bit length; (Dhong fig. 4: shows that the slopes have a number of bits)
computing, by the mantissa computation stage, an output mantissa component of an output floating-point value by multiplying, [using an integer multiplier], the slope value having the first bit length by the M-L least significant bits having a second bit length different from the first bit length to compute a product and adding, [by an integer adder] of the mantissa computation stage, the offset value to the product, (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it; Dhong [0030]: a 10-bit slope value 314; Dhong Fig. 3: shows the 32-bit floating point mantissa being split into 5 most significant bits and 18 least significant bits)
[the integer multiplier] being configured to multiply a first [integer] having the first bit length by a second [integer] having the second bit length (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it)
and to output the product [as an integer having a number of bits equal to the sum of the first bit length and the second bit length;] (Dhong Fig. 4: Shows that the 18 least significant mantissa bits are multiplied by the slope and the base is added to it)
and computing, by an exponent computation stage [implemented by the configurable interconnect fabric and the plurality of logic blocks], an output exponent component of the output floating-point value, (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300).
Dhong fails to teach the computing the output exponent component comprising negating an exponent component of the input floating-point value.
However, Lutz does teach the computing the output exponent component comprising negating an exponent component of the input floating-point value (Lutz [0024]: negating the exponent of the input value).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the exponent and mantissa computation stages as taught by Dhong with negating the exponent as taught by Lutz. One of ordinary skill in the art would have been motivated to make this combination because it is typically desired to keep the size of the data processing apparatus as small as possible, and in particular to enable efficient use of the logic provided within the data processing apparatus as taught by Lutz (Lutz [0016]).
Dhong in view of Lutz fails to teach A method for accelerating computations in a field programmable gate array (FPGA) comprising a configurable interconnect fabric connecting a plurality of logic blocks, of the FPGA implemented by the configurable interconnect fabric and the plurality of logic blocks and implemented by the configurable interconnect fabric and the plurality of logic blocks.
However, Arrow does teach A method for accelerating computations in a field programmable gate array (FPGA) (Arrow Section What is FPGA: Field Programmable Gate Array (FPGA))
comprising a configurable interconnect fabric connecting (Arrow Section FPGA Architecture: surrounded by a system of programmable interconnects, called a fabric)
a plurality of logic blocks, (Arrow Section FPGA Architecture: configurable logic blocks (CLBs)).
of the FPGA implemented by the configurable interconnect fabric and the plurality of logic blocks, (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric)
implemented by the configurable interconnect fabric and the plurality of logic blocks (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this change because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
Dhong in view of Lutz further in view of Arrow fails to teach an integer multiplier, an integer adder, and outputting the product as an integer.
However, Shankar does teach an integer multiplier (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations)
an integer adder (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations).
Outputting the product of Dhong in view of Lutz further in view of Arrow as an integer (Shankar Page 17 lines 14-18: The media processing unit 610 similarly includes a 16X16-bit integer multiplier-adder for perform operations such as lighting, transform normal lighting, computation and normalization of vertex view vectors, and specular light source operations. The media processing unit 610 supports clipping operations and 1/squareroot operations for lighting tasks, and reciprocal operations)
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow with the integer multiplier, integer adder, and outputting the product as an integer as taught by Shankar. One of ordinary skill in the art would have been motivated to make this combination because Integer multipliers can process more data faster than floating point multipliers because they do not have to deal with exponents, speeding up calculations.
Dhong in view of Lutz further in view of Arrow further in view of Shankar fails to teach the product [as an integer] having a number of bits equal to the sum of the first bit length and the second bit length.
However, Schulte does teach the product of Dhong in view of Lutz further in view of Arrow further in view of Shankar [as an integer] having a number of bits equal to the sum of the first bit length and the second bit length; (Schulte [0015]: Referring to FIG. 4, a particular embodiment of a rectangular floating point multiplier 430, corresponding to the multiplier 130 of FIG. 1 is illustrated. The rectangular floating-point multiplier is implemented in two pipeline stages as shown in FIG. 4. The first stage 402 includes of a 76-bit.times.27-bit multiplier which accepts a 76-bit feedback term in a redundant carry-save format and produces a 103-bit product in a redundant carry-save format).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar with the output length as taught by Schulte. One of ordinary skill in the art would have been motivated to make this combination because the division operations can be executed more efficiently at the multiplier 130 than with a multiplier that uses operands of equal sizes, while still achieving the desired level of precision for the quotient Q as taught by Schulte (Schulte [0017]).
Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte fails to teach wherein the input floating-point value is represented in a low-precision binary floating-point data format where M is less than 23.
However, Mangnall teaches wherein the input floating-point value is represented in a low-precision binary floating-point data format where M is less than 23 (Mangnall [0093]: in some examples, the floating point numbers may be expressed at a different precision level, e.g. in half (16 bit) precision).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte with the input format as taught by Mangnall. One of ordinary skill in the art would have been motivated to make this combination because it would increase the efficiency of system as the 16 bit numbers would require less resources to process. Also, it can be particularly efficient to cause the bit slices to be are of varying length, such that they can be handled by look up tables or estimation, depending on their significance as taught by Mangnall (Mangnall [0213]).
With regards to claim 18, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 17 above. Dhong teaches wherein [the configurable interconnect fabric and the logic blocks are further configured] to implement a reciprocal-square-root function data path (Dhong [0021]: a preferred embodiment of the present invention is directed to function estimate instructions for the reciprocal function (1/x) and reciprocal square root function)
comprising: a mantissa portion [implemented by the logic blocks and the configurable interconnect fabric] of the mantissa computation stage; (Dhong Fig. 3 and Fig. 4: Show the mantissa computation stage)
and an exponent portion [implemented by the logic blocks and the configurable interconnect fabric] of the exponent computation stage, (Dhong [0031]: Exponent value 310 is computed by performing simple operations, such as addition and subtraction of offsets and shifts, on exponent value 311 of floating-point operand 300)
wherein the linear interpolation lookup table further comprises a reciprocal-square-root lookup table, (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd)
and looking up the slope value and the offset value from the reciprocal-square-root lookup table, based on the L most significant bits and a parity of the exponent component of the input floating-point value when the function selection input value indicates a reciprocal- square-root function (Dhong [0029]: an index for a reciprocal square-root estimate function would need to include at least one exponent bit (the least significant exponent bit), since the value of the mantissa of a reciprocal square root function is dependent on whether the exponent of the function's argument is even or odd).
Dhong fails to teach and wherein the method further comprises: selecting between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value and dividing the exponent component of the input floating point value by two when the function selection input value indicates a reciprocal-square-root function.
However, Lutz does teach and wherein the method further comprises: selecting between the reciprocal function data path and the reciprocal-square-root function data path in accordance with a function selection input value; (Lutz [0042]: which decodes the instruction and then dependent on the instruction sends appropriate control signals to other elements of the data processing apparatus to cause the operation specified by the instruction to be implemented)
dividing the exponent component of the input floating point value by two when the function selection input value indicates a reciprocal-square-root function; (Lutz [0059]: producing the exponent of the estimate of the result value by halving and negating the exponent).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong with the selection of the datapath and dividing the exponent by two as taught by Lutz. One of ordinary skill in the art would have been motivated to make this change for at least the same reasons as claim 17 above as well as because it would reduce the size of the processor as there would not need to be a separate set of components for each data path.
Dhong in view of Lutz fails to teach the configurable interconnect fabric and the logic blocks are further configured and implemented by the logic blocks and the configurable interconnect fabric.
However, Arrow does teach the configurable interconnect fabric and the logic blocks are further configured (Arrow Section FPGA Design: a configuration file that contains information on how to hook up the CLBs and other modules)
implemented by the logic blocks and the configurable interconnect fabric (Arrow Section FPGA Architecture: configurable logic blocks (CLBs) surrounded by a system of programmable interconnects, called a fabric).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz with the FPGA as taught by Arrow. One of ordinary skill in the art would have been motivated to make this combination because The ability to configure the hardware of the FPGA, reconfigure it when needed and optimize it for a particular set of functions makes the FPGA an attractive option in many applications (Arrow Section FPGA Uses).
Claims 6, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall further in view of Pineiro et al. (“High-Speed Function Approximation Using a Minimax Quadratic Interpolator”) hereinafter Pineiro.
With regards to claim 6, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 5 above. Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte fails to teach wherein the reciprocal-square-root lookup table comprises entries in the domain of [1,4).
However, Pineiro does teach wherein the reciprocal-square-root lookup table comprises entries in the domain of [1,4) (Pineiro Fig. 1: Shows the reciprocal square root having an interval of [1,4)).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall with the reciprocal square root having a domain of [1,4) as taught by Pineiro. One of ordinary skill in the art would have been motivated to make this change because three steps are carried out when approximating a function: range reduction of the argument to a predetermined input interval as taught by Pineiro (Pineiro section 3.1).
With regards to claim 14, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 13 above. Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte fails to explicitly teach wherein the configuration file further configures the reciprocal-square-root lookup table to comprise entries in the domain of [1,4).
However, Pineiro does explicitly teach wherein the configuration file further configures the reciprocal-square-root lookup table to comprise entries in the domain of [1,4) (Pineiro Fig. 1: Shows the reciprocal square root having an interval of [1,4)).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall with the reciprocal square root having a domain of [1,4) as taught by Pineiro. One of ordinary skill in the art would have been motivated to make this change because three steps are carried out when approximating a function: range reduction of the argument to a predetermined input interval as taught by Pineiro (Pineiro section 3.1).
With regards to claim 19, Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall teaches all of the limitations of claim 18 above. Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte fails to explicitly teach wherein the reciprocal-square-root lookup table comprises entries in the domain of [1,4).
However, Pineiro does explicitly teach wherein the reciprocal-square-root lookup table comprises entries in the domain of [1,4) (Pineiro Fig. 1: Shows the reciprocal square root having an interval of [1,4)).
Therefore, it would have been obvious, before the effective filing date of the claimed invention, for one of ordinary skill in the art to combine the teachings of Dhong in view of Lutz further in view of Arrow further in view of Shankar further in view of Schulte further in view of Mangnall with the reciprocal square root having a domain of [1,4) as taught by Pineiro. One of ordinary skill in the art would have been motivated to make this change because three steps are carried out when approximating a function: range reduction of the argument to a predetermined input interval as taught by Pineiro (Pineiro section 3.1).
Allowable Subject Matter
Claims 8, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcoming the 35 U.S.C. 101 rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.O.G./Examiner, Art Unit 2151
/NICHOLAS KLICOS/Primary Examiner, Art Unit 2118
Prosecution Insights