DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant’s submission filed 05 January 2026 [hereinafter Response] has been entered, where:
Claims 1, 4, 5, 9-11, 13, 14, and 19 have been amended.
Claims 2, 3, and 17 have been cancelled.
New claims 21, 22, and 23 are presented for examination.
Claims 1, 4-16, and 18-23 are pending.
Claims 1, 4-16, and 18-23 are rejected.
Claim Interpretation
3. The following is a quotation of 35 U.S.C. § 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. § 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. § 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. § 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. § 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. § 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. § 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. § 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. § 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. § 112(f) because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are:
“an ion-shuttling path module” in claim 14.
“a quantum processing unit” in claim 15.
Because these claim limitations are being interpreted under 35 U.S.C. § 112(f) they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If Applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. § 112(f) Applicant may:
(1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. § 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or
(2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. § 112(f).
Claim Objections
4. The objection to claim 1 due to informalities is WITHDRAWN in view of the Applicant’s amendment to the claim.
Claim Rejections - 35 U.S.C. § 112
5. The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
6. The rejection to claims 1-8, 9-12, and 19 under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention is WITHDRAWN in view of the Applicant’s amendments to the respective claims.
Claim Rejections - 35 U.S.C. § 101
7. 35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
8. Claims 1, 4-16, and 18-23 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites a quantum data loader, which is a machine, and thus one of the statutory categories of patentable subject matter. (35 U.S.C. § 101).
However, under Step 2A Prong One, the claim recites the limitation of “[(b)] connections connecting pairs of qubits according to a tree pattern.” The plain meaning of “connections connecting pairs of qubits according to a tree pattern” encompasses the mental observations or evaluations of which, as explained in Applicant’s disclosure, is a function of the size of the n-dimensional classical data vector and the type of data loader circuit to be implemented, which is not inconsistent with the Applicant’s disclosure. (MPEP § 2111). Also, the plain meaning of a “qubit” is a fundamental unit of quantum information capable of representing not just 0 or 1, but also a superposition of both states simultaneously, which is not inconsistent with the Applicant’s disclosure. (MPEP § 2111). That is, the limitation can practically be performed in the human mind, including, for example, observations, evaluations, judgments, and opinions, and accordingly, is a mental process, (MPEP § 2106.04(a)(2) sub III), which is one of the groupings of abstract ideas. (MPEP § 2106.04(a)(2)). The claim recites more details or specifics of the abstract idea of “[(b)] connecting . . . according to a tree pattern,” including “[(a)] n qubits,” “[(b.1)] hardware of each connection allowing a quantum gate operation to be performed on a pair of qubits,” “[(b)] the connections comprising: [(b.2)] first adjacent connections connecting adjacent qubits in the first group according to the tree pattern; [(b.3)] second adjacent connections connecting adjacent qubits in the second group according to the tree pattern; and [(b.4)] a non-adjacent connection connecting a first qubit of the first group to a second qubit in the second group that is not adjacent to the first qubit of the first group,” and accordingly, are merely more specific to the abstract idea. Also, Examiner notes that in the context of a tree pattern, the plain meaning of the claim term “adjacent” refers to the relationship between trees or branches that share a common point of connection or are located next to each other. Also, in the context of tree patterns, the plain meaning of the claim term "non-adjacent" refers to nodes that are not directly connected by a path within the tree structure. Thus, claim 1 recites an abstract idea.
Under Step 2A Prong Two, the claim as a whole is not integrated into a practical application, because the additional elements recited in the claim beyond the identified judicial exception include “[(b.1)] hardware of each connection,” which is recited at a high-level of generality, and accordingly, is a generic computer component used to implement the abstract idea, (MPEP § 2106.05(f)), and does not serve to integrate the abstract idea into a practical application. Accordingly, claim 1 is directed to an abstract idea.
Finally, under Step 2B, the additional elements, taken alone or in combination, do not represent significantly more than the abstract idea itself. The additional elements include “[(b.1)] hardware of each connection,” which is recited at a high-level of generality, and accordingly, is a generic computer component used to implement the abstract idea, (MPEP § 2106.05(f)), and does not amount to significantly more than the abstract idea. Accordingly, claim 1 is subject-matter ineligible.
Claim 4 depends directly or indirectly from claim 1. The claim recites more details or specifics of the abstract idea of “[(b)] connecting . . . according to a tree pattern,” including [(b.2.1), (b.3.1)] wherein the first group of qubits and the second group of qubits each include eight or fewer qubits”), and accordingly, are merely more specific to the abstract idea. Under Step 2A Prong Two, the abstract idea of the claim is not integrated into a practical application, (see MPEP § 2106.04(d)), nor under Step 2B does it amount to significantly more than the abstract idea, (MPEP § 2106.05 sub I; see also MPEP § 2106.05(a) – (h)), because the claims recites no more than the abstract idea. Accordingly, claims 3 and 4 are subject-matter ineligible.
Claims 5-8 depend directly or indirectly from claim 1. The claim recites more details or specifics of the abstract idea of “[(b)] connecting . . . according to a tree pattern,” including (claim 5: “[(a.1)] wherein the n is a power of two and greater than 16,” claim 6: “[(a.1)] wherein the n qubits are arranged in a two-dimensional plane,” claim 7: “[(a.2)] wherein the n qubits are arranged in a grid pattern,” claim 8: “[(a.3)] wherein the n qubits are arranged so that a number of non-adjacent connections is minimized”), and accordingly, are merely more specific to the abstract idea.
Also, under Step 2A Prong One, claim 8 recites the limitation “[(a.3)] wherein the n qubits are arranged so that a number of non-adjacent connections is minimized.” The activity of “minimized” can practically be performed in the human mind, including, for example, observations, evaluations, judgments, and opinions, and accordingly, is a mental process, (MPEP § 2106.04(a)(2) sub III), which is one of the groupings of abstract ideas. (MPEP § 2106.04(a)(2)).
Under Step 2A Prong Two, the abstract idea of the claim is not integrated into a practical application, (see MPEP § 2106.04(d)), nor under Step 2B does it amount to significantly more than the abstract idea, (MPEP § 2106.05 sub I; see also MPEP § 2106.05(a) – (h)), because the claims recite no more than the abstract idea. Accordingly, claims 5-8 are subject-matter ineligible.
Claim 9 depends from claim 1. The claim recites more details or specifics of the abstract idea of “[(b)] connecting . . . according to a tree pattern,” including “[(b.4.1)] wherein the non-adjacent connection comprises one or more ancilla qubits,” and accordingly, is merely more specific to the abstract idea. Under Step 2A Prong Two, the abstract idea of the claim is not integrated into a practical application, (see MPEP § 2106.04(d)), nor under Step 2B does it amount to significantly more than the abstract idea, (MPEP § 2106.05 sub I; see also MPEP § 2106.05(a) – (h)), because the claims recite no more than the abstract idea. Accordingly, claim 9 is subject-matter ineligible.
Claims 10-12 depend directly or indirectly from claim 1. The claims recite more details or specifics to the abstract idea of “[(b)] connecting . . . according to a tree pattern,” including (claim 10: “[(b.4.1)] wherein the non-adjacent connection comprises a bus that connects the first qubit to the second qubit,” claim 11: [(b.4.2)] wherein a second non-adjacent connection comprises a second bus that connects a third qubit of a third group of qubits to the first qubit or the second qubit,” claim 12: “[(a.1)] wherein the n qubits are located on a first layer and the bus is located on a different second layer”), and accordingly, are merely more specific to the abstract idea. Also, the plain meaning of “bus” is synonymous to a “connection” serving as a data transmission path, which is not inconsistent with the Applicant’s disclosure. (MPEP § 2111).
Under Step 2A Prong Two, the abstract idea of the claim is not integrated into a practical application, (see MPEP § 2106.04(d)), nor under Step 2B does it amount to significantly more than the abstract idea, (MPEP § 2106.05 sub I; see also MPEP § 2106.05(a) – (h)), because the claims recite no more than the abstract idea. Accordingly, claims 10-12 are subject-matter ineligible.
Claim 13 depends directly or indirectly from claim 1. Under Step 2A Prong Two, the claim as a whole is not integrated into a practical application, because the additional elements recited in the claim beyond the identified judicial exception include “[(b.4.1)] the non-adjacent connection comprises a metal wire that connects a first semiconductor quantum dot spin qubit to a second semiconductor quantum dot spin qubit.” The limitation is generally linking the use of abstract idea of “[(b)] connecting . . . according to a tree pattern,” to a particular technological environment or field of use (that is, a quantum computing environment), (MPEP § 2106.05(h)), that under Step 2A Prong Two does not integrate the abstract idea into a practical application, nor under Step 2B amounts to significantly more than the abstract idea. Therefore, claim 13 is directed to the abstract idea.
Claim 14 depends directly or indirectly from claim 1. The claim as a whole is not integrated into a practical application, because the additional elements recited in the claim beyond the identified judicial exception include “[(b.4.1)] the non-adjacent connection comprises an ion-shuttling path module that connects a first trapped-ion qubit to a second trapped-ion qubit, [(b.4.1.1)] wherein the ion-shuttling path module is configured to physically move the first trapped-ion qubit along a shuttling path to be adjacent to the second trapped-ion qubit.” The limitation is generally linking the use of abstract idea of “[(b)] connecting . . . according to a tree pattern,” to a particular technological environment or field of use (that is, a quantum computing environment), (MPEP § 2106.05(h)), that under Step 2A Prong Two does not integrate the abstract idea into a practical application, nor under Step 2B amounts to significantly more than the abstract idea. Therefore, claim 14 is directed to the abstract idea.
Claims 15 and 16 depend directly or indirectly from claim 1. The claims as a whole is not integrated into a practical application, because the additional elements recited in the claim beyond the identified judicial exception include (claim 15: “[(a.1)] the n qubits are superconducting-circuit qubits, and the quantum data loader is coupled to [(c)] a quantum processing unit comprising a set of qubits different than the n qubits in the quantum data loader,” claim 16: [(c.1)] the set of qubits of the quantum processing unit are not superconducting-circuit qubits”). The limitations are generally linking the use of abstract idea of “[(b)] connecting . . . according to a tree pattern,” to a particular technological environment or field of use (that is, a quantum computing environment), (MPEP § 2106.05(h)), that under Step 2A Prong Two does not integrate the abstract idea into a practical application, nor under Step 2B amounts to significantly more than the abstract idea. Therefore, claims 15 and 16 are directed to the abstract idea.
Claims 18 and 19 depend directly or indirectly from claim 1. The claims as a whole is not integrated into a practical application, because the additional elements recited in the claim beyond the identified judicial exception include (claim 18: “[(a.1)] the n qubits are semiconductor-spin qubits, and the quantum data loader is coupled to [(c)] a quantum processing unit comprising a set of qubits different than the n qubits in the quantum data loader,” claim 19: [(c.1)] the n qubits are not superconducting-circuit qubits and [(c.2)] the set of qubits of the quantum processing unit are superconducting-circuit qubits, trapped-ion qubits, or neutral-atom qubits”). The limitations are generally linking the use of abstract idea of “[(b)] connecting . . . according to a tree pattern,” to a particular technological environment or field of use (that is, a quantum computing environment), (MPEP § 2106.05(h)), that under Step 2A Prong Two does not integrate the abstract idea into a practical application, nor under Step 2B amounts to significantly more than the abstract idea. Therefore, claims 18 and 19 are directed to the abstract idea.
Claim 20 depends from claim 1. The claim recites more details or specifics of the abstract idea of “[(b)] connecting . . . according to a tree pattern,” including “[(b.5)] the connections include n−1 connections,” and accordingly, is merely more specific to the abstract idea. Under Step 2A Prong Two, the abstract idea of the claim is not integrated into a practical application, (see MPEP § 2106.04(d)), nor under Step 2B does it amount to significantly more than the abstract idea, (MPEP § 2106.05 sub I; see also MPEP § 2106.05(a) – (h)), because the claims recite no more than the abstract idea. Accordingly, claim 20 is subject-matter ineligible.
Claims 21-23 depend from claim 1. The claims recite more details or specifics to the abstract idea of “[(b)] connections connecting . . . according to a tree pattern,” where (claim 21: “[(b.2.1)] no qubit in the first group is connected to another qubit in the first group by a non-adjacent connection, and [(b.3.1)] no qubit in the second group is connected to another qubit in the second group by a non-adjacent connection”; claim 22: [(b.2.1), (b.3.1)] no qubit in the first group is connected to one of the qubits in the second group by an adjacent connection”; and claim 23: “no qubit in the first group is adjacent to one of the qubits in the second group”), and accordingly, are merely more specific to the abstract idea. Under Step 2A Prong Two, the abstract idea of the claim is not integrated into a practical application, (see MPEP § 2106.04(d)), nor under Step 2B does it amount to significantly more than the abstract idea, (MPEP § 2106.05 sub I; see also MPEP § 2106.05(a) – (h)), because the claims recite no more than the abstract idea. Accordingly, claims 21-23 are subject-matter ineligible.
Claim Rejections – 35 U.S.C. § 103
9. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
12. Claims 1 and 4-8 are rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese] and US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510].
Regarding claim 1, Cortese teaches [a] quantum data loader (Cortese, Abstract, teaches “Quantum circuits and methods load N=2n classical bits into an entangled quantum output state using a gate depth of order O(n) [(that is, a quantum data loader configured to encode an n-dimensional vector representing classical data into a quantum state)]”), the quantum data loader comprising:
n qubits (Cortese ¶ 0007 & Fig. 2 teaches parallel loading of N bits of classical data into a quantum computer [Examiner annotations in dashed-line text boxes]:
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Cortese ¶ 0009 teaches a “N qubit quantum state ›produced by the input circuit of FIG. 2 is represented mathematically as the tensor product of the quantum states of the N individual qubits [(that is, n qubits)], to form a quantum ‘word’ of size N”) comprising a first group of qubits and a second group of qubits different than the first group (Cortese, Fig. 6, teaches recursive assembly of two [(that is, groups of the n qubits)], two-qubit “words” [(that is, “qubits b00 and b01” are a first group of qubits, and “qubits b10 and b11“ are a second group of qubits different from the first group)] [Examiner annotations in dashed-line text boxes]:
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Cortese ¶ 0057 teaches “schematically shows conceptual recursive assembly of a quantum state ᴪ from N=4 qubits (i.e. n=2) [(that is, groups of the n qubits)] representing classical bits b00, b01, b10, and b11 using a recursion of depth two according to an embodiment); and
connections connecting pairs of qubits of the n qubits according to a tree pattern (Cortese, Fig. 13, teaches a circuit 30’ having a data loading tree [Examiner annotations in dashed-line text boxes]:
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Cortese ¶ 0089 teaches “‘[t]he circuit 30’″ shown in FIG. 13 applies the desired disentangling operation for the second level of the data loading assembly tree [(that is, connections connecting pairs of qubits of the n qubits according to a tree pattern)]”), . . . , the connections comprising:
first adjacent connections connecting adjacent qubits in the first group according to the tree pattern; second adjacent connections connecting adjacent qubits in the second group according to the tree pattern (referring to above, Cortese, Fig. 6, teaches recursive assembly of two [(that is, groups of the n qubits)], two-qubit “words” [(that is, “qubits b00 and b01” are first adjacent connections connecting adjacent qubits in the first group according to the tree pattern, and “qubits b10 and b11“ are second adjacent connections connecting adjacent qubits in the second group according to the tree pattern)]; Cortese ¶ 0057 teaches “schematically shows conceptual recursive assembly of a quantum state ᴪ from N=4 qubits (i.e. n=2) [(that is, groups of the n qubits)] representing classical bits b00, b01, b10, and b11 using a recursion of depth two according to an embodiment); and
a non-adjacent connection connecting a first qubit of the first group to a second qubit in the second group that is not adjacent to the first qubit of the first group (referring to above, Cortese, Fig. 6, teaches recursive assembly of two [(that is, groups of the n qubits)], two-qubit “words” [(that is, “qubits b00 and b11” are a non-adjacent connections connecting a first qubit of the first group to a second qubit in the second group that is not adjacent to the first qubit of the first group)]”).
Though Cortese teaches connections connecting qubits in a data loading assembly tree, Cortese, however, does not explicitly teach –
* * *
[connections connecting] . . . , hardware of each connection allowing a quantum gate operation to be performed on a pair of qubits, . . . :
* * *
But Hilton ‘510 teaches –
* * *
[connections connecting] . . . , hardware of each connection allowing a quantum gate operation to be performed on a pair of qubits (Hilton ‘510 ¶ 0024 teaches “controllably communicatively coupling a first inter-cell coupling qubit of the first cell to a second inter-cell coupling qubit of another cell via one or more inter-cell couplers. Direct coupling by the inter-cell couplers defines an adjacency relationship between the cells of the first and second inter-cell coupling qubits. The method further comprises controllably communicatively coupling a first qubit of the first cell and a second qubit of a second cell via a long-range coupler [(that is, “intra-cell coupler,” “inter-cell coupler” and “long range coupler” are hardware of each connection allowing a quantum gate operation to be performed on a pair of qubits)]”; also, Hilton ‘510 ¶ 0042 teaches “[e]lements of a quantum processor may be programmable, including (for example) the qubits, couplers, and/or other devices. A quantum processor may be in communication with one or more classical computers, which may program elements of the quantum processors. For example, qubits, couplers, and/or other devices may be superconducting and may have tunable inductance [(that is, hardware of each connection)], which may be controlled by one or more classical computers to model a problem [(that is, a quantum gate operation)]”), . . . :
* * *
Cortese and Hilton ‘510 are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify Cortese pertaining to quantum machine loading with the adjacent and non-adjacent qubit gates of Hilton ‘510.
The motivation to do so is because of a “general desire for an analog processor topology which permits coupling between arbitrary pairs of qubits with reduced computational overhead in at least some circumstances.” (Hilton ‘510 ¶ 0005).
Examiner notes that the Applicant’s preamble does not afford patentable weight to the Applicant’s claims because the claim preamble is not “necessary to give life, meaning, and vitality” to the claim. Moreover, because the Applicant’s preamble merely states the purpose or intended use of the invention rather than any distinct definition of any of the claimed invention’s limitations, the preamble is not considered a limitation and is of no significance to claim construction.
Regarding claim 4, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Cortese teaches -
wherein the first group of qubits and the second group of qubits each include eight or fewer qubits (Cortese, Fig. 6, teaches recursive assembly of two, two-qubit “words” [Examiner annotations in dashed-line text boxes]:
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[(that is, “group b00 & b01 qubits” and “group b10 & b11 qubits” are wherein groups include eight or fewer qubits )]”).
Regarding claim 5, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Cortese teaches -
wherein the n is a power of two (Cortese ¶ 0070 teaches “the gate depth, i.e. the maximum number of gates through which a quantum state must pass from input to output, has order O(n2). One may likewise show that the number of physical gates has order O(n2) [(that is, “order O(n2)” is wherein n is a power of two)]”) . . . .
Hilton ‘510 teaches -
[wherein n is . . . ] greater than 16 (Hilton ‘510 ¶ 0102 teaches “[c]ell 500a may comprise any suitable number of qubits 532, 534 and couplers 536, 538, 540, 546, 548. As depicted, cell 500a comprises 12 qubits 532, 534, arranged in a grid with six row-wise qubits 532 and six column-wise qubits 534”; see below Hilton ‘510, Fig. 2C, which shows six cells of eight qubits each for 48 qubits [(that is, n is . . . greater than 16)]).
Regarding claim 6, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Hilton ‘510 teaches -
wherein the n qubits are arranged in a two-dimensional plane (Hilton ‘510, Fig. 1A, teaches
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Hilton ‘510 ¶ 0043 teaches “FIG. 1A shows an example quantum processor topology 200 [(that is, as shown, “topology 200” is wherein the n qubits are arranged in a two-dimensional plane)]”).
Regarding claim 7, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 6, as described above in detail.
Hilton ‘510 teaches -
wherein the n qubits are arranged in a grid pattern (Hilton ‘510, Fig. 1B, teaches arrangement of qubits in a grid patter [Examiner annotations in dashed-line text boxes]:
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Hilton ‘510 ¶ 0050 teaches “Qubits 232, 234 may be said to be arranged in a “grid”, with qubits 232 forming columns and qubits 234 forming rows. In some implementations, qubits 232, 234 are arranged non-orthogonally—for instance, qubits 232, 234 may be arranged at 60 or 120 degree angles to each other (and/or at some other angle) [(that is, wherein the n qubits are arranged in a grid pattern)]”).
Regarding claim 8, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 7, as described above in detail.
Hilton ‘510 teaches -
wherein the n qubits are arranged so that a number of non-adjacent connections is minimized (Hilton ‘510, Fig. 2C, teaches a topology 300 that reduces the overhead of coupling at least some qubits [Examiner annotations in dashed-line text boxes]:
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Hilton ‘510 ¶ 0058 teaches “Long-range couplers 314 are ‘long-range’ in the sense that they couple qubits 232, 234 which are not adjacent; Hilton ‘510 ¶ 0071 teaches “In total, five qubits 232, 234 and four couplers 240, 270, 336 are used, corresponding to an overhead of three qubits 232, 234 and three couplers 240, 270, 336. This represents a reduction in overhead relative to the example coupling between qubits 232 a and 232 f enabled by topology 200 [of Fig. 1C] (which required an overhead of at least four qubits 232, 234 and four couplers 240, 270) [(that is, the effect of long-range couplers 335 is to reduce non-adjacent coupler 270, which effect is that the n qubits are arranged so that a number of non-adjacent connections is minimized)]”).
Regarding claim 21, the combination of Cortese and Hilton ‘510 teach all of the limitations of claim 1, as described above in detail.
Hilton ‘510 teaches -
no qubit in the first group is connected to another qubit in the first group by a non-adjacent connection, and no qubit in the second group is connected to another qubit in the second group by a non-adjacent connection (Hilton ‘510, Fig. 1B, teaches a group of qubits in the form of a cell 220 [Examiner annotations in dashed-line text boxes]:
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Hilton ‘510, Abstract, teaches “[q]ubits in the topology are grouped into cells [(that is, “cells” are at least the first group or the second group)]; Hilton ‘510 ¶ 0048 teaches “[e]ach intra-cell coupler 240 is operable to couple together qubits 232, 234 of cell 220 [(that is, an “intra-cell coupler” is not a non-adjacent connection, and thus connected to another qubit in the first group by a non-adjacent connection, and no qubit in the second group is connected to another qubit in the second group by a non-adjacent connection)]”).
Regarding claim 22, the combination of Cortese and Hilton ‘510 teach all of the limitations of claim 1, as described above in detail.
no qubit in the first group is connected to one of the qubits in the second group by an adjacent connection (Hilton ‘510, Abstract, teaches “[q]ubits in the topology are grouped into cells [(that is, “cells” are at least the first group or the second group)]; Hilton ‘510 ¶ 0048 teaches “[e]ach intra-cell coupler 240 is operable to couple together qubits 232, 234 of cell 220 [(that is, an “intra-cell coupler” is not either of a “long range coupler” or an “inter-cell coupler,” and thus, no qubit in the first group is connected to one of the qubits in the second group by an adjacent connection)]”).
Regarding claim 23, the combination of Cortese and Hilton ‘510 teach all of the limitations of claim 1, as described above in detail.
Hilton ‘510 teaches -
no qubit in the first group is adjacent to one of the qubits in the second group (Hilton ‘510, Abstract, teaches “[q]ubits in the topology are grouped into cells [(that is, “cells” are at least the first group and the second group)]”; Hilton ‘510 & Fig. 1C teaches “[t]he qubits of a cell 210 may be coupled to each other by intra-cell couplers (not shown in FIG. 1A), thereby forming a subtopology of topology 200 [(that is, as indicated by an “intra-cell coupler” for a cell of qubits, no qubit in the first group is adjacent to one of the qubits in the second group)]”).
13. Claim 9 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese] and US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], and US Published Application 20200401478 to Reilly et al. [hereinafter Reilly].
Regarding claim 9, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Though Cortese and Hilton ‘510 teach the feature of ancilla qubits and long-range couplers; however, the combination of Cortese and Hilton ‘510 does not explicitly teach –
wherein the non-adjacent connection comprises one or more ancilla qubits.
But Reilly teaches -
wherein the non-adjacent connection comprises one or more ancilla qubits (Reilly ¶ 0015 teaches a “quantum computing device and a method for performing quantum computing, that achieves the all-to-all connectivity between qubits necessary for performing lattice surgery with a smaller number of logical ancilla qubits [(that is, “all-to-all connectivity” is a . . . connection comprises one or more ancilla qubits)], thereby reducing the spatial overhead in qubits”; Reilly ¶ 0025 teaches “transversal CNOT operations [(that is, a connection )] are performed between the qubits of pairs of adjacent qubits where one member of each pair belongs to the first or second square patch and the other to the set of N qubits [(that is, “one [pair] member” and “the other [pair member]” is a non-adjacent connection comprises one or more ancilla qubits)]”).
Cortese, Hilton ‘510, and Reilly are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Reilly teaches all-to-all connectivity between qubits necessary for performing lattice surgery with a smaller number of logical ancilla qubits, thereby reducing the spatial overhead in qubits.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese and Hilton ‘510 pertaining to quantum machine loading having adjacent and non-adjacent qubit gates with the all-to-all connectivity of the ancilla qubits of Reilly.
The motivation to do so is to “achieve the object of reducing the space overhead for the ancillas needed to provide all-to-all connectivity between qubits by introducing a small data-bus between the planar code patches encoding a logical qubit.” (Reilly ¶ 0029).
14. Claims 10-12 are rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese] and US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], and US Patent 7613765 to Hilton et al. [hereinafter Hilton ‘765].
Regarding claim 10, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Though Cortese and Hilton ‘510 teach the features of a long-range coupler for lower-overhead coupling between qubits in non-adjacent cells, the combination of Cortese and Hilton ‘510, however, does not explicitly teach –
wherein the non-adjacent connection comprises a bus that connects the first qubit to the second qubit.
But Hilton ‘765 teaches -
wherein the non-adjacent connection comprises a bus that connects the first qubit to the second qubit (Hilton ‘765 teaches a bus system coupling non-adjacent qubits together [Examiner annotations in dashed-line text boxes]:
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Hilton ‘765 6:62-66 teaches “[i]n [bus] system 700, bus 990 is capacitively coupled to respective qubits 610 by respective capacitors 611-E.).
Cortese, Hilton ‘510, and Hilton ‘765 are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Hilton ‘765 teaches a superconducting bus and a controllable coupling mechanism that controllably couples the superconducting bus to the qubit.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese and Hilton ‘510 pertaining to quantum machine loading having adjacent and non-adjacent qubit gates with the bus system of Hilton ‘765.
The motivation to do so is because “he qubits are free to have the same energy-level spacing, as the coupling is controlled not by tuning the energy level spacing in the qubits or in a resonator but by tuning controllable coupling elements. This provides the additional benefit of reducing the complexity, and therefore cost, of the inventive quantum architectures relative to known quantum systems.” (Hilton ‘765 10:8-14).
Regarding claim 11, the combination of Cortese, Hilton ‘510, and Hilton ‘765 teaches all of the limitations of claim 10, as described above in detail.
Hilton ‘765 teaches -
wherein a second non-adjacent connection comprises a second bus that connects a third qubit of a third group of qubits to the first qubit or the second qubit (Hilton ‘765, Fig. 5A, teaches a second bus providing a second non-adjacent connection [Examiner annotations in dashed-line text boxes]:
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Hilton ‘765 24:16-20 teaches “a portion 500 of a two-dimensional bus architecture comprising N rows by M rows that includes a pivot segment 460-K. Each row, 350-1 through 350-N, comprises a plurality of bus segments 350 and each bus segment 350 is connected to a plurality of qubits 110 [(that is, “bus segments 350-N,K & 350-N,M” are a second non-adjacent connection comprises a second bus that connects a third qubit to the first qubit or the second qubit)]”).
Regarding claim 12, the combination of Cortese, Hilton ‘510, and Hilton ‘765 teaches all of the limitations of claim 10, as described above in detail.
Hilton ‘765 teaches -
wherein the n qubits are located on a first layer and the bus is located on a different second layer (Hilton ‘765 24:25-27 and Fig. 5A teaches the use of “vias,” where a “two-dimensional bus architecture of FIG. 5A can be extended into a third dimension in which there are successive layers of architecture 500, each layer controllably connected to the other by vias extending from, for example, positions 502 of architecture 500 [(that is, “successive layers” wherein the n qubits are located on a first layer and the bus is located on a different second layer)]”).
15. Claim 13 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese] and US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], US Patent 7613765 to Hilton et al. [hereinafter Hilton ‘765], and US Published Application 20200052101 to Petta et al. [hereinafter Petta].
Regarding claim 13, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Though Cortese and Hilton ‘510 teach a non-adjacent connection, the combination of Cortese and Hilton ‘510, however, does not explicitly teach –
wherein the non-adjacent connection comprises a metal wire that connects a first semiconductor quantum dot spin qubit to a second semiconductor quantum dot spin qubit.
But Hilton ‘765 teaches -
wherein the non-adjacent connection comprises a metal wire (Hilton ‘765 27:14-18 teaches, “[r]eferring to FIGS. 9A and 9C, in some embodiments control wires (buses) [(that is, a metal wire)] are routed on layers above the circuit, and are connected to nodes 905 through vias, which pass vertically through the layers in the fabricated structure [(that is the “layers” are a non-adjacent connection comprises a metal wire)]”) . . . .
Cortese, Hilton ‘510, and Hilton ‘765 are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Hilton ‘765 teaches a superconducting bus and a controllable coupling mechanism that controllably couples the superconducting bus to the qubit.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese and Hilton ‘510 pertaining to quantum machine loading having adjacent and non-adjacent qubit gates with the bus system including a metal wire of Hilton ‘765.
The motivation to do so is because “he qubits are free to have the same energy-level spacing, as the coupling is controlled not by tuning the energy level spacing in the qubits or in a resonator but by tuning controllable coupling elements. This provides the additional benefit of reducing the complexity, and therefore cost, of the inventive quantum architectures relative to known quantum systems.” (Hilton ‘765 10:8-14).
Though Cortese, Hilton ‘510, and Hilton ‘765 teach the feature of a system bus connection for adjacent and non-adjacent qubits, the combination of Cortese, Hilton ‘510, and Hilton ‘765, however, does not explicitly teach –
[wherein a non-adjacent connection comprises a metal wire] that connects a first semiconductor quantum dot spin qubit to a second semiconductor quantum dot spin qubit.
But Petta teaches -
[wherein the non-adjacent connection comprises a metal wire] that connects a first semiconductor quantum dot spin qubit to a second semiconductor quantum dot spin qubit (Petta ¶ 0161 teaches “[t]he interaction of qubits via microwave frequency photons enables long-distance qubit-qubit coupling [(that is, “long-distance” being non-adjacent, and “qubit-qubit” is a first . . . qubit to a second . . . qubit)] and facilitates the realization of a large-scale quantum processor. However, qubits based on electron spins in semiconductor quantum dots have proven challenging to couple to microwave photons [(that is, semiconductor quantum dot spin qubit)]. In this section is shown that a sizable coupling for a single electron spin is possible via spin-charge hybridization using a magnetic field gradient in a silicon double quantum dot.”).
Cortese, Hilton ‘510, Hilton ‘765, and Petta are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Hilton ‘765 teaches a superconducting bus and a controllable coupling mechanism that controllably couples the superconducting bus to the qubit. Petta teaches storing and transferring quantum information.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese, Hilton ‘510, and Hilton ‘765 pertaining to quantum machine loading having adjacent and non-adjacent qubit gates having a bus system including a metal wire with the semiconductor quantum dot spin qubits of Petta.
The motivation to do so is because “qubits based on electron spins in semiconductor quantum dots have proven challenging to couple to microwave photons. In this section is shown that a sizable coupling for a single electron spin is possible via spin-charge hybridization using a magnetic field gradient in a silicon double quantum dot. Based on parameters already shown in recent experiments, optimal working points are predicted to achieve a coherent spin-photon coupling, an essential ingredient for the generation of long-range entanglement.” (Petta ¶ 0161).
16. Claim 14 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese], US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], and Webber et al., “Efficient Qubit Routing for a Globally Connected Trapped Ion Quantum Computer,” arXiv (Feb 2020) [hereinafter Webber].
Regarding claim 14, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Though Cortese and Hilton ‘510 teaches connections allowing a quantum gate operations to be performed on a pair of qubits, the combination of Cortese and Hilton ‘510 does not explicitly teach –
wherein the non-adjacent connection comprises an ion-shuttling path module that connects a first trapped-ion qubit to a second trapped-ion qubit,
wherein the ion-shuttling path module is configured to physically move the first trapped-ion qubit along a shuttling path to be adjacent to the second trapped-ion qubit.
But Webber teaches -
wherein the non-adjacent connection comprises an ion-shuttling path module (Webber, Figs. 1A – 1C teach an ion-shuttling path [Examiner annotations in dashed-line text boxes]:
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Webber, left column of p. 3, “2. Problem Specification and Routing Algorithm,” first paragraph, teaches “ions (qubits) are restricted to a square grid, (see Figure 1B), which consists of an array of repeated X-Junctions (see Figure 1A), each containing a single gate zone. Ions must first be shuttled (physically moved) [(that is, a non-adjacent connection comprises an ion-shuttling path module)]”) that connects a first trapped-ion qubit to a second trapped-ion qubit (Webber, left column of p. 3, “2. Problem Specification and Routing Algorithm,” first paragraph, teaches “gate zones enable both single and two qubit gates [(that is, connects a first trapped-ion qubit to a second trapped-ion qubit)]. To perform a quantum algorithm on this device it must first be decomposed into the native gate set, which can be optimized”),
wherein the ion-shuttling path module is configured to physically move the first trapped-ion qubit along a shuttling path to be adjacent to the second trapped-ion qubit (Webber, right column of p. 1, “1. Introduction,” first full paragraph, teaches “one architecture which offers a scalable approach to trapped ion quantum computing, involves a large connected ion trap array across which individual ions are physically shuttled [(that is, the shuttling path module is configured to physically move the first trapped-ion qubit along a shuttling path to be adjacent to the second trapped-ion qubit)]. The architecture provides a solution to scale to very large qubit numbers [(that is, such “very large qubit numbers” include a non-adjacent connection)], which will be a requirement to run many important algorithms”).
Cortese, Hilton ‘510, and Webber are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Webber teaches qubit routing algorithm which enables efficient global connectivity in a particular trapped ion quantum computing architecture.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese and Hilton ‘510 pertaining to quantum machine loading for adjacent and non-adjacent qubit gates with the ion shuttling paths of Webber.
The motivation to do so is because, “for the shuttling parameters used, the trapped ion design has a substantially lower cost associated with connectivity.” (Webber, Abstract).
17. Claim 15 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese], US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], and US Published Application 20160267032 to Rigetti et al. [hereinafter Rigetti].
Regarding claim 15, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Hilton ‘510 teaches -
wherein the n qubits are superconducting-circuit qubits, and the quantum data loader is coupled to a quantum processing unit (Hilton ‘510 ¶ 0042 teaches “[e]lements of a quantum processor [(that is, a quantum processing unit)] may be programmable, including (for example) the qubits, couplers, and/or other devices. A quantum processor may be in communication with one or more classical computers [(that is, a “classical computer” functions as, and is covered by, the quantum data loader, which is coupled to a quantum processing unit)], which may program elements of the quantum processors. For example, qubits, couplers, and/or other devices may be superconducting [(that is, the n qubits are superconducting-circuit qubits)] and may have tunable inductance, which may be controlled by one or more classical computers [(that is, quantum data loader)] to model a problem”) . . . .
Though Cortese and Hilton ‘510 teach the features of a quantum data loader coupled to a quantum processor, the combination of Cortese and Hilton ‘510 does not explicitly teach –
[wherein . . . a quantum processing unit] comprising a set of qubits different than the n qubits in the quantum data loader.
But Rigetti teaches -
[wherein . . . a quantum processing unit] comprising a set of qubits different than the n qubits in the quantum data loader (Rigetti ¶ 0377 teaches “the transition frequencies of the qubit devices [(that is, the quantum data loader)] and the quantum processor cell are staged in frequency. For instance, the qubit frequencies can be chosen such that each qubit in the quantum processor cell has a qubit operating frequency that is distinct from the operating frequencies of all nearest-neighbor qubits, and each nearest-neighbor for any given qubit has a different qubit operating frequency difference than the other nearest-neighbors for the given qubit. Thus, each qubit can have a different difference in frequency between itself and each neighboring qubit [(that is, the “qubits” with respect to one another are different)], such that no two coupler devices that have the same drive frequency are coupled to the same qubit device [(that is, a quantum processing unit comprising a set of qubits different than the n qubits in the quantum data loader)]”).
Cortese, Hilton ‘510, and Rigetti are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Rigetti teaches qubit routing algorithm which enables efficient global connectivity in a particular trapped ion quantum computing architecture.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese and Hilton ‘510 pertaining to quantum machine loading for adjacent and non-adjacent qubit gates with the different qubits of Rigetti.
The motivation to do so is because “the architecture of the quantum computing system 100 provides a practicable and economical solution for large-scale quantum computation.” (Rigetti ¶ 0040).
18. Claim 16 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese], US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], US Published Application 20160267032 to Rigetti et al. [hereinafter Rigetti], and US Published Application 20190044066 to Thomas et al. [hereinafter Thomas].
Regarding claim 16, the combination of Cortese, Hilton ‘510, and Rigetti teach all of the limitations of claim 15, as described above in detail.
Though Cortese, Hilton ‘510, and Rigetti teach a quantum processing device, the combination of Cortese, Hilton ‘510, and Rigetti, however, does not explicitly teach –
wherein the set of qubits of the quantum processing unit are not superconducting-circuit qubits.
But Thomas teaches -
wherein the set of qubits of the quantum processing unit are not superconducting-circuit qubits (Thomas ¶ 0091 teaches a “quantum processing device 2026 may include one or more of the quantum circuits or spin qubit device assemblies with VC-based spin qubits integrated on a semiconductor substrate as described herein, e.g., the quantum circuit 100 as shown in FIG. 1 or any further variations of such a circuit as described above, or/and any of the spin qubit device assemblies shown in FIG. 2, 4, or 6, or any further variations of those assemblies as described above, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits/devices described herein, and monitoring the result of those operation [(that is, the set of qubits of the quantum processing unit are not superconducting-circuit qubits)]”).
Cortese, Hilton ‘510, Rigetti, and Thomas are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Rigetti teaches qubit routing algorithm which enables efficient global connectivity in a particular trapped ion quantum computing architecture. Thomas teaches integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese, Hilton ‘510, and Rigetti pertaining to quantum machine loading for adjacent and non-adjacent qubit gates having different qubits with the non-superconducting-circuit qubits of Thomas.
The motivation to do so is because “[i]ntegration of [vacancy center (VC)] islands on semiconductor substrates typically used in semiconductor manufacturing according to any of these methods may provide a substantial improvement with respect to conventional approaches to building VC-based spin qubit devices and may promote wafer-scale integration of VC-based spin qubits for use in quantum computing devices.” (Thomas, Abstract).
19. Claim 18 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese], US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], Almudever et al., “The Engineering Challenges in Quantum Computing,” IEEE (2017) [hereinafter Almudever], and US Published Application 20160267032 to Rigetti et al. [hereinafter Rigetti].
Regarding claim 18, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Though Cortese and Hilton ‘510 teach the features of a n qubits, the combination of Cortese and Hilton ‘510, however, does not explicitly teach –
wherein the n qubits are semiconductor-spin qubits, and . . . .
But Almudever teaches -
wherein the n qubits are semiconductor-spin qubits (Almudever, right column at p. 4, “Electronic Semiconductor Qubits,” first paragraph, teaches “semiconductor host materials single electrons can be either trapped by isolated donor atoms or confined and controlled using gate-defined potentials. The spin degree of freedom in these systems is considered the most promising qubit representation due to its long coherence time [36], [37]. These devices can be measured and controlled fully electrically much like transistors in today’s digital electronics and also their fabrication exploits the same technologies as the semiconductor industry. . . . Single spin qubits can be controlled both by electrical or magnetic driving fields [(that is, wherein the n qubits are semiconductor-spin qubits)]”), and . . . .
Cortese, Hilton ‘510, and Almudever are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Almudever teaches discusses the different engineering challenges when building a quantum computer ranging from the core qubit technology, the control electronics, to the microarchitecture for the execution of quantum circuits and efficient quantum error correction.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese and Hilton ‘510 pertaining to quantum machine loading including adjacent and non-adjacent qubit gates with the semiconductor-spin qubits of Almudever.
The motivation to do so is to is because “[t]he spin degree of freedom in these systems is considered the most promising qubit representation due to its long coherence time [36], [37]. These devices can be measured and controlled fully electrically much like transistors in today’s digital electronics and also their fabrication exploits the same technologies as the semiconductor industry.” (Almudever, right column of p. 4, “Electronic Semiconductor Qubits,” first paragraph).
Though Cortese, Hilton ‘510, and Almudever teach the features of a quantum data loader coupled to a quantum processor and semiconductor qubits, the combination of Cortese and Hilton ‘510, however, does not explicitly teach –
. . . and the quantum data loader is coupled to a quantum processing unit comprising a set of qubits different than the n qubits in the quantum data loader.
But Rigetti teaches -
. . . and the quantum data loader is coupled to a quantum processing unit comprising a set of qubits different than the n qubits in the quantum data loader (Rigetti ¶ 0377 teaches “the transition frequencies of the qubit devices [(that is, the quantum data loader)] and the quantum processor cell are staged in frequency. For instance, the qubit frequencies can be chosen such that each qubit in the quantum processor cell has a qubit operating frequency that is distinct from the operating frequencies of all nearest-neighbor qubits, and each nearest-neighbor for any given qubit has a different qubit operating frequency difference than the other nearest-neighbors for the given qubit. Thus, each qubit can have a different difference in frequency between itself and each neighboring qubit [(that is, the “qubits” with respect to one another are different)], such that no two coupler devices that have the same drive frequency are coupled to the same qubit device [(that is, a quantum processing unit comprising a set of qubits different than the n qubits in the quantum data loader)]”).
Cortese, Hilton ‘510, Almudever, and Rigetti are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Almudever teaches discusses the different engineering challenges when building a quantum computer ranging from the core qubit technology, the control electronics, to the microarchitecture for the execution of quantum circuits and efficient quantum error correction. Rigetti teaches qubit routing algorithm which enables efficient global connectivity in a particular trapped ion quantum computing architecture.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese, Hilton ‘510, and Almudever pertaining to quantum machine loading for adjacent and non-adjacent qubit gates with the different qubits of Rigetti.
The motivation to do so is because “the architecture of the quantum computing system 100 provides a practicable and economical solution for large-scale quantum computation.” (Rigetti ¶ 0040).
20. Claim 19 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese], US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], Almudever et al., “The Engineering Challenges in Quantum Computing,” IEEE (2017) [hereinafter Almudever], US Published Application 20160267032 to Rigetti et al. [hereinafter Rigetti], US Published Application 20190044066 to Thomas et al. [hereinafter Thomas], and Webber et al., “Efficient Qubit Routing for a Globally Connected Trapped Ion Quantum Computer,” arXiv (Feb 2020) [hereinafter Webber].
Regarding claim 19, the combination of Cortese, Hilton ‘510, Almudever, and Rigetti teaches all of the limitations of claim 18, as described above in detail.
Though Cortese, Hilton ‘510, Almudever, and Rigetti teach a quantum processing device, the combination of Cortese, Hilton ‘510, Almudever, and Rigetti, however, does not explicitly teach –
wherein the n qubits are not superconducting-circuit qubits and
the set of qubits of the quantum processing unit are superconducting-circuit qubits, trapped-ion qubits, or neutral-atom qubits.
But Thomas teaches -
wherein the n qubits are not superconducting-circuit qubits (Thomas ¶ 0091 teaches a “quantum processing device 2026 may include one or more of the quantum circuits or spin qubit device assemblies with VC-based spin qubits integrated on a semiconductor substrate as described herein, e.g., the quantum circuit 100 as shown in FIG. 1 or any further variations of such a circuit as described above, or/and any of the spin qubit device assemblies shown in FIG. 2, 4, or 6, or any further variations of those assemblies as described above, and may perform data processing by performing operations on the qubits that may be generated in the quantum circuits/devices described herein, and monitoring the result of those operation [(that is, the set of qubits of the quantum processing unit are not superconducting-circuit qubits)]”) and . . . .
Cortese, Hilton ‘510, Almudever, Rigetti, and Thomas are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Almudever teaches discusses the different engineering challenges when building a quantum computer ranging from the core qubit technology, the control electronics, to the microarchitecture for the execution of quantum circuits and efficient quantum error correction. Rigetti teaches qubit routing algorithm which enables efficient global connectivity in a particular trapped ion quantum computing architecture. Thomas teaches integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese, Hilton ‘510, Almudever, and Rigetti pertaining to quantum machine loading for adjacent and non-adjacent qubit gates with non-superconducting quantum processor qubits of Thomas.
The motivation to do so is because “the architecture of the quantum computing system 100 provides a practicable and economical solution for large-scale quantum computation.” (Rigetti ¶ 0040).
Though Cortese, Hilton ‘510, Almudever, Rigetti, and Thomas teach a quantum processing device, the combination of Cortese, Hilton ‘510, Almudever, Rigetti, and Thomas, however, does not explicitly teach –
. . . and the set of qubits of the quantum processing unit are superconducting-circuit qubits, trapped-ion qubits, or neutral-atom qubits.
But Webber teaches -
. . . and the set of qubits of the quantum processing unit are superconducting-circuit qubits, trapped-ion qubits, or neutral-atom qubits. (Webber, right column of p. 1, “1. Introduction,” first full paragraph, teaches “one architecture which offers a scalable approach to trapped ion quantum computing, involves a large connected ion trap array across which individual ions are physically shuttled [15, 16]. The architecture provides a solution to scale to very large qubit numbers, which will be a requirement to run many important algorithms [(that is, the set of qubits of the quantum processing unit are . . . trapped-ion qubits . . . .)]”).
Cortese, Hilton ‘510, Almudever, Rigetti, Thomas, and Webber are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Almudever teaches discusses the different engineering challenges when building a quantum computer ranging from the core qubit technology, the control electronics, to the microarchitecture for the execution of quantum circuits and efficient quantum error correction. Rigetti teaches qubit routing algorithm which enables efficient global connectivity in a particular trapped ion quantum computing architecture. Thomas teaches integrating vacancy centers (VCs) on semiconductor substrates for forming VC-based spin qubit devices. Webber teaches qubit routing algorithm which enables efficient global connectivity in a particular trapped ion quantum computing architecture.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese, Hilton ‘510, Almudever, Rigetti, and Thomas pertaining to quantum machine loading for adjacent and non-adjacent qubit gates with a quantum processor based on trapped-ion qubits of Webber.
The motivation to do so is because, “for the shuttling parameters used, the trapped ion design has a substantially lower cost associated with connectivity.” (Webber, Abstract).
21. Claim 20 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20190213493 to Cortese et al. [hereinafter Cortese], US Published Application 20170220510 to Hilton et al. [hereinafter Hilton ‘510], and Vyas et al., “Rooted-tree network for optimal non-local gate implementation,” arXiv (2015) [hereinafter Vyas].
Regarding claim 20, the combination of Cortese and Hilton ‘510 teaches all of the limitations of claim 1, as described above in detail.
Though Cortese and Hilton ‘510 teach connecting pairs of qubits according to a tree pattern, the combination of Cortese and Hilton ‘510, however, does not explicitly teach –
wherein the connections include n−1 connections.
But Vyas teaches -
wherein the connections include n−1 connections (Vyas at p. 2, “2. Rooted Tree Network,” first paragraph, teaches “we take recourse to graph theory for designing a generalized network for optimizing classical communication cost, while keeping the network easy for implementation. In our proposed construct, there are (n − 1) remote control parties who want to implement control unitary gates on one target party. In the graph theory framework, each remote party is represented by a vertex. Each vertex may have two or more qubits. One or more qubits of a vertex are connected to the qubits of other vertices through edges, made up of Bell states. Since each remote agent is connected to at least one other, the graph representing the quantum network is connected. A graph is connected, if all the vertices are joined to each other by a path through edges. To ensure an optimal entanglement cost, the number of edges [(that is, an “edge” is a connection, where the connections include n-1 connections)] of the relevant graph should be (n − 1). It can be shown that a connected graph of n vertices with (n − 1) edges has to be a tree”).
Cortese and Hilton ‘510 are from the same or similar field of endeavor. Cortese teaches quantum algorithm-agnostic method for deterministically loading classical data bits into a quantum state composed of an optimal Log2(N) data qubits. Hilton ‘510 teaches techniques for improving the connectivity of analog computing systems, and particularly of quantum computing systems including those associated with gate model quantum computing. Vyas teaches a rooted-tree network is the most general entanglement distribution for implementing qubits.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant’s invention to modify the combination of Cortese and Hilton ‘510 pertaining to quantum machine loading including the adjacent and non-adjacent qubit gates with the rooted-tree network for qubit entanglement of Vyas.
The motivation to do so is because “the novelty of the rooted-tree entanglement distribution between n remote parties lies in the fact that, it opens up the freedom of designing the entanglement network according to the capacity of maintaining entangled channels of each party, as well as the suitable number of implementation steps and the available classical communication resources.” (Vyas at p. 8, “5. Discussion,” first paragraph).
Response to Arguments
22. Examiner has fully considered Applicant’s arguments, and responds below accordingly.
Claim Rejections – 35 U.S.C. § 101
23. Applicant argues that “the Office Action asserts that a qubit is a ‘fundamental unit of . . . information representing not just 0 or 1, but also a superposition of both states’ that can be ‘performed in the human mind.’ This is incorrect. A qubit is a physical entity that forms a quantum mechanical system. For example, qubits can be ‘superconducting qubits, spin qubits, trapped ions, arrays of neutral atoms, and photonic systems (e.g., photons in waveguides)’ (see paragraph 137 of the application as filed). A qubit can be in a quantum state, which is a physical state. More specifically, a qubit can be in a first quantum state, a second quantum state, or third quantum state that is a superposition of the first and second states. In the field of quantum computing, values (such as ‘0’ and ‘1’) are assigned to these physical states in order to perform calculations. However, a qubit and its quantum states are physical entities.” (Response at p. 7).
Examiner’s Response:
Examiner respectfully disagrees because under Step 2A Prong One and a broadest reasonable interpretation, the claim term “qubit” is simply an informational unit. That the term is a “physical entity” is not tethered to the claims, as submitted by Applicant.
Exemplar claim 1 recites a “quantum data loader.” The plain meaning of the term “quantum data loader” is a tool or method used in quantum computing to load classical data into quantum states, which under a reasonable broadest interpretation is converting classical computer data into a quantum state, and is not inconsistent with the Applicant’s disclosure. (MPEP § 2111; see Specification ¶ 0004 (“a quantum data loader configured to encode an n-dimensional vector representing classical data into a quantum state.”)).
With respect to the claim term “qubit,” the Office action sets out that
the plain meaning of a ‘qubit’ is a fundamental unit of quantum information capable of representing not just 0 or 1, but also a superposition of both states simultaneously, which is not inconsistent with the Applicant's disclosure. (MPEP § 2111 ). That is, the limitation can practically be performed in the human mind, including, for example, observations, evaluations, judgments, and opinions, and accordingly, is a mental process, (MPEP § 2106.04(a)(2) sub Ill), which is one of the groupings of abstract ideas. (MPEP § 2106.04(a)(2)).
(Non-Final Action filed 15 September 2025, at pp. 5-6; see also hereinabove, as set out in detail). With regard to qubits, exemplar claim 1 recites, inter alia:
* * *
[(a)] n qubits comprising a first group of qubits and a second group of qubits different than the first group: and
[(b)] connections connecting pairs of qubits of the n qubits according to a tree pattern, hardware of each connection allowing a quantum gate operation to be performed on a pair of qubits, . . . :
* * *
(claim 1, lines 4-8 (emphasis added by Examiner)).
Applicant points to the Specification in support of a “qubit is a physical entity,” (Response at p. 7), where:
[a] quantum processing device (also referred to as a quantum computer, quantum processor, or quantum processing unit) exploits the laws of quantum mechanics in order to perform computations. A quantum processing device can be a universal or a non-universal quantum processing device (a universal quantum device can execute any possible quantum circuit (subject to the constraint that the circuit doesn't use more qubits than the quantum device possesses)). Quantum processing devices commonly use so-called qubits, or quantum bits. While a classical bit always has a value of either 0 or 1, a qubit is a quantum mechanical system that can have a value of 0, 1, or a superposition of both values. Example physical implementations of qubits include superconducting qubits, spin qubits, trapped ions, arrays of neutral atoms, and photonic systems (e.g., photons in waveguides). For the purposes of this disclosure, a qubit may be realized by a single physical qubit or as an error-protected logical qubit that itself comprises multiple physical qubits. The disclosure is also not specific to qubits. The disclosure may be generalized to apply to quantum processors whose building blocks are qudits (d-level quantum systems, where d>2) or quantum continuous variables, rather than qubits.
(Specification ¶ 0137 (emphasis added by Examiner)). Examiner points out that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 20 USPQ2d 1057 (Fed. Cir. 1993).
Though it may be said that “quantum processing devices” inherently implement the “qubit’ as a fundamental unit of quantum information, the reverse is not necessarily so. A “qubit” does not inherently require deployment on a “quantum processing device,” and indeed, may be deployed in a classical computer, such as through simulations and/or classical computer tools. For example, as set out above, a “quantum data loader” of Applicant’s invention is a tool or method used in quantum computing to load classical data (binary bits) into quantum states (qubits). In the broadest reasonable interpretation, a classical computer may be used to convert classical data into quantum states, in a qubit informational format.
Accordingly, under Step 2A Prong One, the limitation of “[(b)] . . . connections connecting pairs of qubits according to a tree pattern" encompasses the mental observations or evaluations of qubits, which can practically be performed in the human mind, and accordingly, is a mental process, (MPEP § 2106.04(a)(2)), as set out above in detail.
24. “Furthermore, amended claim 1 recites spatial relationships of these (physical) qubits. In particular, amended claim 1 recites two groups of qubits, where qubits in each group include adjacent qubits (that are connected by adjacent connections). Amended claim 1 also recites two qubits not being adjacent to each other (which are connected by the non-adjacent connection).” (Response at p. 7).
Examiner’s Response:
The claims do not recite such a “spatial relationship,” and instead, merely recite more details or specifics to the abstract idea of “connections connecting pairs of qubits according to a tree pattern,” and accordingly, are merely more specific to the abstract idea.
Applicant relies on terms not recited in Applicant’s claims. Applicant submits that the amended claims recite “spatial relationships of these (physical) qubits.” However, the claims do not recite such a “spatial relationship.” The claims simply recite “first adjacent connections connecting adjacent qubits” and “second adjacent connections connecting adjacent qubits,” and “a non-adjacent connection connecting a first qubit of the first group to a second qubit in the second qubit,” which are further details or specifics of the ”tree pattern” of the claims.
In the context of a tree pattern, the plain meaning of the claim term “adjacent” refers to the relationship between trees or branches that share a common point of connection or are located next to each other. Also, in the context of tree patterns, the plain meaning of the claim term "non-adjacent" refers to nodes that are not directly connected by a path within the tree structure.
As set out above in detail, under Step 2A Prong One, the limitation of “[(b)] . . . connections connecting pairs of qubits according to a tree pattern" encompasses the mental observations or evaluations of qubits, which can practically be performed in the human mind, and accordingly, is a mental process, (MPEP § 2106.04(a)(2)), as set out above in detail.
The claim also recites more details or specifics of the abstract idea of “[(b)] connections connecting pairs of qubits according to a tree pattern,” where:
* * *
[(b.1)] first adjacent connections connecting adjacent qubits in the first group according to the tree pattern;
[(b.2)] second adjacent connections connecting adjacent qubits in the second group according to the tree pattern; and
[(b.3)] a non-adjacent connection connecting a first qubit of the first group to a second qubit in the second group that is not adjacent to the first qubit of the first group.
and accordingly, are merely more specific to the abstract idea, as set out above in detail.
25. Applicant submits that “as recited in amended claim 1, ‘connections’ refer to hardware that allows quantum gate operations to be performed on pairs of qubits. Not only is the hardware itself a physical entity but a quantum gate operation is a physical operation. To give a specific example, performing a quantum gate operation on a pair of qubits that changes the quantum states of those qubits is a physical operation performed on physical entities that changes the physical states of those entities.” (Response at pp. 7-8).
Examiner’s Response:
Examiner respectfully disagrees because the plain meaning of the claim term “connections connecting,” in the context of tree patterns, refers to the relationships or pathways between different nodes or branches within the tree structure. Under a broadest reasonable interpretation, the claim term “connections connecting” relate to node relationships of pathways, which is not inconsistent with the Applicant’s disclosure. (MPEP § 2111). Accordingly, the limitation of “[(b)] connections connection . . . according to a tree pattern” is an abstract idea under Step 2A Prong One, as set out above in detail.
Accordingly, the pending claims are subject-matter ineligible, as set out above in detail.
Claim Rejections – 35 U.S.C. § 103
26. Applicant submits that “[t]he combination of Cortese and Hilton does not teach or suggest amended claim 1. For example, the quantum circuits of Cortese do not teach or suggest amended claim 1 because a quantum circuit does not illustrate connections between qubits. Instead, quantum circuits illustrate the order of execution of quantum gates. For more information on quantum circuits, please see paragraph 138 of the current application as filed. Hilton similarly does not teach or suggest amended claim 1.” (Response at p. 8).
Examiner’s Response:
Examiner respectfully disagrees. Hilton ‘510 is relied upon as teaching, inter alia, “controllably communicatively coupling a first inter-cell coupling qubit of the first cell to a second inter-cell coupling qubit of another cell.” (Hilton ‘510 ¶ 0024). Hilton ‘510 also teaches that “qubits, couplers, and/or other devices may be superconducting and may have tunable inductance, which may be controlled by one or more classical computers to model a problem. The one or more classical computers may be used to implement quantum annealing [(that is, a quantum gate operation)] on the quantum processor.” (Hilton ‘510 ¶ 0042).
The plain meaning of “hardware of each connection” in the context of “allowing a quantum gate operation to be performed on a pair of qubits” is to generally provide a communication path for the quantum gate operation to be performed. The broadest reasonable interpretation of the claim term “hardware of each connection” covers the teachings of Hilton ‘510, which is not inconsistent with the Applicant’s disclosure. (MPEP § 2111).
Also, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. Where a rejection of a claim is based on two or more references, a reply that is limited to what a subset of the applied references teaches or fails to teach, or that fails to address the combined teaching of the applied references may be considered to be an argument that attacks the reference(s) individually, as is the case here with the cited prior art of Cortese. MPEP § 2145.IV.
Moreover, the rejections hereinabove clearly sets forth which claim limitations are taught by each of the prior art references, and the reasons why it would be obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant's invention to combine their teachings, and Applicant has not explained why the cited prior art references cannot be combined in the manner set forth in the rejection.
27. Applicant submits that “[a]lthough paragraph 102 [of Hilton ‘510] states that qubits in a cell may be arranged as a tree, this is referring to the physical arrangement of qubits relative to each other. Qubits physically arranged in a tree pattern do not teach or suggest connections that connect pairs of qubits according to a tree pattern, as recited in amended claim 1. Thus, the combination of Cortese and Hilton does not teach or suggest amended claim 1. Thus, amended claim 1, as well as the claims that depend therefrom, are patentable.” (Response at pp. 8-9).
Examiner’s Response:
Examiner respectfully disagrees because Cortese is relied upon as teaching a data loading tree (that is, according to a tree pattern) having at least first and second groups of qubits, as is described above in detail.
Regarding the cited prior art of Hilton ‘510, the reference is relied upon as teaching the limitation of a “hardware of each connection.” Further, Hilton ‘510 also teaches that “qubits, couplers, and/or other devices may be superconducting and may have tunable inductance, which may be controlled by one or more classical computers to model a problem. The one or more classical computers may be used to implement quantum annealing [(that is, a quantum gate operation)] on the quantum processor.” (Hilton ‘015 ¶ 0042). As set out above in detail, the broadest reasonable interpretation of the claim term covers the teachings of Hilton ‘510.
Also, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. Where a rejection of a claim is based on two or more references, a reply that is limited to what a subset of the applied references teaches or fails to teach, or that fails to address the combined teaching of the applied references may be considered to be an argument that attacks the reference(s) individually, as is the case here with the cited prior art of Hilton ‘510. (MPEP § 2145.IV).
Still further, Applicant appears to rely on claim limitations not tethered to the instant claims (e.g., “referring to the physical arrangement of qubits relative to each other” (Response at pp. 8-9)). In contrast, the claim simply recites:
* * *
[(b)] connections connecting pairs of qubits of the n qubits according to a tree pattern,
[(b.1)] hardware of each connection allowing a quantum gate operation to be performed on a pair of qubits, . . . :
* * *
(Claim 1, lines 6-8 (emphasis added by Examiner)). Accordingly, the claims are not limited as suggested by Applicant.
Moreover, the rejections hereinabove clearly sets forth which claim limitations are taught by each of the prior art references, and the reasons why it would be obvious to a person having ordinary skill in the art as of the effective filing date of the Applicant's invention to combine their teachings, and Applicant has not explained why the cited prior art references cannot be combined in the manner set forth in the rejection.
Conclusion
28. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
29. The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
(US Published Application 20160071021 to Raymond) teaches mapping of most real world problems into a quantum processor whose topology implements a bipartite graph often requires increasing a connectivity on the chip or quantum processor. Connectivity may be increased by implementing the concept of logical qubits or “chains” of qubits, where a plurality of qubits are strongly coupled together and represent a single problem variable, and denominated herein as a logical qubit since the plurality of physical qubits in any given chain operate or function as a single qubit, albeit with a higher connectivity that would otherwise be available to a single physical qubit.
(Goodrich et al., “Optimizing Adiabatic Quantum Program Compilation using a Graph-Theoretic Framework,” arXiv (2017)) teaches we introduce a graph-theoretic framework for developing structured embedding algorithms. Using this framework, we introduce a biclique virtual hardware layer to provide a simplified interface to the physical hardware. Additionally, we exploit bipartite structure in quantum programs using odd cycle transversal (OCT) decompositions. By coupling an OCT-based embedding algorithm with new, generalized reduction methods, we develop a new baseline for embedding a wide range of optimization problems into fault-free D-Wave annealing hardware.
30. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to KEVIN L. SMITH whose telephone number is (571) 272-5964. Normally, the Examiner is available on Monday-Thursday 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, KAKALI CHAKI can be reached on 571-272-3719. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.L.S./
Examiner, Art Unit 2122
/KAKALI CHAKI/Supervisory Patent Examiner, Art Unit 2122