DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. Applicant's arguments received 12/22/2025 have been considered but are moot in view of the new ground(s) of rejection. Detailed response is given in sections 3-5 as set forth below in this Office action.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is
not identically disclosed as set forth in section 102 of this title, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have been
obvious before the effective filing date of the claimed invention to a person having ordinary skill in
the art to which the claimed invention pertains. Patentability shall not be negated by the manner in
which the invention was made.
4. Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al. (US 20180211874 A1) in view of Shu et al. (US 20200395356 A1).
Regarding claim 1, Basker discloses a contact over active gate (COAG) layout design reliability test macro (Abstract; para. 0005-0007; Figs. 1, 7, 13 and 15) comprising: gate-shaped structures (e.g., the vertical portions of the gate dielectric layer 150 in Figs. 1, 5 and 15; see also annotated Fig. 1 below) disposed over an active area of a substrate (110 of 99 Fig. 1) and located between a pair of gate spacers (140), the gate-shaped structures formed entirely from a solid dielectric (para. 0046); source/drain regions (120 Fig. 1) present on opposite sides of the gate-shaped structures (para. 0045, 0056-0058); source/drain contacts (combination of source/drain contact liner 200, source/drain contact fill 210 and source/drain contact caps 230 Figs. 7, 13 and 15) in direct contact with the source/drain regions (para. 0085-0087); a dielectric fill material (130 Figs. 1, 7 and 15) disposed on the source/drain contacts; and gate contacts (combination of gate contact liner 250 and gate contact layer 260 Fig. 15) present over, and in direct contact with, the gate-shaped structures in the active area (para. 0107), wherein the dielectric fill material (130) is present in between the gate contacts and the source/drain contacts (Figs. 1, 7 and 15; para. 0059-0060), but not above a bottommost surface of the gate contacts (note, the instant claim 1 does not provide a clear definition for the term “a bottommost surface” in the sense of an object's orientation or relationship in direction with reference to a given physical 3-dimentional coordinate system; accordingly, with the broadest reasonable interpretation to the claim, the outside wall of the gate contact layer 260 reads on “a bottommost surface of the gate contacts”, thus the dielectric fill material 130 is present in between the gate contacts and the source/drain contacts but not above said bottommost surface of the gate contacts, see annotated Fig. 15 below).
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Basker does not mention explicitly: the gate-shaped structures formed entirely from a solid dielectric such that no non-dielectric material is located between the pair of gate spacers.
Shu discloses a semiconductor test structure disposed over a semiconductor substrate (Fig. 2A), comprising: gate-shaped structures (114) disposed over an active area (104) of a substrate (102) and located between a pair of gate spacers (112); source/drain regions (108) present on opposite sides of the gate-shaped structures (para. 0032); wherein the gate-shaped structures formed entirely from a solid dielectric such that no non-dielectric material is located between the pair of gate spacers (para. 0026: “the dummy gate structures 114 include amorphous silicon”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Shu’s teaching of dummy gate structures (114), which are formed entirely from a solid dielectric, into Basker’s invention to assist developing the layout of all the components of the COAG test macro. Doing so would allow for providing a reusable block of design elements to help evaluate the integrity and robustness of a particular layout structure of the test macro. The skilled person would conceive and apply such modification without needing inventive skill but depending on practical considerations and according to the dictates of the circumstances. Also, the skilled person in the art would have recognized that the results of such a modification were predictable for COAG layout design since the use of that known technique provides the rationale to arrive at a conclusion of obviousness. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007).
Regarding claims 2 and 3, Basker discloses: isolation regions (e.g., the bottom portions of 150 Figs. 1, 5 and 15) in the active area below the gate-shaped structures, wherein the isolation regions comprise a same material as the gate-shaped structures (para. 0045).
Regarding claim 4, Basker discloses: wherein the gate-shaped structures comprise a material selected from silicon oxide (para. 0046).
The combination of Basker and Shu does not mention explicitly: wherein the gate-shaped dielectric structures comprise a material selected from the group consisting of: silicon oxide (SiOx), silicon nitride (SiN), and combinations thereof.
Examiner takes official notice that dielectric material such as silicon oxide (SiOx), silicon nitride (SiN), and combinations thereof are well known in the semiconductor industry where they are commonly used for manufacturing dielectric structures. Since Basker and Shu teach the general condition of the material for making the gate-shaped dielectric structures (Basker, para. 0046; Shu, para. 0026), it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the gate-shaped dielectric structures in the combination of Basker/Shu with a desired material selected from the group consisting of: silicon oxide (SiOx), silicon nitride (SiN), and combinations thereof to arrive the claimed invention, depending on practical considerations and according to the dictates of the circumstances. It has been held to be within the general skill of worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 5, Basker discloses: wherein the gate spacers offset (i.e., counteract by having an opposing force or effect) the source/drain regions (120 Fig. 7) from the gate-shaped structures (Figs. 7 and 15; para. 0074).
Regarding claim 6, Basker discloses: wherein the gate spacers (140) is an insulating dielectric layer (para. 0071).
Basker does not mention explicitly: the gate spacers comprise a material selected from the group consisting of: silicon oxide (SiOx), silicon oxycarbide (SiOC), SiN, silicon-boron-nitride (SiBN), siliconborocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and combinations thereof.
Examiner takes official notice that dielectric material such as silicon oxide (SiOx), silicon oxycarbide (SiOC), SiN, silicon-boron-nitride (SiBN), siliconborocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and combinations thereof are well known in the semiconductor industry where they are commonly used as insulating layers between different components of electronic devices, making it a key material in transistor manufacturing. Since Basker and Shu teaches the general condition of the gate spacers material (Basker, para. 0071; Shu, para. 0031), it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the gate spacers in the combination of Basker/Shu to arrive the claimed invention by selecting a desired material from the group consisting of: silicon oxide (SiOx), silicon oxycarbide (SiOC), SiN, silicon-boron-nitride (SiBN), siliconborocarbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and combinations thereof to arrive the claimed invention, depending on practical considerations and according to the dictates of the circumstances. It has been held to be within the general skill of worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 7, Basker discloses: wherein the source/drain contacts (i.e., combination of 200, 210 and 230) are present over the source/drain regions (Figs. 7 and 15).
Regarding claim 8, Basker does not mention explicitly: wherein the source/drain contacts (i.e., the combination of 200, 210 and 230 Figs. 7, 13 and 15) extend below the source/drain regions (120).
Shu discloses semiconductor structures disposed over active regions via contact structures disposed over such active regions (Abstract), comprising: a plurality of source/drain regions (108 Fig. 2A) present on opposite sides of gate-shaped dielectric structures (114 Fig. 2A); source/drain contacts (156 Fig. 12C) in direct contact with the source/drain regions (para. 0078), wherein the source/drain contacts extend below the source/drain regions (Fig. 12C).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Basker’s source/drain contacts in view of Shu’s teaching to arrive the claimed invention as a design choice of the source/drain contacts. The skilled person would conceive and apply such modification without needing inventive skill but depending on practical considerations and according to the dictates of the circumstances. Also skilled person in the art would have recognized that the results of such a modification were predictable for the contact over active gate (COAG) of the semiconductor structures since the use of that known technique provides the rationale to arrive at a conclusion of obviousness.
Regarding claim 9, Basker discloses: wherein the dielectric fill material (the protective layer or insulating dielectric layer 130) is selected from the group consisting of: silicon oxide (SiOx), silicon carbide (SiC), SiOCN, SiN, organosilicate glass (SiCOH), and combinations thereof.
Examiner takes official notice that dielectric material such as silicon oxide (SiOx), silicon carbide (SiC), SiOCN, SiN, and organosilicate glass (SiCOH) are well known in the semiconductor industry where they are commonly used as insulating layers between different components of electronic devices, making it a key material in transistor manufacturing. Since Basker teaches the general condition of the dielectric fill material (para. 0060), it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify Basker’s dielectric fill material with a desired material to arrive the claimed invention depending on practical considerations and according to the dictates of the circumstances. It has been held to be within the general skill of worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 10, Basker discloses: wherein the dielectric fill material has a thickness t of from about 5 nm to about 30 nm (para. 0059).
Regarding claim 11, Basker discloses: wherein the active area comprises fins present on the substrate (para. 0044-0045).
5. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al. in view of Shu et al. further in view of Han et al. (US 20110068332 A1).
Regarding claim 19, Basker discloses a method of making a contact over active gate (COAG) layout design, the method comprising: providing a reliability test macro comprising: gate-shaped structures (e.g., the vertical portions of the gate dielectric layer 150 in Figs. 1, 5 and 15; see also annotated Fig. 1 above) disposed over an active area of a substrate (110 of 99 Fig. 1) and located between a pair of gate spacers (140), the gate-shaped structures formed entirely from a solid dielectric (para. 0046); source/drain regions (120 Fig. 1) present on opposite sides of the gate-shaped dielectric structures (para. 0045, 0056-0058); source/drain contacts (combination of source/drain contact liner 200, source/drain contact fill 210 and source/drain contact caps 230 Figs. 7, 13 and 15) in direct contact with the source/drain regions (para. 0085-0087); a dielectric fill material (130 Figs. 1, 7 and 15) disposed on the source/drain contacts; gate contacts (combination of gate contact liner 250 and gate contact layer 260 Fig. 15) present over, and in direct contact with, the gate-shaped dielectric structures in the active area (para. 0107), wherein the dielectric fill material (130) is present in between the gate contacts and the source/drain contacts (Figs. 1, 7 and 15; para. 0059-0060), but not above a bottommost surface of the gate contacts (see discussion of claim 1 and the annotated Fig. 15 presented above).
Basker does not mention explicitly: the gate-shaped structures being formed entirely from a solid dielectric such that no non-dielectric material is located between the pair of gate spacers; and said method further comprising: applying a voltage V to at least one of the gate contacts; and detecting current between the gate contacts and the source/drain contacts due to breakdown or leakage of the dielectric fill material.
Shu discloses a semiconductor test structure disposed over a semiconductor substrate (Fig. 2A), comprising: gate-shaped structures (114) disposed over an active area (104) of a substrate (102) and located between a pair of gate spacers (112); source/drain regions (108) present on opposite sides of the gate-shaped structures (para. 0032); wherein the gate-shaped structures formed entirely from a solid dielectric such that no non-dielectric material is located between the pair of gate spacers (para. 0026: “the dummy gate structures 114 include amorphous silicon”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Shu’s teaching of dummy gate structures (114), which are formed entirely from a solid dielectric, into Basker’s invention to assist developing the layout of all the components of the COAG test macro. Doing so would allow for providing a reusable block of design elements to help evaluate the integrity and robustness of a particular layout structure of the test macro. The skilled person would conceive and apply such modification without needing inventive skill but depending on practical considerations and according to the dictates of the circumstances. Also, the skilled person in the art would have recognized that the results of such a modification were predictable for COAG layout design since the use of that known technique provides the rationale to arrive at a conclusion of obviousness. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007).
Han discloses a method of evaluating gate insulation layer formed by a dielectric material (para. 0008-0009, 0069, 0107), comprising: applying a voltage to at least one of gate contacts, and detecting current between the gate contacts and source/drain contacts due to breakdown or leakage of the dielectric material (Fig. 20A/20B; para. 0132: “… gate-source leakage current (I.sub.GS, in amps, on the right vertical axis) vs. gate voltage (V.sub.GS)”; para. 0133).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Basker/Shu in view of Han to arrive the claimed invention by incorporating an additional step of evaluating the insulating property of the dielectric material between the gate contacts and the source/drain contacts as taught by Han. Doing so would allow to provide quality control analyses to verify operating stability of the dielectric fill material (Han, para. 0008-0009).
Regarding claim 20, Basker discloses: wherein the reliability test macro further comprises: isolation regions (e.g., the bottom portions of 150 Figs. 1, 5 and 15) in the active area below the gate-shaped structures, wherein the isolation regions comprise a same material as the gate-shaped structures (para. 0045).
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Contact Information
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIUQIN SUN whose telephone number is (571)272-2280. The examiner can normally be reached 9:30am-6:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby A. Turner can be reached on (571) 272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/X.S/Examiner, Art Unit 2857
/SHELBY A TURNER/Supervisory Patent Examiner, Art Unit 2857
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