Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed March 31st, 2026 has been entered. Claims 1-19 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US Patent Application Publication 20190064329 A1), hereinafter Liu, in view of Liu et al (US Patent Application Publication 20190302241 A1), hereinafter Liu and Gao, in view of Trueblood et al. (United States Patent No. 1063221 B1), hereinafter Trueblood, further in view of Skirlo et al. (United States Patent Application Publication 20190265574 A1), hereinafter Skirlo.
Regarding claim 1, Liu teaches a measurement device for the three-dimensional geometric capture of an environment (Fig. 1B; [0036] a representative LIDAR system 150), comprising:
a multi-beam emitter for emitting a plurality of transmission beams ([0036] a light emitter 152 that can generate a laser beam (e.g., in the form of one or more light pulses). The laser beam can be a single laser pulse or a series of laser pulses),
a multi-beam receiver having a plurality of receiving areas for receiving emitted transmission beams of the plurality of transmission beams returning from the environment ([0038] The return beam 166 (e.g., in the form of one or more returning light pulses) can be reflected by the beam splitting device 156 toward a receiving lens 168, which can collect and focus the returned beam on a detector 170), and
a receiver circuit ([0038] A controller 172 including measuring circuitry, such as a TOF unit, can be used to measure the TOF in order to determine the distance to the object 180), wherein:
the receiver circuit is configured to carry out a time measurement of a signal change of the input signal by sampling the binary outputs of the respective delay line and simultaneous consideration of the sampled binary outputs at a certain point in time by further taking into account individual time delays of the delay elements ([0062] The TDC has a series of sequentially coupled delay units. In some embodiments, calibrating the FPGA includes determining delay times associated with some or all of the delay units. The individual delay time can be an average delay time across multiple delay units, or can be an individual delay time that is determined separately for each delay unit.), and
the receiver circuit further comprises: a reference generator configured to generate a reference signal having a reference signal change, wherein the reference signal is asynchronous to a sampling clock driving the sampling of the binary outputs ([0067] The calibration signals can be digital signals, such as a square wave signal including a rising edge and/or a falling edge. In some embodiments, the calibration signals are randomized signals, e.g., randomized with respect to timing), and
a selector configured that individual ones of the delay lines are fed with individual ones of the return signals and that alternating each of the individual ones of the delay lines is fed with the reference signal instead ([0067] The plurality of calibration signals can be sequentially received and propagated through the series of sequentially coupled delay units, such that the series receives a single calibration signal at a time and does not receive the next calibration signal until the previous signal has propagated through the series); and
the receiver circuit is configured to carry out a statistical analysis of the sampled binary outputs that correspond to the reference signal that propagated through one of the delay lines ([0077] In some embodiments, if the number of randomized calibration signals used is sufficiently large, the probability that a delay unit will be the last in the series to receive a signal will be proportional to its count, and the count will be proportional to its individual delay time;) and, based thereof, to determine individual time delays of the delay elements of the one of the delay lines and to take into account the determined individual time delays in the time measurement of the signal change when the one of the delay lines is fed with one of the return signals (Fig. 11; [0102] Block 830 includes outputting a pulse signal representing the returning light pulse; [0103] Block 840 includes measuring timing information of the pulse signal using an FPGA).
Liu fails to teach the receiver circuit comprising a programmable integrated circuit having a plurality of parallel delay lines, wherein each delay line has a plurality of delay elements, which sequentially propagate an input signal of the respective delay line, wherein each of the delay elements is configured to provide a binary output as a function of the input signal,
However, Liu and Gao teaches the receiver circuit comprising a programmable integrated circuit having a plurality of parallel delay lines, wherein each delay line has a plurality of delay elements, which sequentially propagate an input signal of the respective delay line, wherein each of the delay elements is configured to provide a binary output as a function of the input signal,
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the parallel arrangement of delay lines similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of ensuring the same input and reference signal is received by ever delay unit.
Liu, as modified, fails to teach the device comprising a selector enabling a calibration process of the delay lines in parallel to the three-dimensional geometric capture of an environment and the receiver circuit configured to perform the calibration process.
However, Trueblood teaches the device comprising a selector enabling a calibration process of the delay lines in parallel to the three-dimensional geometric capture of an environment and the receiver circuit configured to perform the calibration process ([Col. 8, line 43 - Col. 9, line 3] To repeat certain sampling operations, the time delay control module 340 can increment the programmable time delay for the delay circuit so that when a transmitter is triggered, the receiver can receive a reflected signal at an incremented time delay value. In some embodiments, the programmable time delay is incremented by adding a predetermined time delay value to a previous programmable time delay; [Col. 9, lines 44-54] As shown in FIG. 6, in some implementations, the trigger selection module 390 controls the select input of the multiplexer 614 to select either the embedded system 610 or the sensor 616 as the source of the pulse for the receiver. As further described in FIG. 6, in some embodiments, the embedded system is preset to generate the triggers for the receiver unless it receives an interrupt from the sensor. In some other embodiments, the embedded system may dynamically choose between the embedded system and the sensor as the source of the trigger for the receiver.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the calibration parallel to scanning systems similar to Trueblood, with a reasonable expectation of success. This would have the predictable result of increasing the efficiency of the system, reducing the direct user input, and allowing the calibration of the device to occur automatically and autonomously.
Liu, as modified, fails to teach a receiver circuit comprising a plurality of measurement channels configured to generate return signals corresponding to respective emitted transmission beams and to time signal changes of the return signals in order to derive time- of-flights of the respective emitted transmission beams
However, Skirlo teaches a receiver circuit comprising a plurality of measurement channels configured to generate return signals corresponding to respective emitted transmission beams and to time signal changes of the return signals in order to derive time- of-flights of the respective emitted transmission beams ([Fig. 3A-3B]; [0058] FIGS. 3A and 3B show how the system can be used to transmit and receive, respectively. Transmission works as described above: exciting an input to the planar dielectric lens yields a plane wave that propagates in a given direction... Receiving works in reverse: the grating collects incident light, and the lens focuses the incident light on the input port associated with the corresponding in-plane angle-of-arrival; [0048] The MZI switch matrix 120 can be replaced by a 3 dB splitting tree (not shown) that illuminates all of the input ports 114 in parallel.)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu, as modified, to comprise the receiver circuit with matching input and output channels similar to Skirlo, with a reasonable expectation of success. This would have the predictable result of ensuring cohesive signal is maintained across transmission and reception of the scan, in a configuration that is known to the art and is cohesive with the switch network established.
Regarding claim 2, Liu, as modified above, teaches the measurement device according to claim 1, wherein the delay elements are configured to provide the binary outputs by recognition of a rising and/or a falling edge of the input signal ([0052] the FPGA receives and samples a square wave signal representing changes in the value of a digital signal value over time to determine time values for the rising and/or falling edges of the signal. The time values for the rising and/or falling edges of the square wave signal can represent the time points at which the analog pulse signal reaches, exceeds, and/or falls below a particular voltage value.).
Regarding claim 3, Liu, as modified above, teaches the measurement device according to claim 1, wherein the receiver circuit comprises a common sampling clock configured to commonly drive the sampling of the binary outputs for all of the delay lines.
Regarding claim 4, Liu, as modified above, teaches the measurement device according to claim 1, wherein the receiver circuit is configured to:
count clock cycles of the sampling clock before the occurrence of the signal change ([0059] The TDC 220 is configured to receive a clock signal 230 (e.g., from an clock of the FPGA 208).), and
determine the elapsed time between clock cycles of the sampling clock since the occurrence of the signal change by using an asynchronous logic ([0059] The TDC 220 is configured to receive a clock signal 230 (e.g., from an clock of the FPGA 208).),
wherein the time measurement of the signal change is carried out by combining the counted clock cycles of the sampling clock and the determined elapsed time between clock cycles of the sampling clock ([0059] At each clock cycle (e.g., prior to or at the time the TDC 220 receives the next edge of the clock signal 230), the TDC 220 can determine the number of delay units triggered by the signal 228 based on the latched output signal of the latch unit 224 to provide a high resolution time value corresponding to the rising or falling edge of the signal 228.).
Regarding claim 5, Liu, as modified above, teaches the measurement device according to claim 1,
Liu, as modified, fails to teach for each of the plurality of parallel delay lines, the receiver circuit comprising a register line, each register line having a plurality of registers associated to the plurality of delay elements and being configured to store the binary outputs.
However, Liu and Gao teaches for each of the plurality of parallel delay lines, the receiver circuit comprising a register line, each register line having a plurality of registers associated to the plurality of delay elements and being configured to store the binary outputs ([0049] An FPGA is an integrated circuit including a plurality of logic blocks that can be programmed by a user after the manufacturing of the FPGA to provide a wide variety of different functionalities... Each logic block can include a plurality of logic cells or slices. A logic cell or slice can include a plurality of components that can be configured by the user to implement logic functions, including but not limited to one or more LUTs (e.g., 3-input or 4-input LUTs), flip-flops, multiplexers, and/or carry logic.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the register lines such as the line of flip-flop units similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of aligning the input data into a desired arrangement for desired processing.
Regarding claim 6, Liu, as modified above, teaches the measurement device according to claim 1.
Liu, as modified, fails to teach for each of the plurality of parallel delay lines, the receiver circuit comprising multiple parallel register lines, each register line having a plurality of registers associated to the plurality of delay elements and being configured to store the binary outputs, and the receiver circuit is configuring an input signal propagating through a respective delay line of the plurality of delay lines is individually sampled by each of the corresponding register lines.
However, Liu and Gao teaches for each of the plurality of parallel delay lines, the receiver circuit comprising multiple parallel register lines, each register line having a plurality of registers associated to the plurality of delay elements and being configured to store the binary outputs ([0049] An FPGA is an integrated circuit including a plurality of logic blocks...Each logic block can include a plurality of logic cells or slices. A logic cell or slice can include a plurality of components that can be configured by the user to implement logic functions, including but not limited to one or more LUTs (e.g., 3-input or 4-input LUTs), flip-flops, multiplexers, and/or carry logic.), and
the receiver circuit is configuring an input signal propagating through a respective delay line of the plurality of delay lines is individually sampled by each of the corresponding register lines ([0080] The FPGA 800 includes a plurality of delay units 802a-802n sequentially coupled to each other.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the register lines that are sampled by the delay units similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of aligning the time delayed input data into a desired arrangement for desired processing.
Regarding claim 7, Liu, as modified above, teaches the measurement device according to claim 1.
Liu, as modified, fails to teach the receiver circuit comprising a distributor section configured to generate several identical distributor section output signals out of a distributor section input signal, wherein the distributor section output signals are copies of the distributor section input signal, and the receiver circuit configured to feed the distributor section output signals to several of the plurality of parallel delay lines in parallel, wherein the receiver circuit is configured that the distributor section is fed with one of the return signals and/or the distributor section is fed with the reference signal.
However, Liu and Gao teaches the receiver circuit comprising a distributor section configured to generate several identical distributor section output signals out of a distributor section input signal, wherein the distributor section output signals are copies of the distributor section input signal (Fig. 7; [0076] The FPGA 700 includes a plurality of differential input ports 704a-704d), and
the receiver circuit configured to feed the distributor section output signals to several of the plurality of parallel delay lines in parallel (Fig. 7),
wherein the receiver circuit is configured that the distributor section is fed with one of the return signals and/or the distributor section is fed with the reference signal ([0076] The magnitude of the delay times can be determined by comparing the known timing of the square wave signal 702 to the time measurements generated by the TDCs 708a-708d.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the distributor section similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of equally distributing the return and reference signal to all parallel delay lines.
Regarding claim 8, Liu, as modified above, teaches the measurement device according to claim 1.
Liu, as modified, fails to teach the receiver circuit comprising multiple comparators providing different switching thresholds, each comparator providing a corresponding comparator output signal as a function of the corresponding switching threshold, the receiver circuit configured that individual comparator output signals are fed in parallel to individual delay lines of the plurality of parallel delay lines, and the receiver circuit configured that the multiple comparators are fed with comparator input signals generated from one of the return signals and/or from the reference signal.
However, Liu and Gao teaches the receiver circuit comprising multiple comparators providing different switching thresholds, each comparator providing a corresponding comparator output signal as a function of the corresponding switching threshold ([0047] FIG. 3 is a schematic illustration of a multi-comparator sampling configuration 300 in accordance with embodiments of the present technology...Each of the comparators is coupled to the same input to perform timing measurement on the same light pulse, but each of the comparators has a different triggering threshold),
the receiver circuit configured that individual comparator output signals are fed in parallel to individual delay lines of the plurality of parallel delay lines ([0047] Each comparator is connected to its respective individual time-to-digital converter (TDC), 350a-350d.), and
the receiver circuit configured that the multiple comparators are fed with comparator input signals generated from one of the return signals and/or from the reference signal ([0045] For example, when an analog pulse signal 202 (e.g., representing a light pulse that is reflected back from a target object) is received at the non-inverting input PIN3, the comparator 240 compares the voltage level of the signal 202 against a reference threshold 206 at the inverting input PIN4).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the parallel comparators similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of increasing the speed of signal processing.
Regarding claim 9, Liu, as modified above, teaches the measurement device according to claim 8, wherein the receiver circuit is configured to compare the comparator output signals in order to determine amplitude dependent timing offsets in the time measurement of the signal change (Liu and Gao: Fig. 2B; [0045] The signal 202 has two sections: a leading section in which the magnitude increases, and a trailing section in which the magnitude decreases. When the magnitude in the leading section of signal 202 exceeds the reference threshold 206, the output of the comparator 202 becomes high (e.g., VDD). Similarly, when the magnitude in the trailing section of signal drops below the reference threshold 206, the output of the comparator 202 becomes low (e.g., GND). The result is a digitized (e.g., binary) square pulse signal 204.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to use the comparators to determine amplitude dependent timing offsets similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of using a known threshold as a way of measuring the signal to mark the time of reception.
Regarding claim 10, Liu, as modified above, teaches the measurement device according to claim 1, wherein the statistical analysis to determine the individual time delays of the delay elements of the one of the delay lines is based on multiple propagations of the reference signal through the one of the delay lines and the assumption that a rising and/or falling edge of the reference signal is evenly distributed over time ([0067] The calibration signals can be digital signals, such as a square wave signal including a rising edge and/or a falling edge. In some embodiments, the calibration signals are randomized signals, e.g., randomized with respect to timing. For example, the calibration signals can be digital square wave signals in which the timing of the rising and/or falling edges of the square wave signals are randomized).
Regarding claim 11, Liu, as modified above, teaches the measurement device according to claim 1, wherein each of the plurality of parallel delay lines comprises at least one hundred delay elements ([0055] Any suitable number of delay units can be used, such as at least 10, at least 25, at least 50, at least 100, or at least 200 delay units).
Regarding claim 12, Liu, as modified above, teaches the measurement device according to claim 1, wherein the receiver circuit comprises an analysis unit being separate from the programmable integrated circuit comprising a further programmable integrated circuit or a microprocessor (Fig. 2; [0045] controller 206), wherein the analysis unit is configured:
to carry out the simultaneous consideration of the sampled binary outputs at a certain point in time for the time measurement of the signal change ([0045] the controller 206 receives the digital signal values and time values generated by the FPGA 208, and calculates the distance to the object based on the digital signal values and time values), and
to carry out the statistical analysis of the sampled binary outputs that correspond to the reference signal that propagated through one of the delay lines, and, based thereof, to determine the individual time delays of the delay elements of the one of the delay lines ([0046] The controller 206 can fit the digital signal values and time values to the pulse signal model and derive an estimated time value based on the shape of the model).
Regarding claim 16, Liu, as modified above, teaches the measurement device according to claim 4:
Liu, as modified, fails to teach each of the plurality of parallel delay lines such that the receiver circuit comprises multiple parallel register lines, each register line having a plurality of registers associated to the plurality of delay elements and being configured to store the binary outputs, and the receiver circuit is configured that an input signal propagating through a respective delay line of the plurality of delay lines is individually sampled by each of the corresponding register lines.
However, Liu and Gao teaches each of the plurality of parallel delay lines such that the receiver circuit comprises multiple parallel register lines, each register line having a plurality of registers associated to the plurality of delay elements and being configured to store the binary outputs ([0049] An FPGA is an integrated circuit including a plurality of logic blocks that can be programmed by a user after the manufacturing of the FPGA to provide a wide variety of different functionalities... Each logic block can include a plurality of logic cells or slices. A logic cell or slice can include a plurality of components that can be configured by the user to implement logic functions, including but not limited to one or more LUTs (e.g., 3-input or 4-input LUTs), flip-flops, multiplexers, and/or carry logic.), and
the receiver circuit is configured that an input signal propagating through a respective delay line of the plurality of delay lines is individually sampled by each of the corresponding register lines (Fig. 7; delays 706a-706d; FPGA 700).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the register line sampling of the delay lines, similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of efficiently processing and organizing the data for processing a returned signal.
Regarding claim 17, Liu, as modified above, teaches the measurement device according to claim 1, wherein each of the plurality of parallel delay lines comprises at a least one thousand delay elements ([0055] Any suitable number of delay units can be used, such as at least 10, at least 25, at least 50, at least 100, or at least 200 delay units.).
Regarding claim 19, Liu, as modified above, teaches the measurement device according to claim 8, wherein the receiver circuit is configured to compare the comparator output signals in order to determine amplitude dependent timing offsets in the time measurement of the signal change due to range walk (Liu and Gao: Fig. 2B; [0045] The signal 202 has two sections: a leading section in which the magnitude increases, and a trailing section in which the magnitude decreases. When the magnitude in the leading section of signal 202 exceeds the reference threshold 206, the output of the comparator 202 becomes high (e.g., VDD). Similarly, when the magnitude in the trailing section of signal drops below the reference threshold 206, the output of the comparator 202 becomes low (e.g., GND). The result is a digitized (e.g., binary) square pulse signal 204.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu to comprise the receiver circuit and comparator configured to amplitude timing offsets, similar to Liu and Gao, with a reasonable expectation of success. This would have the predictable result of detecting range walk problems in a returned signal.
Claims 13-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, in view of Liu and Gao, Trueblood, Skirlo, and further in view of Hall et al. (US Patent Application Publication 20180321360 A1), hereinafter Hall.
Regarding claim 13, Liu, as modified above, teaches the measurement device according to claim 1.
Liu and Liu and Gao fail to teach the measurement device that comprises laser pulser electronics configured to generate a synchronized laser trigger signal for triggering laser pulse emission in the scope of emitting of the plurality of transmission beams, wherein: the programmable integrated circuit comprises a trigger generator configured to generate an initial trigger signal, and the laser pulser electronics is configured to generate the synchronized laser trigger signal by synchronizing the initial trigger signal with a known transmission clock signal, wherein the transmission clock signal is generated by the same clock source as the sampling clock.
However, Hall teaches the measurement device that comprises laser pulser electronics configured to generate a synchronized laser trigger signal for triggering laser pulse emission in the scope of emitting of the plurality of transmission beams ([0041] Illumination source 132 emits a measurement pulse of illumination light 134 in response to a pulse of electrical energy 131), wherein:
the programmable integrated circuit comprises a trigger generator configured to generate an initial trigger signal ([0040] Pulse trigger signal 143 is communicated to illumination driver IC 140 and directly triggers illumination driver IC 140 to provide an electrical pulse 131;), and
the laser pulser electronics is configured to generate the synchronized laser trigger signal by synchronizing the initial trigger signal with a known transmission clock signal, wherein the transmission clock signal is generated by the same clock source as the sampling clock ([0040] In this manner, pulse trigger signal 143 generated based on the internal clock of receiver IC 150 is employed to trigger both pulse generation and return pulse data acquisition.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu, as modified above, to comprise the synchronized laser trigger, similar to Hall, with a reasonable expectation of success. This would have the predictable result of synchronizing signals to ensure coherent and known signal times for a better time-of-flight measurement.
Regarding claim 14, Liu, as modified above, teaches the measurement device according to claim 13, wherein the measurement device comprises a linking generator and multiple laser triggers, wherein:
each of the laser triggers is configured to provide the triggering of laser pulse emission in the scope of emitting an associated transmission beam of the plurality of transmission beams (Hall: [0040] Pulse trigger signal 143 is communicated to illumination driver IC 140 and directly triggers illumination driver IC 140 to provide an electrical pulse 131 to illumination source 132, which causes illumination source 132 to generate a pulse of illumination light 134),
the multiple laser triggers are controlled by the same synchronized laser trigger signal ([0040] This ensures precise synchronization of pulse generation and return pulse acquisition which enables precise time of flight calculations.),
the linking generator is configured to generate activation signals for the transmission beams associated to the multiple laser triggers, wherein each of the transmission beams associated to the multiple laser triggers is uniquely assigned to one of the activation signals ([0038] In these embodiments, master controller 190 communicates a distinct pulse command signal 191 to each different integrated LIDAR measurement device), and
the measurement device is configured that each of the activation signals activates the emission of its associated transmission beam by its associated laser trigger ([0041] Illumination source 132 emits a measurement pulse of illumination light 134 in response to a pulse of electrical energy 131).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu, as modified above, to comprise the linking generator with synchronized and unique triggers, similar to Hall, with a reasonable expectation of success. This would have the predictable result of synchronizing signals to ensure coherent and known signal times for a better time-of-flight measurement.
Regarding claim 15, Liu, as modified above, teaches the measurement device according to claim 1, wherein the measurement device is configured to feed the laser trigger signal to a delay line of another programmable integrated circuit and, based thereof, to determine an emission time of the laser trigger signal (Fig. 7; [0076] the timing of the square wave signal 702 differs from the timing of the digital signal values output by the differential input ports 704a-704d due to delay times exhibited by the differential input ports 704a-704d, schematically represented herein by port delays 706a-706d).
Liu, as modified, fails to teach the programmable integrated circuit that comprises a trigger generator configured to generate a laser trigger signal.
However, Hall teaches the programmable integrated circuit that comprises a trigger generator configured to generate a laser trigger signal ([0038] Master controller 190 is configured to generate a pulse command signal 191 that is communicated to receiver IC 150 of integrated LIDAR measurement device 130...master controller 190 coordinates the timing of LIDAR measurements performed by any number of integrated LIDAR measurement devices.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu, as modified above, to comprise integrated circuit fed a laser trigger to determine emission time of the trigger, similar to Hall, with a reasonable expectation of success. This would have the predictable result of increasing processing speed in one IC by the trigger of another IC.
Regarding claim 18, Liu, as modified above, teaches the measurement device according to claim 14, wherein the programmable integrated circuit comprises a trigger generator configured to generate a laser trigger signal (Hall: [0040] Pulse trigger signal 143 is communicated to illumination driver IC 140 and directly triggers illumination driver IC 140 to provide an electrical pulse 131 to illumination source 132, which causes illumination source 132 to generate a pulse of illumination light 134), and the measurement device is configured to feed the laser trigger signal to a delay line of another programmable integrated circuit and, based thereof, to determine an emission time of the laser trigger signal (Fig. 7; [0076] The magnitude of the delay times can be determined by comparing the known timing of the square wave signal 702 to the time measurements generated by the TDCs 708a-708d.).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of this invention to modify the invention of Liu, as modified above, to comprise the trigger generator, measurement device, and integrated circuit to determine an emission time of the trigger, similar to Hall, with a reasonable expectation of success. This would have the predictable result of increasing processing speed through compartmentalized components to determine laser emission times.
Response to Arguments
Applicant's arguments filed March 31st, 2026 have been fully considered but they are not persuasive.
Regarding the amendments made, the amended claim limitation has been addressed in the newly amended claim rejection, with reason for obviousness to combine provided.
In regards to the argument that the combination of Trueblood with the other prior art of record fails to teach the immediate invention of claim 1, the examiner points to the use of Trueblood to teach the parallel operation in conjunction with the prior art of Liu. In combination with the referencing calibration method of Liu, the parallel operations of Trueblood shows this configuration of circuitry to be a standard practice in the art and one of ordinary skill in the art would be motivated to combine such features as a method of expediting the process outlined by the prior art of Liu.
Regarding the argument that one of ordinary skill would interpret "asynchronous" to be linked to a temporal distribution of signal changes, it is noted that claims are examined in the context that they are presented. The independent claim of the claim set does not limit the invention in such a way that the only interpretation of the language used points to the interpretation presented. Claims are examined under the broadest reasonable interpretation to one of ordinary skill in the art and under such a criteria, the prior art teaches an asynchronous signal, as argued previously, for the independent claim. As such the rejections made previously are maintained in this Final Office Action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERT W VASQUEZ/Examiner, Art Unit 3645
/HELAL A ALGAHAIM/SPE , Art Unit 3645
Prosecution Insights