DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 30-43 are rejected under AIA 35 U.S.C. 103 as being unpatentable over US 2017/0290521 to Angle in view of US 2005/0127936 to Chen and US 20090177144 to Masmanidis.
As per claim 30, Angle discloses a method of assembling a neural recording probe (see neural-interface probe 100 in Fig 1A; also see Fig 14) having a terminal (see proximal portions 312b of the wires 312 in Fig 3-4; also see Fig 14) with a plurality of bumps (see connection pads 317 in Fig 3, and substrate wire bumps 319 in Fig 4, and connection pads 1417 in Fig 14 Part A) projecting from a bottom surface thereof, with a neural recording front-end integrated circuit (see chip 120 in Fig 1A, and chip 620 in Fig 6, and chip 1420 in Fig 14; Para 0070 indicates that the chips 120/160/1420 can be integrated circuits) having a plurality of area pads (see array of bond pads 622 of chip 620 in Fig 6) each having an active circuit buried thereunder (it is inherent and/or obvious that integrated circuits include buried circuits which are overlayed and connected to the pads of the integrated circuits), wherein a neural probe (see substrate 110/314 in Fig 1A and 3-4 respectively) connects the terminal to an implantable portion (see distal portions 112c/312c of wires 112/312 in Fig 1A, 3-4, and 14 respectively), wherein the implantable portion includes a plurality of shanks (see individual distal portions 112c/312c of wires 112/312 in Fig 1A, 3-4, and 14 respectively), and wherein the method comprises:
depositing an anisotropic conductive film ACF (see anisotropic conductive adhesive 1444 in Fig 14 Part B which can be an anisotropic conductive film as indicated by Para 0096) between the bumps of the terminal and the area pads of the integrated circuit (see Fig 14 Part C);
aligning a terminal of the neural probe with the integrated circuit such that the bumps projecting from the bottom surface of the terminal are aligned with respective area pads of the integrated circuit (see Fig 14 Part C; Para 0097);
applying pressure between the terminal and the integrated circuit at a predetermined temperature (see thermocompression bonding in Fig 14 Part D; Para 0097); and
cooling the terminal and the integrated circuit until the ACF hardens (see Fig 14 Part D; Para 0097; it is inherent and/or obvious that the thermocompression bonding described in Para 0097 would include cooling the chip 1420 and the wire bundle substrate 1410 from the elevated temperatures used during thermocompression bonding).
As per claim 30, Angle discloses the elements of the current invention as detailed above with respect to claim 30. The embodiment of Angle used to reject the above elements of claim 30 discloses that the anisotropic conductive film ACF is deposited onto the bumps of the terminal rather than on the area pads of the integrated circuit as claimed. However, it would be within the skill of one of ordinary skill in the art to determine where to deposit an electrically conducting material between two structures to electrically connect the two structures to each other. Further, Angle discloses alternative embodiments in which electrically conductive material and/or filler materials, which are functional equivalents to the anisotropic conductive film ACF used in the current embodiment, are deposited on the area pads of the integrated circuit rather than on the bumps of the terminal (see solder caps 1526a deposited on the conductive pillars 1528 of the chip 1520 in Fig 15, and the solder caps 1626a and the chip level underfill 1646 deposited on the conductive pillars 1628 of the chip 1620 in Fig 16; Para 0098-0100).
Further, Chen discloses a similar method of using an anisotropic conductive film ACF wherein the anisotropic conductive film (see SCF 50 in Fig 4) is simply provided between terminal pads (14) of a substrate (10) and bumps (22) of a driver IC (20) and compressed and heated between the terminal pads and the bumps to adhesively bond the driver IC to the substrate and electrically connect the bumps 22 to the terminal pads 14 (Para 0018), therefore inherently implying that the positioning of the anisotropic conductive film on either the pads of the substrate or the bumps of the driver IC is not critical for the effective use of the anisotropic conductive film.
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the invention of Angle so as to deposit the ACF onto the area pads of the integrated circuit rather than on the bumps of the terminal as taught by Chen and the alternative embodiments of Angle. One of ordinary skill in the art would recognize that determining where to deposit an ACF electrically conducting two structures together between the two structures would be well within the skill of one of ordinary skill in the art based on the suitability for the intended final application and that there are only so many options for where to deposit an ACF material between two structures being electrically connected to each other and therefore it would be a routine matter to one of ordinary skill in the art to choose to deposit the ACF on the area pads on the integrated circuit as claimed in light of Angle and Chen; the obvious advantage being that this would ensure that the ACF is not misaligned with the array of pads of the integrated circuit while the ACF would still effectively electrically connect the area pads of the integrated circuit to the bumps of the terminal, thereby reducing potential connection failures to the IC as would be generally understood by one of ordinary skill in the art.
As per claim 30, Angle and Chen disclose the elements of the current invention as detailed above with respect to claim 30, but Angle does not explicitly disclose that each shank of the plurality of shanks (see 112c/312c in Fig 1A and 3-4 respectively) includes a plurality of electrodes mounted therein. However, it is well-known in the art to provide shank portions of an implantable portion with plural electrodes in order in increase the available electrodes to increase the number of signals that can be received and/or recorded by the probe, and therefore it would have been an obvious choice for one of ordinary skill in the art to choose to have shank portions with plural electrodes mounted therein.
Further, Masmanidis discloses a similar neural recording probe and method of making the neural recording probe that uses a ACF film (see anisotropic conducting film 602 in Fig 6) for assembly, wherein the implantable portion of the neural probe includes multiple shank portions each with plural electrodes mounted therein to allow for any suitable number of electrodes to be used that advantageously can separately address sites at different locations including front and back sides of the shanks (see Fig 3, 5-7, 11, 14-15, 18-19; see abstract; see Para 0005-0006, 0037-0038, 0042)
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the above combination of Angle and Chen so as to modify the shank portions to each include plural electrode mounted therein as taught by Masmanidis. One of ordinary skill in the art would recognize that it is well-known in the art to provide shank portions of an implantable portion with plural electrodes in order to in increase the available electrodes to increase the number of signals that can be received and/or recorded by a certain number of shanks, and that choosing the number of electrodes to provide on a shank would be well within the skill of one of ordinary skill in the art based on the suitability for the intended final application, therefore it would be a routine matter to one of ordinary skill in the art to choose to have plural electrodes mounted on each shank as taught by Masmanidis; the obvious advantage being that the plural electrodes would allow for any suitable number of electrodes to be used that could advantageously separately address sites at different locations including front and back sides of the shanks (Masmanidis: Para 0038, 0042)
As per claim 31, Angle, Chen, and Masmanidis discloses the elements of the current invention as detailed above with respect to claim 30. Angle further discloses that the number of electrodes (see electrodes 315 being the end portions of the conductive cores 316 of the wires 312 in Fig 3-4) can be 1000, 10000, or 1000000 wires, greater than 1000000 wires, or any number between the aforementioned ranges (Para 0049) and a same number of area pads (Para 0074 indicates that the number of wires to pads of the integrated circuit can have a 1:1 correspondence) wherein it is inherent and/or obvious that the integrated circuit of the chips as disclosed in Angle include buried circuits which are overlayed and connected to the pads of the integrated circuits.
As per claim 32, Angle discloses a method of electrically connecting electrical conductors of a cable (see wires 112 of wire bundle substrate 110 in Fig 1A, and wires 312 of wire bundle substrate 310 in Fig 3-4, and wire bundle substrate 1410 in Fig 14) for a multi-channel neural probe (see neural-interface probe 100 in Fig 1A; also see Fig 14) to an integrated circuit (see chip 120 in Fig 1A, and chip 620 in Fig 6, and chip 1420 in Fig 14; Para 0070 indicates that the chips 120/160/1420 can be integrated circuits) having an array of area pads (see array of bond pads 622 of chip 620 in Fig 6) that are each electrically connected to a corresponding active circuit located underneath the area pad (it is inherent and/or obvious that integrated circuits include buried circuits which are overlayed and connected to the pads of the integrated circuits), the method comprising:
providing a cable (see wires 112 provided in the wire bundle substrate 110 in Fig 1A, and wires 312 in wire bundle substrate 310 in Fig 3-4, and wire bundle substrate 1410 in Fig 14) comprising electrical conductors (see conductive cores 316 in Fig 3-4; also see Fig 14) and a terminal (see proximal portions 312b of the wires 312 in Fig 3-4; also see Fig 14) at one end of the cable, wherein the cable connects the terminal to an implantable portion (see distal portions 112c/312c of wires 112/312 in Fig 1A, 3-4, and 14 respectively), wherein the implantable portion includes a plurality of shanks (see individual distal portions 112c/312c of wires 112/312 in Fig 1A, 3-4, and 14 respectively), wherein the terminal comprises a rigid body (see support base 314 in Fig 3-4; also see Fig 14) having a plurality of electrically-conductive bumps (see connection pads 317 in Fig 3, and substrate wire bumps 319 in Fig 4, and connection pads 1417 in Fig 14 Part A) each connected to one of the electrical conductors of the cable, wherein the bumps project outwardly from the rigid body (see Fig 3 and 4 which depict two embodiments of Angle, both of which the proximal portions 312b of the wires 312, i.e. the connection pads 317 in Fig 3 and the substrate wire bumps 319 in Fig 4, project outwardly from the support base 314; also see Fig 14 which corresponds to the embodiment of Fig 3 as indicated by Para 0096) and are arranged in an array corresponding in size and shape to the array of area pads on the integrated circuit (see chip 620 with array of bond pads 622 in Fig 6 corresponding to the array of connection pads 1417 of the wire bundle substrate 1410 in Fig 14);
depositing an anisotropic conductive film ACF (see anisotropic conductive adhesive 1444 in Fig 14 Part B which can be an anisotropic conductive film as indicated by Para 0096) between the bumps of the terminal and the area pads of the integrated circuit (see Fig 14 Part C);
aligning the terminal of the cable with the integrated circuit such that the bumps projecting from the bottom surface of the terminal are aligned with respective area pads of the integrated circuit (see Fig 14 Part C; Para 0097);
applying pressure between the terminal and the integrated circuit at an elevated temperature (see thermocompression bonding in Fig 14 Part D; Para 0097); and
cooling the terminal and the integrated circuit until the ACF hardens (see Fig 14 Part D; Para 0097; it is inherent and/or obvious that the thermocompression bonding described in Para 0097 would include cooling the chip 1420 and the wire bundle substrate 1410 from the elevated temperatures used during thermocompression bonding).
As per claim 32, Angle discloses the elements of the current invention as detailed above with respect to claim 32. The embodiment of Angle used to reject the above elements of claim 32 discloses that the anisotropic conductive film ACF is deposited onto the bumps of the terminal rather than on the area pads of the integrated circuit as claimed. However, it would be within the skill of one of ordinary skill in the art to determine where to deposit an electrically conducting material between two structures to electrically connect the two structures to each other. Further, Angle discloses alternative embodiments in which electrically conductive material and/or filler materials, which are functional equivalents to the anisotropic conductive film ACF used in the current embodiment, are deposited on the area pads of the integrated circuit rather than on the bumps of the terminal (see solder caps 1526a deposited on the conductive pillars 1528 of the chip 1520 in Fig 15, and the solder caps 1626a and the chip level underfill 1646 deposited on the conductive pillars 1628 of the chip 1620 in Fig 16; Para 0098-0100).
Further, Chen discloses a similar method of using an anisotropic conductive film ACF wherein the anisotropic conductive film (see SCF 50 in Fig 4) is simply provided between terminal pads (14) of a substrate (10) and bumps (22) of a driver IC (20) and compressed and heated between the terminal pads and the bumps to adhesively bond the driver IC to the substrate and electrically connect the bumps 22 to the terminal pads 14 (Para 0018), therefore inherently implying that the positioning of the anisotropic conductive film on either the pads of the substrate or the bumps of the driver IC is not critical for the effective use of the anisotropic conductive film.
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the invention of Angle so as to deposit the ACF onto the area pads of the integrated circuit rather than on the bumps of the terminal as taught by Chen and the alternative embodiments of Angle. One of ordinary skill in the art would recognize that determining where to deposit an ACF electrically conducting two structures together between the two structures would be well within the skill of one of ordinary skill in the art based on the suitability for the intended final application and that there are only so many options for where to deposit an ACF material between two structures being electrically connected to each other and therefore it would be a routine matter to one of ordinary skill in the art to choose to deposit the ACF on the area pads on the integrated circuit as claimed in light of Angle and Chen; the obvious advantage being that this would ensure that the ACF is not misaligned with the array of pads of the integrated circuit while the ACF would still effectively electrically connect the area pads of the integrated circuit to the bumps of the terminal, thereby reducing potential connection failures to the IC as would be generally understood by one of ordinary skill in the art.
As per claim 32, Angle and Chen disclose the elements of the current invention as detailed above with respect to claim 32, but Angle does not explicitly disclose that each shank of the plurality of shanks (see 112c/312c in Fig 1A and 3-4 respectively) includes a plurality of electrodes mounted therein. However, it is well-known in the art to provide shank portions of an implantable portion with plural electrodes in order in increase the available electrodes to increase the number of signals that can be received and/or recorded by the probe, and therefore it would have been an obvious choice for one of ordinary skill in the art to choose to have shank portions with plural electrodes mounted therein.
Further, Masmanidis discloses a similar neural recording probe and method of making the neural recording probe that uses a ACF film (see anisotropic conducting film 602 in Fig 6) for assembly, wherein the implantable portion of the neural probe includes multiple shank portions each with plural electrodes mounted therein to allow for any suitable number of electrodes to be used that advantageously can separately address sites at different locations including front and back sides of the shanks (see Fig 3, 5-7, 11, 14-15, 18-19; see abstract; see Para 0005-0006, 0037-0038, 0042)
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the above combination of Angle and Chen so as to modify the shank portions to each include plural electrode mounted therein as taught by Masmanidis. One of ordinary skill in the art would recognize that it is well-known in the art to provide shank portions of an implantable portion with plural electrodes in order to in increase the available electrodes to increase the number of signals that can be received and/or recorded by a certain number of shanks, and that choosing the number of electrodes to provide on a shank would be well within the skill of one of ordinary skill in the art based on the suitability for the intended final application, therefore it would be a routine matter to one of ordinary skill in the art to choose to have plural electrodes mounted on each shank as taught by Masmanidis; the obvious advantage being that the plural electrodes would allow for any suitable number of electrodes to be used that could advantageously separately address sites at different locations including front and back sides of the shanks (Masmanidis: Para 0038, 0042)
As per claim 33, Angle, Chen, and Masmanidis discloses the elements of the current invention as detailed above with respect to claim 32. Angle further discloses that the number of electrical conductors (see wires 612 with conductive cores 316 in Fig 3-4) in the cable can be 1000, 10000, or 1000000 wires, greater than 1000000 wires, or any number between the aforementioned ranges (Para 0049) and with each of the conductors electrically connected to a separate one of the bumps (see connection pads 317 in Fig 3, and substrate wire bumps 319 in Fig 4, and connection pads 1417 in Fig 14 Part A that are connected to the wires respectively), and wherein the integrated circuit includes a separate one of the area pads for each of the bumps and a separate one of the active circuits located underneath each separate area pad (see chip 620 with m x n two dimensional array of bond pads 622 corresponding to the number of wires in the wire bundle substrates in Fig 6; Para 0051 and 0074; it is inherent and/or obvious that integrated circuits include buried circuits which are overlayed and connected to the pads of the integrated circuits).
As per claims 34 and 39, Angle, Chen, and Masmanidis discloses the elements of the current invention as detailed above with respect to claims 30 and 32 respectively. Angle further discloses that each bump of the plurality of bumps includes a projection portion (see projection portions of connection pads 317 in Fig 3, substrate wire bumps 319 in Fig 4, substrate wire bumps 1219 in Fig 12, and connection pads 1417 in Fig 14 Part A) projecting from a bottom surface of the terminal, and wherein the method further comprises electroplating the projection portion of each of the plurality of bumps to form an electroplated projection portion of each of the plurality of bumps (see electroplated solder caps 1219a in Fig 12).
As per claims 35 and 40, Angle, Chen, and Masmanidis discloses the elements of the current invention as detailed above with respect to claims 34 and 39 respectively. Angle further discloses that the electroplated projection portion is formed by depositing a first metal (see solder caps 1219a in Fig 12) onto the projection portion of each of the plurality of bumps.
As per claims 36 and 41, Angle, Chen, and Masmanidis discloses the elements of the current invention as detailed above with respect to claims 35 and 40 respectively. Angle further discloses that the first metal is an other conductive metal (see solder caps 1219a in Fig 12 comprising SnAg or SnAg alloy according to Para 0080 and 0086; also see Fig 7 and 15-16 in which bumps are made of a conductive pillar made of Cu, Au, Ag, Pt, Pd, etc. and a solder cap made of SnAg or SnAg alloy according to Para 0080).
As per claims 37 and 42, Angle, Chen, and Masmanidis discloses the elements of the current invention as detailed above with respect to claims 35 and 40 respectively. Angle does not explicitly disclose depositing a first metal layer of the projection portion on the terminal followed by depositing a second metal onto the first metal layer for each of the plurality of bumps. However, it would be within the skill of one of ordinary skill in the art to determine where to deposit metal layers and how many metal layers to use for bumps provided to electrically connect two structures. Further, Angle discloses different embodiments in which deposited metal bumps are provided on the terminal or both the terminal and the integrated circuit (see Fig 7-8, 10, and 15-16 that shows the deposited bumps provided on the integrated circuit; see Fig 11-12 and 14 that shows the deposited bumps provided on both the terminal and the integrated circuit) including embodiments in which the bumps are provided on the integrated circuit that are made by electroplating a first layer (see conductive pillars 728 in Fig 7D, conductive pillars 1528 in Fig 15,and conductive pillars 1628 in Fig 16) followed by electroplating a second layer (see solder caps 726a in Fig 7D, solder caps 1526a in Fig 15, solder caps 1626a in Fig 16) on the second layer to form the bumps of the integrated circuit, wherein the second layer can be made of a lower melting point material to wet the other contact for enhanced connection with the second layer, and/or to allow for the first and/or second layer to be used for alignment (see Para 0080 and 0098-0100).
At the time the application was filed, it would have been obvious to one of ordinary skill it the art to modify the above combination of Angle, Chen, Masmanidis so as to deposit a first metal layer onto the projection portion to form a first metal layer followed by depositing a second metal onto the first metal layer to form each of the bumps as taught by the different embodiments of Angle. One of ordinary skill in the art would recognize that determining the location of deposited layers of a bump and determining the number of layers used to form the bump would be well within the skill of one of ordinary skill in the art based on the suitability for the intended final application and that there are only so many options for where and how many metal layers to deposit between the terminal and the integrated circuit and therefore it would be a routine matter to one of ordinary skill in the art to choose to deposit two layers for forming the bumps as taught by Angle and to choose to deposit the bumps onto the terminal as also taught by Angle; the obvious advantage being that this would allow for the second layer to be made of a lower melting point material to wet the other contact for enhanced connection with the second layer, and/or to allow for the first and/or second layer to be used for alignment (Angle: Para 0080 and 0098-0100).
As per claims 38 and 43, Angle, Chen, and Masmanidis discloses the elements of the current invention as detailed above with respect to claims 37 and 42 respectively. Angle further discloses that the second metal is an other conductive metal (see solder caps 1219a in Fig 12 comprising SnAg or SnAg alloy according to Para 0080 and 0086).
Response to Arguments
Applicant’s arguments, see Applicant’s remarks, filed 11/17/2025, with respect to the rejection(s) of claim(s) 30 and 32 under AIA 35 U.S.C. 103 as being unpatentable over US 2017/0290521 to Angle in view of US 2005/0127936 to Chen have been fully considered and are persuasive in light of the claim amendments filed 11/17/2025. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20090177144 to Masmanidis (see above 103 rejection for specific details).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joshua D. Anderson, whose telephone number is (571) 270-0157. The examiner can normally be reached from Monday to Friday between 7 AM and 1 PM Arizona time.
If any attempt to reach the examiner by telephone is unsuccessful, the examiner’s supervisor, Thomas Hong, can be reached at (571) 272-0993.
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/JOSHUA D ANDERSON/
Examiner, Art Unit 3729
/THOMAS J HONG/Supervisory Patent Examiner, Art Unit 3729