DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed January 8th, 2026. Claims 27-45 are pending, of which claims 27-45 are currently rejected.
Response to Arguments
The claims filed January 8th, 2026 have been entered. Claims 27-45 remain pending in the application. Applicant’s amendments to the Claims have overcome each and every objection, previously set forth in the Office Action mailed October 8th, 2025.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 8th, 2026 has been entered.
Claim Objections
Applicant has amended the claims to address the informalities. Therefore, the previous objections to the Claims have been withdrawn. One new claim objection has been made. See Claim Objections.
Prior Art Rejections
Applicant’s arguments regarding the previously cited art have been fully considered and are persuasive. New grounds of rejection have been made by Examiner that are necessitated by the amendments. See Claim Rejections - 35 USC § 103.
Double Patenting
The non-statutory double patenting rejection as set forth in the previously in the Office Action mailed October 8th, 2025 has been withdrawn in response to the terminal disclaimer submitted by Applicant.
Claim Objections
Claim 37 is objected to because of the following informalities;
On line 7 “each of the first and the second VDC circuitry having a respective register array” should be “an entropic output bit” should be “each of the first and the second VDC circuitry has a respective register array”.
Claims 38-45 are objected to based on their dependence upon claim 37 which is objected to.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over by Altera (“Advanced Synthesis Cookbook”), included in the IDS filed on 02/15/2022 (hereinafter “Altera”), in view of R. Ye et al. (“Reconfiguration-Oriented Approximate Adder Design and Its Application”, 2013) (hereinafter “Ye”), further in view of Pham et al. (7268587) (hereinafter “Pham”).
Altera teaches:
A system on chip (SOC) to generate a nondeterministic data stream, comprising:
a first variable delay chain (VDC) circuitry having a first delay chain and a second delay chain (Altera: Page 14-3 Figure 14-2; Page 14-4 Line 1-2 "When the clear is released on the carry chains registers, the decoded "1" races down both chains."), each of the first and the second delay chains further comprising a respective register array (Figure 14-2 Register bank) and an adder array (Figure 14-2, unlabeled carry chain as indicated below),
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defined by separate adder array calibration settings (Altera: Pg. 14-4 Fig. 14-4 shows calibration separately for each of the carry chains), the first VDC circuitry to provide a first race output bit and a second race output bit (Altera: 14-4 Line 2 "The latches detect which chain produced a "1" first."; Page 14-5 Figure 14-5 Table showing first output bit and second output bit, along with latch output);
a race condition latch circuitry to select a race output winner from the first and second race output bits (Altera: Page 14-3 Figure 14-3 Output Latches; Page 14-5 Figure 14-5 showing output bits and corresponding behavior of latch circuitry); and
a bit logic circuitry to receive the selected race output winner bit and provide an output bit corresponding to the selected race output (Altera: Page 14-5 Figure 14-5 showing output bit corresponding to the selected race output winner bit).
Altera does not explicitly teach the delay chains being of different lengths or these different lengths of the first and second VDC circuitries being configurable.
However, Ye teaches configuration of adder chains including configurability of bit-length and therethrough the length of the carry chain itself (Ye: Pg. 49 Col. 2 Section 3.1).
It would have been obvious before the effective filing date of the claimed invention to combine the configurable length of adder chains as taught by Ye with the first and second VDC circuitry, latch circuitry, and bit logic circuitry as taught by Altera as both teachings are directed towards FPGA implementations. One with ordinary skill in the art would be motivated to combine the teachings because this would increase the flexibility of the functionality of the circuitry, and therethrough increase entropy (Ye: Pg. 49 Col. 2 Section 3.1).
Altera in view of Ye does not explicitly teach the delay chains being of different lengths.
However, Pham teaches delay chains being of different lengths (Pham: Col. 1 Lines 7-10).
It would have been obvious before the effective filing date of the claimed invention to combine the differing delay chain lengths of Pham with the first and second VDC circuitry, latch circuitry, and bit logic circuitry and configurable bit length as taught by Altera in view of Ye as all teachings are directed towards FPGA implementations. One would be motivated to combine the teachings because Pham provides improved routing flexibility of output signals (Pham: Col. 41 Lines 34-37) which can enhance entropy.
In combining Altera, Ye, and Pham, the VDC circuitries, latch circuitry, and bit logic circuitry would be present as recited in the claims, and the VDC circuitries would be separately calibratable including calibration of the delay chain lengths, and having the delay chain lengths the same or different.
Therefore, Altera in view of Ye in view of Pham teaches:
A system on chip (SOC) to generate a nondeterministic data stream, comprising:
a first variable delay chain (VDC) circuitry having a first delay chain with a first delay chain length and a second delay chain with a second delay chain length that is configured to be controllably different from or the same as the first chain delay length, each of the first and the second delay chains further comprising a respective register array and an adder array, wherein the first and second delay chain lengths are defined by separate adder array calibration settings, the first VDC circuitry to provide a first race output bit and a second race output bit;
a race condition latch circuitry to select a race output winner from the first and the second race output bits; and
a bit logic circuitry to receive the selected race output winner bit and provide an output bit corresponding to the selected race output.
Claims 28 and 32-36 are rejected under 35 U.S.C. 103 as being unpatentable over Altera in view of Ye in view of Pham further in view of Yang et al. (A complementary architecture for high-speed true random number generator”) (hereinafter “Yang”).
Regarding claim 28, while Altera in view of Ye in view of Pham teaches the SOC of claim 27, Altera in view of Pham does not explicitly teach a register to receive and store output, a concatenator to interleave the different outputs or entropy extraction circuitry.
However, Yang teaches:
a register to receive and store output bits corresponding to a plurality of selected race outputs, the register to provide an output bit stream periodically (Yang: Page 249 Fig. 3 Output bits “1011” and “1100” from sampling register at input of P2S; Page 249 Lines 20-28 “At this stage, it samples the output of the exclusive-or (XORed) output of each step from the TRNG delay chain… Followed by the sampling register, a parallel to serial converter is designed to transfer the two-bit random number into one bit stream.”);
a concatenator to interleave different output bit streams to provide an entropic output bit corresponding to a plurality of selected race outputs (Yang: Page 249 Fig. 3 Sampling register obtains output bits from different streams and outputs its own bit streams “1011” and “1100”); and
an entropy extraction circuitry to convert the entropic output bit signal into a nondeterministic data stream (Yang: Page 249 Fig. 3 P2S interleaves outputs from the different race outputs, creating an interleaved signal; Page 249 Lines 25-27 “Followed by the sampling register, a parallel to serial converter is designed to transfer the two-bit random number into one bit stream.”; Page 249 Lines 30-33 “At the same time, since the final one bit data stream has included two kinds of nonuniformity information…the random entropy has been optimized eventually.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the register and concatenator as taught by Yang with the variable delay chain circuitry and latch circuitry as taught by Altera in view of Ye in view of Pham as all teachings are directed towards computation through carry/delay chains. One with ordinary skill in the art would be motivated to combine the teachings so that the speed of random number generation is increased (Yang: Page 249 Lines 29-30 “After that, a doubled speed random data stream is achieved.”).
Regarding claim 32, Altera in view of Ye in view of Pham in view of Yang further teaches:
The SOC of claim 32, wherein the concatenator alternatingly concatenates serial race output bits (Yang: Page 249 Fig. 3 Sampling register obtains output bits from different streams and outputs its own bit streams “1011” and “1100”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the register and concatenator as taught by Yang with the variable delay chain circuitry and latch circuitry as taught by Altera in view of Ye in view of Pham as all teachings are directed towards computation through carry/delay chains. One with ordinary skill in the art would be motivated to combine the teachings for at least the same reasons as discussed above in claim 28.
Regarding claim 33, Altera in view of Ye in view of Pham in view of Yang further teaches:
The SOC of claim 32, further comprising an online health test and calibration circuitry to identify noise in the partially entropic output bit and to calibrate at least one of the first delay chain and a second delay chain to remediate the noise (Altera: Page 14-5 Lines 1-6 “Together the race and adjustment circuits generate a series of “first” signals which exhibit noise-based instability…The signals are discarded entirely during delay adjustments as well as when consecutive trials produce the same result.”; Page 14-4 Figure 14-4 shows that chain A and/or B are calibrated or adjusted when either of them have shown the same or repeating results over a number of trials).
Regarding claim 34, Altera in view of Ye in view of Pham in view of Yang teaches:
The SOC of claim 28, further comprising a delay chain calibration circuitry to induce calibration bits to one of the VDC circuitry (Altera: Page 14-5 Lines 20-21 “Increasing the number of calibration bits creates a higher chance of finding an unstable setting in return for a modest increase in area cost.”) to synchronize response time between the first and second delay chains (Altera: Page 14-5 Lines 7-8 “Note that if the delay becomes predictable the output circuitry stops generating bits. If the stability persists, then the adjustment state machine switches to another setting.”; Page 14-4 Lines 20-24 “The chain_delay_adjust example iterates through settings and counts the number of A first and B first outputs over 255 trials. If the results are consistent, it changes the setting and reevaluates. For unstable settings it makes not adjustment but continues to evaluate.”).
Regarding claim 35, Altera in view of Ye in view of Pham in view of Yang teaches:
The SOC of claim 28, wherein the race condition latch circuitry (Altera: 14-3 Latch circuitry) is configured to select a race output winner as a function of the duty cycle for the first and second delay chains (Page 14-3 Lines 11-13 “Two of these variable delay chains drive the latch circuit shown in Figure 14-3. The output registers use the same clock as the chain input registers. The circuit is intended to meet timing for one clock cycle despite containing latches on the critical path.”).
Regarding claim 36, Altera in view of Ye in view of Pham in view of Yang teaches:
The SOC of claim 28, wherein the concatenator interleaves different output bit streams by alternatingly using output bits from different circuitries (Yang: Page 249 Fig. 3 Sampling register obtains output bits from different streams and outputs its own bit streams “1011” and “1100”).
The motivation to combine with respect to claim 28 applies equally to claim 36.
Claims 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Altera in view of Ye in view of Pham in view of Yang further in view of Lazich et al. (8990276) (hereinafter “Lazich”).
Regarding claim 29, while Altera in view of Ye in view of Pham in view of Yang teaches each delay chain having a respective register array (Altera: Figure 14-2 register bank) and adder chain (Altera: Figure 14-2 carry chain) and each pair of chains outputting its respective race output bit (Altera: Figure 14-5 showing output bits and corresponding behavior of latch circuitry), Altera in view of Ye in view of Pham in view of Yang does not explicitly teach a third and fourth delay chain.
However, Lazich teaches:
a second VDC circuitry having a third delay chain and a fourth delay chain (Lazich: Col. 19 Lines 49-54 “FIG. 8b shows a first interconnection (chain pair) 820 of a 4×4 matrix of delay elements, in which a first chain 821 and a second chain 822 are formed and a second interconnection (chain pair) 825 in which a first chain 826 and a second chain 827 are formed, one chain being formed by applying one code word of the corresponding selection code for chain pairs…”; Fig. 15 Element 1522 comparator yielding outputs from chain; Col. 30 Lines 34-35 “… by a numeric comparator 1522 on the one hand and therefore generates one bit…”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the third and fourth chain as taught by Lazich with the SOC as taught by Altera in view of Ye in view of Pham in view of Yang as all teachings are directed towards computation through carry/delay chains. One with ordinary skill in the art would be motivated to combine the teachings because the bits generated by the two chain pairs are completely uncorrelated (Lazich: Col. 18 Lines 54-55)., therefore allowing for more entropy.
Regarding claim 30, Altera in view of Ye in view of Pham in view of Yang further in view of Lazich teaches:
The SOC of claim 29 wherein each of the first and second VDC circuits has a chain length defined by the number of adders in each respective array (Altera: Page 14-5 Lines 11-12 “The chain_delay_rand example file instantiates the race circuit using 32-bit chains with 16 delay selections each, an adjustment state machine, and an output filter.”).
Regarding claim 31, while Altera in view of Ye in view of Pham in view of Yang in view Lazich further teaches a first delay chain having a length of 2 (L = 2), and the second delay chain having a chain length 4 (2+2= 4; 4 as L+N, 2 as L, 2 as N), 2 = L and 2 = N, and 2 and 2 are non-consecutive prime numbers (Pham: Col. 2 Lines 56-60).
The motivation to combine with respect to claim 27 applies equally to claim 31.
Claims 37-38, and 43-45 are rejected under 35 U.S.C. 103 as being unpatentable over Altera in view of Ye in view of Pham in view of Lazich, further in view of Stewart (US 2013/0022203 A1).
With regards to claim 37, Altera teaches:
A method to generate a nondeterministic data stream, comprising:
generating a first race output bit from a first variable delay chain (VDC) circuitry (Altera: Page 14-4 Line 2 "The latches detect which chain produced a "1" first."; Page 14-5 Figure 14-5 Table showing first output bit and second output bit, along with latch output) and generating a second race output bit form a second VDC circuitry (Altera: Pg. 14-5 Fig. 14-5 Table showing first output bit and second output bit from the carry chains; Pg. 14-3 Fig. 14-2 shows the first and second carry chains as shown below) based on independent calibration settings for each of the first and second variable delay chains (Altera: Pg. 14-4 Fig. 14-4 shows state machine for calibration, calibration settings separate for each of the first and second chains labeled “A” and “B”),
wherein each of the first and second VDC circuitry having a respective register array (Altera: Page 14-3 Fig. 14-2 Register bank) and an adder array circuitry (Altera: Page 14-3 Fig. 14-2 unlabeled carry chain as indicated below)
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selecting a race output winner from among the first and the second race output bits at a race condition latch circuitry (Altera: Page 14-3 Figure 14-3 Output Latches; Page 14-5 Figure 14-5 showing output bits and corresponding behavior of latch circuitry);
providing, at a bit logic circuitry, an output bit corresponding to the selected race output winner bit (Altera: Page 14-5 Figure 14-5 showing output bit corresponding to the selected race output winner bit).
Altera does not explicitly teach:
with a first delay chain length
with a second delay chain length that is configured to be controllably different from or the same as the first delay chain length
independent calibration settings for each of the first and second variable delay chains,
generating a second race output bit from a second VDC circuitry;
storing output bits corresponding a plurality of selected race outputs at a shift register and providing an output bit stream periodically from the shift register;
interleaving different output bit streams from a plurality of shift registers to provide an entropic output bit corresponding to the selected race outputs; and
converting the entropic output bit signal into a nondeterministic data stream at an entropy extraction circuitry.
However, Ye teaches configuration of adder chains including configurability of bit-length and therethrough the length of the carry chain itself (Ye: Pg. 49 Col. 2 Section 3.1).
The motivation to combine with respect to claim 27 applies equally to claim 37.
Altera in view of Ye does not explicitly teach:
with a first delay chain length
with a second delay chain length that is configured to be controllably different from or the same as the first delay chain length
independent calibration settings for each of the first and second variable delay chains,
generating a second race output bit from a second VDC circuitry;
storing output bits corresponding a plurality of selected race outputs at a shift register and providing an output bit stream periodically from the shift register;
interleaving different output bit streams from a plurality of shift registers to provide an entropic output bit corresponding to the selected race outputs; and
converting the entropic output bit signal into a nondeterministic data stream at an entropy extraction circuitry.
However, Pham teaches delay chains being of different lengths (Pham: Col. 1 Lines 7-10).
The motivation to combine with respect to claim 27 applies equally to claim 37.
Altera in view of Ye in view of Pham does not explicitly teach:
generating a second race output bit from a second VDC circuitry;
storing output bits corresponding a plurality of selected race outputs at a shift register and providing an output bit stream periodically from the shift register;
interleaving different output bit streams from a plurality of shift registers to provide an entropic output bit corresponding to the selected race outputs; and
converting the entropic output bit signal into a nondeterministic data stream at an entropy extraction circuitry.
However, Lazich teaches:
generating a second race output bit from a second VDC circuitry (Lazich: Col. 19 Lines 49-54 “FIG. 8b shows a first interconnection (chain pair) 820 of a 4×4 matrix of delay elements, in which a first chain 821 and a second chain 822 are formed and a second interconnection (chain pair) 825 in which a first chain 826 and a second chain 827 are formed…; Fig. 15 Element 1522 comparator yielding outputs from chain; Col. 30 Lines 34-35 “… by a numeric comparator 1522 on the one hand and therefore generates one bit…”).
The motivation to combine with respect to claim 29 applies equally to claim 37.
Altera in view of Ye in view of Pham in view of Lazich does not explicitly teach:
storing output bits corresponding a plurality of selected race outputs at a shift register and providing an output bit stream periodically from the shift register;
interleaving different output bit streams from a plurality of shift registers to provide a entropic output bit corresponding to the selected race outputs; and
converting the entropic output bit signal into a nondeterministic data stream at an entropy extraction circuitry.
However, Stewart teaches:
storing output bits corresponding a plurality of selected race outputs at a shift register and providing an output bit stream periodically from the shift register (Stewart: ¶ 0012 “The linear feedback shift registers [or LFSRs] are seeded with values from a plurality of oscillators and are updated asynchronously.”; ¶ 0032 “Returning to FIG. 3, the linear feedback shift registers update based on the comparison, as illustrated at 310. Each linear feedback shift register outputs a pseudorandom sequence.”);
interleaving different output bit streams from a plurality of shift registers to provide a entropic output bit corresponding to the selected race outputs (Stewart: ¶ 0019 “For example, the mixing function can describe an ordered selection from bit positions of the linear feedback shift registers. A number can be generated by concatenating bit values in the described ordered bit positions of the linear feedback shift registers.”); and
converting the entropic output bit signal into a nondeterministic data stream at an entropy extraction circuitry (Stewart: Fig. 2 Element 214 Mixer taking values from LFSR 0 and LFSR 1 in order to create a data stream/number; ¶ 0012 “The device also includes a mixing module that mixes bit values selected from the linear feedback shift registers in accordance with a mixing function to generate a number.”; ¶ 0037 “The entropy synchronizer and balancer module 216 can derive an entropy value from the value of the oscillator 218. A mixing function can be selected from a set of mixing functions based on the entropy value. The selected mixing function is applied by the mixer 214 to the linear feedback shift registers 202 and 204.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the linear feedback shift registers, the mixer, and the entropy extraction as taught by Stewart with the SOC as taught by Altera in view of Ye in view of Pham in view of Lazich as all teachings are directed towards digital design. Stewart enhances the random number generation of Altera in view of Ye in view of Pham in view of Lazich by including the linear feedback shift registers which can be updated non-deterministically and independently of other linear feedback shift registers (Stewart: ¶ 0017), further allowing for increased uniqueness between components of the system, in order to augment entropy further.
Therefore, Altera in view of Ye in view of Pham in view of Lazich in view of Stewart teaches:
A method to generate a nondeterministic data stream, comprising:
generating a first race output bit from a first variable delay chain (VDC) circuitry with a first delay chain length and generating a second race output bit from a second VDC circuitry with a second delay chain length that is configured to be controllably different from or the same as the first delay chain length based on independent calibration settings for each of the first and second variable delay chains, wherein each of the first and the second VDC circuitry having a respective register array and an adder circuitry;
selecting a race output winner from among the first and the second race output bits at a race condition latch circuitry;
providing, at a bit logic circuitry, an output bit corresponding to the selected race output winner bit;
storing output bits corresponding to a plurality of selected race outputs at a shift register and providing an output bit stream periodically from the shift register;
interleaving different output bit streams from a plurality of shift registers to provide an entropic output bit corresponding to the selected race outputs; and
converting the entropic output bit signal into a nondeterministic data stream at an entropy extraction circuitry.
Regarding claim 38, Altera in view of Ye in view of Pham in view of Lazich in view of Stewart further teaches:
The method of claim 27, further comprising periodically evaluating the output bits corresponding to the selected race output winner bits at an online health test circuitry to determine a noise level (Altera: Page 14-5 Lines 1-6 “Together the race and adjustment circuits generate a series of “first” signals which exhibit noise-based instability. Certain outcomes are more likely than others… The signals are discarded entirely during delay adjustments as well as when consecutive trials produce the same result.”; Figure 14-4 shows that chain A and/or B are calibrated when either of them have shown the same results over a number of trials.”).
Regarding claim 43, Altera in view of Ye in view of Pham in view of Lazich in view of Stewart further teaches:
The method of claim 37, further comprising alternatingly interleaving output bit streams corresponding to a plurality of VDC circuitry outputs (Stewart: ¶ 0019 “For example, the mixing function can describe an ordered selection from bit positions of the linear feedback shift registers. A number can be generated by concatenating bit values in the described ordered bit positions of the linear feedback shift registers.”).
The motivation to combine with respect to claim 37 applies equally to claim 43.
Regarding claim 44, Altera in view of Ye in view of Pham in view of Lazich in view of Stewart further teaches:
The method of claim 37, wherein selecting a race output winner further comprises selecting a race output winner as a function of the duty cycle for the first and the second delay chains (Altera: Page 14-3 Lines 11-13 “Two of these variable delay chains drive the latch circuit shown in Figure 14-3. The output registers use the same clock as the chain input registers. The circuit is intended to meet timing for one clock cycle despite containing latches on the critical path.”).
Regarding claim 45, Altera in view of Ye in view of Pham in view of Lazich in view of Stewart further teaches:
The method of claim 37, wherein interleaving different output bit streams from a plurality of shift registers further comprises alternatingly using output bits from different circuitries (Stewart: ¶ 0019 “For example, the mixing function can describe an ordered selection from bit positions of the linear feedback shift registers. A number can be generated by concatenating bit values in the described ordered bit positions of the linear feedback shift registers.”).
The motivation to combine with respect to claim 37 applies equally to claim 45.
Claims 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Altera in view of Ye in view of Pham in view of Lazich, in view of Stewart, further in view of Saito (US 2007/0156798 A1).
Regarding claim 39, while Altera in view of Ye in view of Pham in view of Lazich in view of Stewart teaches the method of claim 38, Altera in view of Ye in view of Pham in view of Lazich in view of Stewart does not explicitly teach the noise level being compared to a predefined threshold.
However, Saito teaches:
comparing the noise level with a predefined noise threshold (Saito: ¶ 0036 “… a block indicated by the reference code 14 is an comparator for comparing an amplified thermal noise signal with a predetermined threshold and outputting the comparison result in the form of a pulse P.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the noise level threshold comparison as taught by Saito with the SOC as taught by Altera, Ye, Pham, Lazich and Stewart as all teachings are directed towards digital design. Saito enhances the random number generation of Altera, Ye, Pham, Lazich and Stewart by ensuring that the random bit streams outputted are truly random as they are based on the noise itself in order to enhance entropy (Stewart: ¶ 0036 “Thus, the output pulse P from the comparator serves as a random pulse based on the randomly occurring thermal noise.”).
Regarding claim 40, Altera in view of Ye in view of Pham in view of Lazich in view of Stewart in view of Saito further teaches:
The method of claim 39, calibrating at least one of the register arrays to substantially increase the noise level to increase randomness (Altera: Page 14-5 Lines 7-8 "Note that if the delay becomes predictable the output circuitry stops generating bits. If the stability persists, then the adjustment state machine switches to another setting."; Page 14-5 Lines 20-21 "Increasing the number of calibration bits creates a higher chance of finding an unstable setting [or a setting with increased noise] in return for a modest increase in area cost." Page 14-4 Lines 20-24 “The chain_delay_adjust example iterates through settings and counts the number of A first and B first outputs over 255 trials. If the results are consistent, it changes the setting and reevaluates. For unstable settings it makes no adjustment but continues to evaluate. The adjusting output notifies the output filter when the circuit is experimenting with settings and is therefore predictable.").
Claim 41 is rejected under 35 U.S.C. 103 as being unpatentable over Altera in view of Ye in view of Pham in view of Lazich, in view of Stewart, in view of Saito, further in view of Parker et al. (US 2018/0293053 A1) (hereinafter “Parker”).
Altera in view of Pham in view of Ye, in view of Lazich, in view of Stewart, in view of Saito teaches the method of claim 40 as well as the use of calibration bits that are inputted to the register array of the first or second VDC circuits for calibration (Altera: Figure 14-4 showing the process of calibration; Page 14-5 Lines 20-21 "Increasing the number of calibration bits creates a higher chance of finding an unstable setting in return for a modest increase in area cost."; Lazich: Col 19 Lines 49-54 " FIG. 8b shows a first interconnection (chain pair) 820 of a 4x4 matrix of delay elements, in which a first chain 821 and a second chain 822 are formed and a second interconnection (chain pair) 825 in which a first chain 826 and a second chain 827 are formed, one chain being formed by applying one code word of the corresponding selection code for chain pairs...").
Altera in view of Ye, in view of Pham, in view of Lazich, in view of Stewart, in view of Saito does not explicitly teach this calibration occurring during an operation mode.
However, Parker teaches:
continually providing calibration during an operation mode (Parker: ¶ 0053 “Alternatively, the frequency of the deterministic feedback loop and/or step size of the adjustment voltage Vadj may be adjusted dynamically during operation of the circuit 500, for example based on changing conditions.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the continual calibration as taught by Parker with the SOC as taught by Altera, Ye, Pham, Lazich, Stewart and Saito as all teachings are directed towards digital design. Parker enhances the random number generation of Altera, Ye, Pham, Lazich, Stewart and Saito by accounting for changing conditions in real time (Parker: ¶ 0053 “… may be adjusted dynamically during operation of the circuit 500, for example based on changing conditions.”) in order to continue generating random data streams.
Claim 42 is rejected under 35 U.S.C. 103 as being unpatentable over Altera in view of Ye, in view of Pham in view of Lazich, in view of Stewart, in view of Saito, further in view of Grybos et al (US 2019/0173545 A1) (hereinafter “Grybos”).
Altera in view of Ye in view of Pham in view of Lazich in view of Stewart in view of Saito teaches the method of claim 40 as well as calibration in order to increase the noise level of the VDC circuits (Altera: Figure 14-4 showing the process of calibration; Page 14-5 Lines 20-21 "Increasing the number of calibration bits creates a higher chance of finding an unstable setting in return for a modest increase in area cost."; Lazich: Col 19 Lines 49-54 " FIG. 8b shows a first interconnection (chain pair) 820 of a 4x4 matrix of delay elements, in which a first chain 821 and a second chain 822 are formed and a second interconnection (chain pair) 825 in which a first chain 826 and a second chain 827 are formed, one chain being formed by applying one code word of the corresponding selection code for chain pairs...”). Altera in view of Ye in view of Pham in view of Lazich in view of Stewart in view of Saito does not explicitly teach calibration by affecting a carry bit propagation.
However, Grybos teaches:
further comprising affecting a carry bit propagation (Grybos: ¶ 0071 Concurrently with generating the plurality of output signals, performing a calibration operation is also performed on the one or more [VDC circuits]. The calibration operation includes: … injecting the calibration signal [or bits] into the one or more [VDC circuits]; and receiving the injected calibration signal [or bits] after propagating through a portion of the [VDC circuits]. A comparison is performed of the injected calibration signal to the calibration signal after propagating through the portion of the [VDC circuit], and a calibration operation is performed on the [VDC circuits] based on the comparison.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine, with reasonable expectation of success, the calibration via bit propagation as taught by Grybos with the SOC as taught by Altera, Ye, Pham, Lazich, Stewart and Saito as all teachings are directed towards digital design. The improvement of Grybos lies increasing efficiency in the calibration process (Grybos: ¶ 0018).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151