Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the applicant's communication filed on 10/28/2025. In virtue of this communication, claims 1-2, 6-7, 10-11, 16 filed on 10/28/2025 are currently pending in the instant application.
Claims 1, 10 have been amended, without adding a new subject matter.
Claims 3-5, 8-9,12-14, 17-19 have been cancelled.
Response to Arguments
Applicant's arguments filed on 10/08/2025 with respect to claim(s) 1, 2, 6, 7, 10, 11, 16 have been considered.
With regard to prior at rejection, Applicant has not provided any argument regarding the cited prior art and how it would not disclose any portion of submitted claims.
Furthermore, regarding the amended section of independent claims 1 and 10, disclosing “based on training with a training data set”, the cited prior art Nava page 536 and 537, Col. 2 discloses the principle component analysis (PCA) digit image test dataset must be processed by applying the first 5 steps, but using calculated from the training set. Given the new Eigen-data set, two Bayesian algorithms, linear and quadratic discriminant classifiers must be trained and tested. The next step will use the linear and quadratic discriminant classifiers using more than 3 principal components from X matrix. Our classification process, for linear and quadratic discriminants, was trained in the complete training data set and tests the performance in the test data set.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-2, 6-7, 10-11, 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Charlos Fabian Nava (US 2017/0372158), hereinafter Nava (158), in view of Nava et al "OCR for Unreadable Damaged Characters on PCBs Using Principal Component Analysis and Bayesian Discriminant Functions," 2015 International Conference on Computational Science and Computational Intelligence (CSCI),2015, further in view of Chen et al. (KR 20190067839.)
As per claim 1, A packaged module processing system comprising:module processing system configured to process a panel having an array of units that are joined together, each unit including structure and a surface, the panel further including a surface outside of the array of units” (Nava(158), discloses ¶[0009] discloses the present disclosure relates to a system for processing printed circuit boards. The system includes a first production system configured to fabricate a plurality of printed circuit boards, with each printed circuit board including a plurality of characters imprinted thereon to provide information about the printed circuit board. The system further includes a character recognition system configured to monitor at least some of the printed circuit boards. The character recognition system includes an imaging component configured to obtain a digital image of the characters on a selected printed circuit board. ¶[0012] discloses Each printed circuit board can be implemented as a packaging substrate panel having an array of modules joined together, such that the joined modules become the individual modules upon singulation by the second production system. Further ¶[0034] and [0036], further see figures 3-5 )
“and character recognition system configured to obtain a digital image of a character imprinted on the surface of each of the array of units of the panel,” (Nava (158) ¶[0037-0038] discloses algorithm to extract features of damaged, unreadable and/or incomplete numerical digit characters from images on printed board circuits (PCBs).)
“the character recognition system further configured to perform a pattern matching process for the digital image of the character” (Nava (158) ¶[0041] discloses using one of the foregoing OCR techniques (e.g., the pattern matching technique) can be utilized. In such a pattern matching technique, a vision system reads identification characters on printed circuits boards (PCBs), where the characters provide processing information such as lot integrity and machine control. )
However Nava (158) is silent on the following which would have been obvious in view of Nava from similar filed of endeavor “the pattern matching process including a principal component analysis to extract more than three principal components,” (Nava, Abstract, discloses having optical character recognition on the principal component analysis extracted features from the image on printed board circuit (PCBs) used for pattern matching. Page, 536 and 537, Col. 2 disclose The principle component analysis (PCA) digit image test dataset must be processed by applying the first 5 steps, but using calculated from the training set. Given the new Eigen-data set, two Bayesian algorithms, linear and quadratic discriminant classifiers must be trained and tested. The next step will use the linear and quadratic discriminant classifiers using more than 3 principal components from X matrix. Our classification process, for linear and quadratic discriminants, was trained in the complete training data set and tests the performance in the test data set. Further Fig. 7 and related paragraphs.)
“the pattern matching process further including linear Bayesian discriminant function to classify and find a correct character that corresponds to the principal components based on training with a training dataset.” (Nava, Abstract, discloses computing linear and quadratic Bayesian discriminant function to classify and find the correct character that correspond to the features. Page, 536 and 537, Col. 2 disclose The principle component analysis (PCA) digit image test dataset must be processed by applying the first 5 steps, but using calculated from the training set. Given the new Eigen-data set, two Bayesian algorithms, linear and quadratic discriminant classifiers must be trained and tested. The next step will use the linear and quadratic discriminant classifiers using more than 3 principal components from X matrix. Our classification process, for linear and quadratic discriminants, was trained in the complete training data set and tests the performance in the test data set.)
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine Nava technique of OCR for characters on PCBs using principal component analysis and Bayesian Discriminant function into Nava (158) technique to provide the known and expected uses and benefits of Nava technique over recognition of unreadable characters on printed circuit boards technique of Nava (158). The proposed combination would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement.
Therefore, it would have been obvious to a person of ordinary skill in the art to incorporate Nava to Nava (158) in order to provide better OCR detectability of unreadable characters. (Refer to Nava page 1, Col. 2.)
However Nava (158) as modified by Nava does not explicitly disclose the following which would have been obvious in view of Chen from similar filed of endeavor “each unit including an overmold structure and a surface over the overmold structure, the panel further including a surface outside of the array of units;” (Chen, page 14 last paragraph page 15, first paragraph, discloses Referring to FIG. 9G, fabrication state 250b may include a panel 252 having a plurality of units to be singulated. For example, singulation may occur at the boundaries shown by dashed lines 260 to yield singulated individual units. Panel 252 is shown to include a substrate panel 254 on which upper portions (collectively shown as 256) are formed thereon. Each unit of such an upper-portion panel may comprise the various parts described herein with reference to Figures 3, 4 and / or 5. For example, each unit of such a top-side panel may include the shielding features of Figures 3, 4, and / or 5. These components may include various components and shielding structures mounted or implemented on the substrate panel 254. The top-side panel 256 may also include an overmolded layer that may be formed as a common layer for a number of individual units. Similar to the common overmold layer, the upper conductive layer 258 may be formed to cover a plurality of individual units.)
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine Chen technique of using overmolded structure in RF circuit into Nava (158) as modified by Nava technique to provide the known and expected uses and benefits of Chen technique over recognition of unreadable characters on printed circuit boards technique of Nava (158) as modified by Nava. The proposed combination would have constituted a mere arrangement of old elements with each performing their known function, the combination yielding no more than one would expect from such an arrangement.
Therefore, it would have been obvious to a person of ordinary skill in the art to incorporate Chen to Nava (158) as modified by Nava in order to prevent unwanted contact with the surface of circuits and filling Gaps for additional protection. (Refer to Chen page 6, paragraph 4.)
Claim 10 has been analyzed and is rejected for the reasons indicated in claim 1 above. Additionally, the rationale and motivation to combine the Nava (158), Nava , and Chen, references, presented in rejection of claim 1, apply to this claim.
As per claim 2, The packaged module processing system of claim 1, Nava (158), as modified by Nava as modified by Chen further discloses “wherein the character recognition system is further configured to obtain a digital image of a character imprinted on the surface outside of the array of units,” (Nava(158), ¶[0012] discloses Each printed circuit board can be implemented as a packaging substrate panel having an array of modules joined together, such that the joined modules become the individual modules upon singulation by the second production system. Further ¶[0034] discloses such a panel can be singulated to produce a number of individual packaged modules. In some embodiments, such singulated packaged modules can be substantially complete, or be processed further. and [0036], further see figures 3-6).
“and perform a pattern matching process for the digital image of the character.”(Nava (158) ¶[0037] discloses a GSC feature extraction technique can be applied to obtain characteristics that will be used in a character recognition step. Experimental results show that applying the GSC algorithm to extract the features and using a KNN classifier with Euclidian Distance can improve optical character recognition (OCR) detectability of damaged characters from about 95% to more than 97%. ¶[0041] discloses one of the foregoing OCR techniques (e.g., the pattern matching technique) can be utilized. )
Claim 11 has been analyzed and is rejected for the reasons indicated in claim 2 above.
As per claim 6, The packaged module processing system of claim 1, Nava (158), as modified by Nava as modified by Chen further discloses “wherein the surface of each unit includes a surface of the respective overmold structure of the unit.” (Chen, page 14 last paragraph page 15, first paragraph, discloses Referring to FIG. 9G, fabrication state 250b may include a panel 252 having a plurality of units to be singulated. For example, singulation may occur at the boundaries shown by dashed lines 260 to yield singulated individual units. Panel 252 is shown to include a substrate panel 254 on which upper portions (collectively shown as 256) are formed thereon. Each unit of such an upper-portion panel may comprise the various parts described herein with reference to Figures 3, 4 and / or 5. For example, each unit of such a top-side panel may include the shielding features of Figures 3, 4, and / or 5. These components may include various components and shielding structures mounted or implemented on the substrate panel 254. The top-side panel 256 may also include an overmolded layer that may be formed as a common layer for a number of individual units. Similar to the common overmold layer, the upper conductive layer 258 may be formed to cover a plurality of individual units. Referring to Figure 9J, fabrication state 264b may include embedding and / or forming overmold 105 on the lower surface of substrate 254 (facing upwardly). In one embodiment, the overmold 105 may completely encapsulate the lower component 104 and the fillers 111 (e.g., through-mold connections) in the fabrication state 264b. )
Claim 15 has been analyzed and is rejected for the reasons indicated in claim 6 above.
As per claim 7, The packaged module processing system of claim 1, Nava (158), as modified by Nava as modified by Chen further discloses “wherein the surface of each unit includes a surface of a shielding layer formed over the respective overmold structure of the unit.” (Chen, page 14 last paragraph- page 15, first -third paragraphs, discloses Referring to FIG. 9G, fabrication state 250b may include a panel 252 having a plurality of units to be singulated. For example, singulation may occur at the boundaries shown by dashed lines 260 to yield singulated individual units. Panel 252 is shown to include a substrate panel 254 on which upper portions (collectively shown as 256) are formed thereon. Each unit of such an upper-portion panel may comprise the various parts described herein with reference to Figures 3, 4 and / or 5. For example, each unit of such a top-side panel may include the shielding features of Figures 3, 4, and / or 5. These components may include various components and shielding structures mounted or implemented on the substrate panel 254. The top-side panel 256 may also include an overmolded layer that may be formed as a common layer for a number of individual units. Similar to the common overmold layer, the upper conductive layer 258 may be formed to cover a plurality of individual units. Referring to Figure 9J, fabrication state 264b may include embedding and / or forming overmold 105 on the lower surface of substrate 254 (facing upwardly). In one embodiment, the overmold 105 may completely encapsulate the lower component 104 and the fillers 111 (e.g., through-mold connections) in the fabrication state 264b. Referring to FIG. 9K, fabrication state 266b may include removing at least a portion of overmold 105. For example, the outward surface (e.g., the top surface) of the overmold 105 may be removed. Removing at least a portion of the overmold 105 may expose the solder balls 106 through the overmold 105. For example, the overmold 105 may partially seal the solder balls 106 after a portion of the overmold 105 has been removed. The portion of overmold 105 may be removed using a variety of different types of processes and / or methods. For example, the overmold 105 may be ground (to the abrasive surface) to remove portions of the overmold 105 (to expose portions of the solder balls 106). In another example, portions of the overmold 105 may be removed using a laser to melt and / or burn portions of the overmold 105 (to expose portions of the solder balls 106). In a further example, a portion of the overmold 105 may be ablated. For example, a stream of particles (e.g., water particles, sand particles, etc.) may be used to erode a portion of the overmold 105. In one embodiment, removing the portion of the overmold 105 may also remove portions of the fillers 111. For example, ablating the overmold 105 may remove the upper portions of the fillers 111. It may also expose portions of the fillers 111 through the overmold 105 and may allow the fillers 111 to provide a connection (e.g., electrical connection) through the overmold 105 have. )
Claim 17 has been analyzed and is rejected for the reasons indicated in claim 7 above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAGHAYEGH AZIMA whose telephone number is (571)272-1459. The examiner can normally be reached Monday-Friday, 9:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vincent Rudolph can be reached at (571)272-8243. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAGHAYEGH AZIMA/Examiner, Art Unit 2671