DETAILED ACTION
Response to Arguments
Applicants applicant's request to reconsider the validity of the rejections made in the final office action mailed 04/07/2026 during the interview was persuasive and the finality of the last action is withdrawn (see interview agenda for example). This action is non-final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the third work function metal" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected by 102(a)(2) as being anticipated by Yim et al. (US 2022/0375935 A1; hereinafter “Yim”).
In regard to claim 1, Yim teaches a CFET structure (CFET stacks of an integrated circuit device 1000) (Fig. 1 and paragraph 15), comprising:
a substrate (a substrate 100) (Fig. 1 and paragraph 15);
a first CFET formed above the substrate (a first CFET stack CFET1) (Fig. 1 and paragraph 15); and
a second CFET formed above the substrate (a second CFET stack CFET2) (Fig. 1 and paragraph 15); wherein:
each CFET comprises a top FET (an upper transistor UT1 and UT2) and a bottom FET (a lower transistor LT1 and LT2) (Fig. 1 and paragraph 16), each of the top FET and bottom FET
comprises at least one nanosheet channel (each of the lower active region 22L and the upper active region 22U may be a nanosheet) (Fig. 1 and paragraph 41);
the top FET of each stacked FET comprises a first polarity (since the stacked transistors are CFET the upper and lower transistors UT and LT have a conductivity opposite of each other) (Fig. 1 and paragraph 16);
the bottom FET of each a stacked FET comprises a second polarity (since the stacked transistors are CFET the upper and lower transistors UT and LT have a conductivity opposite of each other) (Fig. 1 and paragraphs 16 and 21);
the top FET of the first CFET comprises a first work function metal material (a first upper gate work function layer 23U_1 formed from a second upper gate work function layer 23U_2 formed from first and second preliminary upper gate work function layers 23UP_1, 23UP_2 and work function layer 23U_3) (Fig. 1, Fig. 14 and paragraphs 21, 39 and 69); and
the top FET of the second CFET comprises a second work function metal material (a second upper gate work function layer 23U_2 formed from first and second preliminary upper gate work function layers 23UP_2 and work function layer 23U_3) (Fig. 1 and paragraphs 21 and 39 and 69).
Claims 1 and 5 are rejected by 102(a)(2) as being anticipated by Smith et al. (US 2019/0172828 A1; hereinafter “Smith”).
In regard to claim 1, Smith teaches a CFET structure (a semiconductor apparatus 400) (Fig. 4 and paragraph 54), comprising:
a substrate (substrate strips 11) (Fig. 4 and paragraph 57);
a first CFET formed above the substrate (a first stack of FETs includes a first FET and a second FET) (Fig. 4 and paragraph 54); and
a second CFET formed above the substrate (a second stack of FETs includes a third FET and a fourth FET) (Fig. 4 and paragraph 55) ; wherein:
each CFET comprises a top FET and a bottom FET (a second FET which includes a second gate 34 and a fourth FET which includes a fourth gate 35 function as the top FETs, and a third FET which includes a third gate 33, and a first FET which includes a first gate 32 functions as the bottom FETs), each of the top FET and bottom FET comprises at least one nanosheet channel (the first through fourth FETs contain first through fourth channels 22-25) (Fig. 4 and paragraphs 54-55);
the top FET of each stacked FET comprises a first polarity; the bottom FET of each a stacked FET comprises a second polarity (FETs having the lower gates are referred to as lower FETs, and FETs having the upper gates are referred to as upper FETs, and the upper FETs are p-type and the lower FETs are n-type) (Fig. 4 and paragraphs 56 and 60);
the top FET of the first CFET comprises a first work function metal material (the second gate 34 includes a WF structure 714) (Fig. 4 and paragraph 70); and
the top FET of the second CFET comprises a second work function metal material (the fourth gate 35 contains a WF structure 714) (Fig. 4, Fig. 7 and paragraph 70).
In regard to claim 5, Smith teaches the CFET structure according to claim 1, further comprising a dielectric layer separating a gate region of the top FET of the first CFET and a gate region of the bottom FET of the first CFET (the fourth gate 35 is physically separated from the third gate 33 using the dielectric separation layer 1410) (Fig. 4 and paragraph 55).
Claims 8 and 14 are rejected by 102(a)(1) as being anticipated by Fulford et al. (US 2021/0104523 A1; hereinafter “Fulford”).
In regard to claim 8, Fulford a CFET structure (complementary field effect transistor) comprising:
a substrate (a plurality of transistor pairs formed over a substrate) (Fig. 1 and paragraph 20);
a first CFET formed above the substrate (a transistor pair 102) (Fig. 1 and paragraph 36);
a second CFET formed above the substrate (a transistor pair 104) (Fig. 1 and paragraph 36);
a third CFET formed above the substrate (a transistor pair 106) (Fig. 1 and paragraph 36); and
a fourth CFET formed above the substrate (a transistor pair 108) (Fig. 1 and paragraph 36);
wherein: each stacked FET comprises a top FET and a bottom FET (a n-type transistor 102A and a p-type transistor 102B) (Fig. 1 and paragraph 36), each of the top FET and bottom FET comprising at least one nanosheet channel (first nano-channels 110, 112, and second nano-channels 114 and 116) (Fig. 1 and paragraph 37);
the top FET of each stacked FET comprises a first polarity (transistor 102A is an n-type transistor) (Fig. 1 and paragraph 36);
the bottom FET of each a stacked FET comprises a second polarity (transistor 102B is a p-type transistor) (Fig. 1 and paragraph 36);
the top FET of the first CFET comprises a first work function metal;
the top FET of the second CFET comprises a second work function metal;
the top FET of the third CFET comprises a third work function metal material; and
the top FET of the fourth CFET comprises a fourth work function metal material (each transistor has gate structures 118-124 which includes a metal stack deposited to surround the first/second nano-channels that would function as the work function metal material) (Fig. 1 and paragraph 57).
In regard to claim 14, Fulford teaches wherein the bottom FET of the fourth CFET comprises an eighth work function metal (as each transistor has gate structures 118-124 which includes a metal stack deposited to surround the first/second nano-channels that would function as the work function metal material, the bottom cfet of the transistor pair 108 would have an eighth work function metal).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Rachmady et al. (US 2023/0073078 A1; hereinafter “Rachmady”).
In regard to claim 2, Yim doesn’t explicitly teach the CFET structure, further comprising independent gate contacts for the top FET of the first CFET and the bottom FET of the first CFET.
Rachmady teaches a CFET structure (complementary field effect transistor) (an integrated circuit structure) (Fig.1A and paragraph 3), comprising independent gate contacts (contacts 125 and 129) for a top FET (upper device) of the first CFET and a bottom FET (lower device) of a first CFET (a CFET on the far left shows independent contacts 125 and 129 for the upper and lower device) (Fig. 1A and paragraphs 24-26).
It would’ve been obvious to one skilled in the art at the time to combine the teachings of Yim in view of Rachmady to have the CFET structure further comprise independent gate contacts for the top FET of the first CFET and the bottom FET of the first CFET since this allows various interconnects schemes to be used as taught by Rachmady (paragraph 26).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Liebmann et al. (US 2021/0043630 A1; hereinafter “Liebmann”).
In regard to claim 3, Yim doesn’t explicitly teach further comprising a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET.
Liebmann teaches a CFET structure (complementary field effect transistor) (3D semiconductor apparatus 399) (Fig. 3L and paragraph 83), comprising a common gate contact (fifth conductive trace 343) for the top FET (nFET N3) of a first CFET (third stack 383) and a bottom FET (pFET P3) of the first CFET (Fig. 3L and paragraphs 46 and 80).
It would’ve been obvious to one skilled in the art to combine the teachings of Yim with the teachings of Liebmann to have a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET since this allows the formation of an inverter therefore improving device functionality as taught by Liebmann (paragraph 80).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Smith.
In regard to claim 4 Yim doesn’t explicitly teach a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET.
Smith teaches a CFET structure (complementary field effect transistor) (semiconductor apparatuses 300) (Fig. 3C and paragraph 48), further comprising a metal contact (routing tracks 314 and 324) connecting a gate region of the bottom FET (first gate 342) of a first CFET (a first stack of FETs 398) and a gate region of the bottom FET (a third gate 352) of a second CFET (a second stacks of FETs 399) (the first gate 342 and the third gate 352, can access one of the routing tracks 314 and 324 depending on orientation of the lower gate) (Figs. 3A-3C and paragraphs 50-52).
It would have been obvious to one skilled in the art to combine the teachings of Yim with the teachings of Smith to have a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET since FETs using the same routing tracks can allow the transfer of electrical signals between FETs with reduced routing congestion within the device as taught by Smith (paragraphs 51-52).
Claim 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Fulford as applied to claim 8, and further in view of Chanemougame et al (US 2023/0017350 A1; hereinafter “Chanemougame”).
In regard to claim 9, Fulford doesn’t explicitly teach the CFET structure, further comprising independent gate contacts for the top FET of the fourth CFET and the bottom FET of the fourth CFET.
Chanemougame teaches a CFET structure (complementary field effect transistor) (semiconductor structure 400) (Fig. 6d and paragraph 32), further comprising independent gate contacts (upper and lower gate contacts 479 and 472) for a top FET (a FET containing an upper gate region 493) of a fourth CFET and a bottom FET (a FET containing a lower gate region 492) of the fourth CFET (the CFET of the plurality of CFETs within the device is shown containing independent gate contacts the upper and lower gate regions 493 and 492) (Fig. 4f, Fig. 6d, paragraphs 32, 41 and 45)
It would’ve been obvious to one skilled in the art to combine the teachings of Fulford with the teachings of Chanemougame to have independent gate contacts for the top FET of the fourth CFET and the bottom FET of the fourth CFET since this allows the manufacture of a compact semiconductor device with increased functionality due to having independent contacts for the gates as taught by Chanemougame (paragraphs 3 and 39).
In regard to claim 12, Fulford doesn’t explicitly teach a dielectric layer separating the top FET of the second CFET and the bottom FET of the second CFET.
Chanemougame teaches a dielectric layer (a dielectric separation layer 418) separating the top FET of the second CFET and the bottom FET of the second CFET (Fig. 6d and paragraph 37).
It would’ve been obvious to one skilled in the art to combine the teachings of Fulford with the teachings of Chanemougame to have a dielectric layer separating the top FET of the second CFET and the bottom FET of the second CFET since this layout is known to prevent unwanted shorts between the gate regions as taught by Chanemougame (paragraph 37).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford as applied to claim 8, and further in view of Liebmann.
In regard to claim 10, Fulford doesn’t explicitly teach further comprising a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET.
Liebmann teaches a CFET structure (complementary field effect transistor) (3D semiconductor apparatus 399) (Fig. 3L and paragraph 83), comprising a common gate contact (fifth conductive trace 343) for the top FET (nFET N3) of a first CFET (third stack 383) and a bottom FET (pFET P3) of the first CFET (Fig. 3L and paragraphs 46 and 80).
It would’ve been obvious to one skilled in the art to combine the teachings of Yim with the teachings of Liebmann to have a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET since this allows the formation of an inverter therefore improving device functionality as taught by Liebmann (paragraph 80).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford as applied to claim 8, and further in view of Smith.
In regard to claim 11, Fulford doesn’t explicitly teach further comprising a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET.
Smith teaches a CFET structure (complementary field effect transistor) (semiconductor apparatuses 300) (Fig. 3C and paragraph 48), further comprising a metal contact (routing tracks 314 and 324) connecting a gate region of the bottom FET (first gate 342) of a first CFET (a first stack of FETs 398) and a gate region of the bottom FET (a third gate 352) of a second CFET (a second stacks of FETs 399) (the first gate 342 and the third gate 352, can access one of the routing tracks 314 and 324 depending on orientation of the lower gate) (Figs. 3A-3C and paragraphs 50-52).
It would have been obvious to one skilled in the art to combine the teachings of Fulford with the teachings of Smith to have a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET since FETs using the same routing tracks can allow the transfer of electrical signals between FETs with reduced routing congestion within the device as taught by Smith (paragraphs 51-52).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Fulford as applied to claim 8, and further in view of Yim.
In regard to claim 13, Fulford doesn’t explicitly teach further comprising a seventh work function metal of the bottom FET of the third CFET, the seventh work function metal in contact with the third work function metal.
Yim teaches a CFET structure (CFET stacks of an integrated circuit device 1000) (Fig. 1 and paragraph 15), further comprising a seventh work function metal (a third upper gate work function layer 23U_3 in the CFET in a first region R1 in which the first CFET stack CFET1 is formed) of the bottom FET of a third CFET (the third upper gate work function layer 23U_3 functions as the seventh work function metal due to the plurality of work function metals within the device as shown in Figs. 14A-14G) (Figs. 14A-14G and paragraphs 45 and 67-70), the seventh work function metal in contact with a third work function metal (the gate work function layer 23U_3 is shown contacting a first preliminary upper gate work function layer 23UP_1) (Figs. 14A-14G).
It would’ve been obvious to one skilled in the art to combine the teachings of Fulford with the teachings of Yim to have a seventh work function metal of the bottom FET of the third CFET, the seventh work function metal in contact with the third work function metal. Since this allows for multiple stacked transistors having different threshold voltages in a device to reduce leakage power as taught by Yim (paragraph 3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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