DETAILED ACTION
Response to Arguments
Applicant's arguments filed 03/04/2026 have been fully considered but they are not persuasive. In regard to claim 1, Applicant asserts that Yim et al. (US 2022/0375935 A1; hereinafter “Yim”) fails to teach “the top FET of the first CFET comprises a first work function metal material; and the top FET of the second CFET comprises a second work function metal material”. The Examiner respectfully disagrees. As shown in Fig. 14 and described in paragraph 69, the n some embodiments, the first and second preliminary upper gate work function layers 23UP_1, 23UP_2 and the third upper gate work function layer 23U_3, which form the upper gate work function layers 23U_1, 23U_2, and 23U_3 include different materials. Further the Examiner notes Applicant's argument that Yim does not teach the work function metal between the top first and second CFET are different metals is not persuasive as the limitations on which the Applicant relies (i.e., ) are not stated in the claims. It is the claims that define the claimed invention, and it is the claims, not specifications that are anticipated or unpatentable. Constant v. Advanced Micro-Devices Inc. , 7 USPQ 2d 1064. Claiming “the top FET of the first CFET comprises a first work function metal material; and the top FET of the second CFET comprises a second work function metal material” does not require the metal material to be different only that two layers of metal exist.
In regard to claim 8, Applicant asserts Lilak et al. (US 2020/0098756 A1; hereinafter “Lilak”) fails to teach the following:
the top FET of the first CFET comprises a first work function metal;
the top FET of the second CFET comprises a second work function metal;
the top FET of the third CFET comprises a third work function metal material; and
the top FET of the fourth CFET comprises a fourth work function metal material
the Examiner respectfully disagrees. The Applicant asserts the cited paragraphs do not inherently or necessarily disclose the claimed limitations wherein the work function metals (145) of the first and the second upper FET would inherently or necessarily comprise differing WFM materials. In response to Applicant's argument that Lilak does not include certain features of Applicant's invention, the limitations on which the Applicant relies (i.e., differing WFM materials) are not stated in the claims. It is the claims that define the claimed invention, and it is the claims, not specifications that are anticipated or unpatentable. Constant v. Advanced Micro-Devices Inc. , 7 USPQ 2d 1064. The limitations of the claim only require the existence that a total of work function materials exist not that said work function materials be different.
Applicant’s arguments in regard to claim 8 filed 03/04/2026 have been fully considered and are persuasive. Therefore, the claim objection rejection has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 5-6 are rejected by 102(a)(2) as being anticipated by Yim et al. (US 2022/0375935 A1; hereinafter “Yim”).
In regard to claim 1, Yim teaches a CFET structure (CFET stacks of an integrated circuit device 1000) (Fig. 1 and paragraph 15), comprising:
a substrate (a substrate 100) (Fig. 1 and paragraph 15);
a first CFET formed above the substrate (a first CFET stack CFET1) (Fig. 1 and paragraph 15); and
a second CFET formed above the substrate (a second CFET stack CFET2) (Fig. 1 and paragraph 15); wherein:
each CFET comprises a top FET (an upper transistor UT1 and UT2) and a bottom FET (a lower transistor LT1 and LT2) (Fig. 1 and paragraph 16), each of the top FET and bottom FET
comprises at least one nanosheet channel (each of the lower active region 22L and the upper active region 22U may be a nanosheet) (Fig. 1 and paragraph 41);
the top FET of each stacked FET comprises a first polarity (since the stacked transistors are CFET the upper and lower transistors UT and LT have a conductivity opposite of each other) (Fig. 1 and paragraph 16);
the bottom FET of each a stacked FET comprises a second polarity (since the stacked transistors are CFET the upper and lower transistors UT and LT have a conductivity opposite of each other) (Fig. 1 and paragraphs 16 and 21);
the top FET of the first CFET comprises a first work function metal material (a first upper gate work function layer 23U_1 formed from a second upper gate work function layer 23U_2 formed from first and second preliminary upper gate work function layers 23UP_1, 23UP_2 and work function layer 23U_3) (Fig. 1, Fig. 14 and paragraphs 21, 39 and 69); and
the top FET of the second CFET comprises a second work function metal material (a second upper gate work function layer 23U_2 formed from first and second preliminary upper gate work function layers 23UP_2 and work function layer 23U_3) (Fig. 1 and paragraphs 21 and 39 and 69).
In regard to claim 5, Yim teaches a dielectric layer (a first upper gate insulator 21U) separating a gate region (a first upper active region 22U) of the top FET of the first CFET and a gate region (a first lower active region 22L) of the bottom FET of the first CFET (the first upper gate insulator 21U is shown between the first upper active region 22U and first lower active region 22L in Fig. 1) (Fig. 1 and paragraphs 16 and 36).
In regard to claim 6, Yim teaches wherein the third work function metal contacts the first work function metal (the first lower gate work function layer 23L is shown contacting the first upper gate work function layer 23U_1 in Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Rachmady et al. (US 2023/0073078 A1; hereinafter “Rachmady”).
In regard to claim 2, Yim doesn’t explicitly teach the CFET structure, further comprising independent gate contacts for the top FET of the first CFET and the bottom FET of the first CFET.
Rachmady teaches a CFET structure (complementary field effect transistor) (an integrated circuit structure) (Fig.1A and paragraph 3), comprising independent gate contacts (contacts 125 and 129) for a top FET (upper device) of the first CFET and a bottom FET (lower device) of a first CFET (a CFET on the far left shows independent contacts 125 and 129 for the upper and lower device) (Fig. 1A and paragraphs 24-26).
It would’ve been obvious to one skilled in the art at the time to combine the teachings of Yim in view of Rachmady to have the CFET structure further comprise independent gate contacts for the top FET of the first CFET and the bottom FET of the first CFET since this allows various interconnects schemes to be used as taught by Rachmady (paragraph 26).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Liebmann et al. (US 2021/0043630 A1; hereinafter “Liebmann”).
In regard to claim 3, Yim doesn’t explicitly teach further comprising a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET.
Liebmann teaches a CFET structure (complementary field effect transistor) (3D semiconductor apparatus 399) (Fig. 3L and paragraph 83), comprising a common gate contact (fifth conductive trace 343) for the top FET (nFET N3) of a first CFET (third stack 383) and a bottom FET (pFET P3) of the first CFET (Fig. 3L and paragraphs 46 and 80).
It would’ve been obvious to one skilled in the art to combine the teachings of Yim with the teachings of Liebmann to have a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET since this allows the formation of an inverter therefore improving device functionality as taught by Liebmann (paragraph 80).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yim in view of Smith et al. (US 2019/0172828 A1; hereinafter “Smith”).
In regard to claim 4 Yim doesn’t explicitly teach a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET.
Smith teaches a CFET structure (complementary field effect transistor) (semiconductor apparatuses 300) (Fig. 3C and paragraph 48), further comprising a metal contact (routing tracks 314 and 324) connecting a gate region of the bottom FET (first gate 342) of a first CFET (a first stack of FETs 398) and a gate region of the bottom FET (a third gate 352) of a second CFET (a second stacks of FETs 399) (the first gate 342 and the third gate 352, can access one of the routing tracks 314 and 324 depending on orientation of the lower gate) (Figs. 3A-3C and paragraphs 50-52).
It would have been obvious to one skilled in the art to combine the teachings of Yim with the teachings of Smith to have a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET since FETs using the same routing tracks can allow the transfer of electrical signals between FETs with reduced routing congestion within the device as taught by Smith (paragraphs 51-52).
Claims 8-9, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. (US 2020/0098756 A1; hereinafter “Lilak”).
In regard to claim 8, Lilak in Fig. 5 and associated Fig. 3B, teaches a CFET structure (complementary field effect transistor) (a CMOS transistor structure 100) (Fig. 5 and paragraph 35),comprising:
a substrate (a silicon substrate 110) (Fig. 5 and paragraph 35);
a first CFET formed above the substrate (a CFET formed from the upper and lower device sections 106 and 108, annotated as A in annotated Fig. 5 below) (Fig. 5 and paragraph 36);
a second CFET formed above the substrate (a CFET formed from the upper and lower device sections 106 and 108, annotated as B in annotated Fig. 5 below) (Fig. 5 and paragraph 36);
a third CFET formed above the substrate (a CFET formed from the upper and lower device sections 106 and 108, annotated as C in annotated Fig. 5 below) (Fig. 5 and paragraph 36); and
a fourth CFET formed above the substrate (a CFET formed from the upper and lower device sections 106 and 108, annotated as D in annotated Fig. 5 below) (Fig. 5 and paragraph 36);
wherein:
each stacked FET comprises a top FET (the upper device 106) and a bottom FET (the lower device 108), each of the top FET and bottom FET comprising at least one nanosheet channel (the nanowire channels 130a and 130b) (Fig. 5 and paragraphs 36-37);
the top FET of each stacked FET comprises a first polarity (the upper device 106 can have an n-type polarity) (Fig. 5 and paragraph 42);
the bottom FET of each a stacked FET comprises a second polarity (the lower device 108 can have a p-type polarity) (Fig. 5 and paragraph 42);
the top FET of the first CFET comprises a first work function metal (a work function layer 145 that wraps around the body of each nanowire 132 of the upper device of CFET A) (Fig. 3B, Fig. 5 and paragraph 37);
the top FET of the second CFET comprises a second work function metal (a work function layer 145 that wraps around the body of each nanowire 132 of the upper device of CFET B) (Fig. 3B, Fig. 5 and paragraph 37);
the top FET of the third CFET comprises a third work function metal material (a work function layer 145 that wraps around the body of each nanowire 132 of the upper device of CFET C) (Fig. 3B, Fig. 5 and paragraph 37); and
the top FET of the fourth CFET comprises a fourth work function metal material (a work function layer 145 that wraps around the body of each nanowire 132 of the upper device of CFET D) (Fig. 3B, Fig. 5 and paragraph 37).
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In regard to claim 9, Lilak teaches further comprising independent gate contacts for the top FET of the fourth CFET and the bottom FET of the fourth CFET (contacts 122 are shown individually over the upper and lower devices 106 and 108 of CFET D in annotated Fig. 5) (annotated Fig. 5 and paragraph 46).
In regard to claim 12, Lilak teaches a dielectric layer (an isolation layer 150) separating the top FET of the second CFET and the bottom FET of the second CFET (annotated Fig. 5 and paragraph 37).
In regard to claim 14, Lilak teaches wherein the bottom FET of the fourth CFET comprises an eight work function metal (a work function layer 145 that wraps around the body of each nanowire 132 of the lower device of CFET D) (Fig. 3B, annotated Fig. 5 and paragraph 37).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak in view of Liebmann.
In regard to claim 10, Lilak doesn’t explicitly teach further comprising a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET.
Liebmann teaches a CFET structure (complementary field effect transistor) (3D semiconductor apparatus 399) (Fig. 3L and paragraph 83), comprising a common gate contact (fifth conductive trace 343) for the top FET (nFET N3) of a first CFET (third stack 383) and a bottom FET (pFET P3) of the first CFET (Fig. 3L and paragraphs 46 and 80).
It would’ve been obvious to one skilled in the art to combine the teachings of Yim with the teachings of Liebmann to have a common gate contact for the top FET of the first CFET and the bottom FET of the first CFET since this allows the formation of an inverter therefore improving device functionality as taught by Liebmann (paragraph 80).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak in view of Smith.
In regard to claim 11, Lilak doesn’t explicitly teach further comprising a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET.
Smith teaches a CFET structure (complementary field effect transistor) (semiconductor apparatuses 300) (Fig. 3C and paragraph 48), further comprising a metal contact (routing tracks 314 and 324) connecting a gate region of the bottom FET (first gate 342) of a first CFET (a first stack of FETs 398) and a gate region of the bottom FET (a third gate 352) of a second CFET (a second stacks of FETs 399) (the first gate 342 and the third gate 352, can access one of the routing tracks 314 and 324 depending on orientation of the lower gate) (Figs. 3A-3C and paragraphs 50-52).
It would have been obvious to one skilled in the art to combine the teachings of Yim with the teachings of Smith to have a metal contact connecting a gate region of the bottom FET of the first CFET and a gate region of the bottom FET of the second CFET since FETs using the same routing tracks can allow the transfer of electrical signals between FETs with reduced routing congestion within the device as taught by Smith (paragraphs 51-52).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lilak as applied to claim 8, and further in view of Lilak as taught in Fig. 1B.
In regard to claim 13, Lilak as taught in Fig. 5 and associated Fig. 3B, teaches a seventh work function metal (a work function layer 145) of the bottom FET of the third CFET (the work function layer 145 is located in the lower device 108 of CFET C formed from the upper and lower device sections 106 and 108) (annotated Fig. 5 and paragraphs 39).
However, Lilak doesn’t explicitly teach the seventh work function metal in contact with the third work function metal.
Lilak as taught in Fig. 1B, teaches a CFET structure (complementary field effect transistor) (a CMOS transistor structure 100) (Fig. 1 and paragraph 35), further comprising a seventh work function metal (a work function layer 145) of a bottom FET of a third CFET (the work function layer 145 is located in the lower device 108 of a CFET formed from the upper and lower device sections 106 and 108 to the far right) (Fig. 1B and paragraphs 39), the seventh work function metal in contact with a third work function metal (the work function layer 145 located in the lower device 108 is shown contacting the work function layer 145 located in the upper device 106 of the CFET formed from the upper and lower device sections 106 and 108 to the far right as shown in Fig. 1B).
It would be obvious to one skilled in the art to combine the teachings of Lilak as taught in Fig. 5 with the embodiment shown in Fig. 1B to have a seventh work function metal of the bottom FET of the third CFET, the seventh work function metal in contact with the third work function metal since this allows for the shape of the fin to be altered resulting in increased electron mobility as taught by Lilak (paragraph 40).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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