Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is non-final and is in response to claims filed on 12/04/2025 via RCE. Claims 1, 4-10, 14, and 16 are pending for examination. Claims 1, 4-6, 9, and 16 are currently amended. Claims 7, 8, 10, 14 are as previously filed.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/04/2025 has been entered.
Response to Arguments
Rejections Under 35 U.S.C. 112
Applicant has amended the claim at issue and therefore the previous rejection has been withdrawn.
Rejections Under 35 U.S.C. 101
Applicant’s arguments, see Remarks 14-18, filed 12/04/2025, with respect to claims 1, 4-10, 14, and 16 have been fully considered and are persuasive. The rejections under 35 U.S.C. 101 of 1, 4-10, 14, and 16 has been withdrawn.
Rejections Under 35 U.S.C. 103
Applicant’s arguments with respect to claims 1, 4-10, 14, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “an absolute value converter”, “a leading one detector”, “a rounder”, and “an exponent updater” in claims 1 and 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 4-10, 14, and 16 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “an exponent updater configured to combine the final mantissa, the symbol from the absolute value converter, and an exponent value derived from the starting bit position to generate a final floating-point result”. However, there is no indication in the original disclosure that the exponent updater combines the final mantissa, the symbol from the absolute value converter, and an exponent value derived from the starting bit position to generate a final floating-point result. FIG. 3 shows that the exponent updater takes 01_C to 0M_C, 01_LD to 0M_LD, and 01_exp to 0M_exp and outputs the exponents of 01 to 0M. It does not combine the mantissas, the symbol from the absolute value converter, and the exponents. The specification discloses, in paragraph [0028], that the exponent updater determines the exponents of each outputs according to the positions of the leading ones, the rounding, and the exponents. It does not disclose combining the mantissas, the symbol from the absolute value converter, and the exponents.
Claim 16 recites similar limitations and is rejected for at least the same reasons as claim 1 above.
Claims 4-10 and 14 are rejected for being dependent on an above rejected claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-10, 14, and 16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is rejected because claim limitations “an absolute value converter”, “a leading one detector”, “a rounder”, and “an exponent updater” invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The written description does not disclose any structure, materials, or acts for performing the absolute value conversion, leading one detection, rounding, or exponent updating. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim 16 also recites “an absolute value converter”, “a leading one detector”, “a rounder”, and “an exponent updater” and is rejected for at least the same reasons as claim 1 above.
Claims 4-10 and 14 are rejected for being dependent on an above rejected claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-8, 10, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20230244442 A1) hereinafter Lee in view of Langhammer et al. (US 20190018673 A1) hereinafter Langhammer 1 further in view of Okutomi et al (Machine Translation of JP 2018097438 A, as filed with the final rejection filed 09/11/2025) hereinafter Okutomi further in view of Langhammer et al. (US 8645449 B1) hereinafter Langhammer 2.
With regards to claim 1, Lee teaches A multi-input multi-output adder for performing a multi-input multi-output floating-point operation, comprising: a fixed-point adder circuity configured to perform an intermediate calculation process of the floating-point operation, wherein the intermediate calculation process comprises: (Lee [0212]: FIG. 31 illustrates a MAC operator 1000 according to an embodiment of the present disclosure. The MAC operator 1000 according to the present embodiment may be applied to the PIM devices 10, 100, and 400, described with reference to FIGS. 1, 2, and 20. Referring to FIG. 31, the MAC operator 1000 of the present embodiment may include a multiplying circuit 1100, a floating-point-to-fixed-point converting circuit 1200, an adder tree 1300, an accumulator 1400, and a fixed-point-to-floating-point converter; Lee [0219]: The adder tree 1300 may perform adding operations on the floating-point format multiplication result data M0_FIX-M7_FIX that is output from the floating-point-to-fixed-point converters FFCO-FFC7. Because the multiplication result data M0_FIX-M7_FIX have fixed-point formats in which the position of a binary point is fixed, the adder tree 1300 may be configured as a fixed-point adder tree)
adding a first source operand and a second source operand to generate a first summed operand; (Lee [0219]: The adder tree 1300 may perform adding operations on the floating-point format multiplication result data M0_FIX-M7_FIX that is output from the floating-point-to-fixed-point converters FFCO-FFC7. Because the multiplication result data M0_FIX-M7_FIX have fixed-point formats in which the position of a binary point is fixed, the adder tree 1300 may be configured as a fixed-point adder tree)
an absolute value converter, coupled to an output of the fixed-point adder circuity, configured to convert an output result from the fixed-point adder circuity into an unsigned number result and to output a symbol thereof; (Lee [0337]: FIG. 55 illustrates an embodiment of the fixed-point-to-floating-point converter 3500 in the MAC operator 3000 of FIG. 50. As described with reference to FIG. 50, the fixed-point-to-floating-point converter 3500 may convert the fixed-point format first multiplication-accumulation data M_ACC_FIX[31:0] transmitted from the accumulator (3400 of FIG. 50) into floating-point format to output floating-point format MAC result data; Lee [0339]: The 2′s complement circuit 3510 may receive the remaining 31-bit data M_ACC_FIX[30:0] of the fixed-point format multiplication-accumulation data M_ACC_FIX[31:0] transmitted from the accumulator (3400 of FIG. 50) except for the MSB, which is the sign bit, and generate and output 2′s complement of the 31-bit data M_ACC_FIX[30:0])
a leading 1 detector, coupled to an output of the absolute value converter, configured to detect a starting bit position of a first 1 of the unsigned number result; (Lee [0341]: The MSB 1 detector 3530 may detect a position of the MSB 1 in the output data OUT[30:0] transmitted from the multiplexer 3520. Here, “MSB 1” may be defined as a most significant bit among the bits with a binary value of “1” in the output data OUT[30:0])
and an exponent updater configured to combine the final mantissa, the symbol from the absolute value converter, and an exponent value derived from the starting bit position to generate a final floating-point result, (Lee [0343]: the floating-point format MAC result data MAC_RST_FLT[31:0]; Lee Fig. 55: shows the sign, exponent, and mantissa being combined)
whereby the intermediate calculation process is performed by the fixed-point adder circuity without requiring normalization and rounding at each addition stage, thereby improving a hardware speed of the multi-input multi-output floating-point operation (Lee [0219]: the adder tree 1300 may be configured as a fixed-point adder tree. Accordingly, overhead of energy and latency due to alignment, normalization, and rounding in the floating-point adder tree may be reduced, and circuit area may also be reduced).
Lee fails to teach performing a direct truncation on at least one last bit of the first summed operand and subsequently performing a right shift on the first truncated-summed operand.
However, Langhammer 1 teaches performing a direct truncation on at least one last bit of the first summed operand (Langhammer 1 [0036]: Therefore, in some embodiments, to control the growth of the results of an arithmetic operation, and therefore packing, the operands 201 at each stage (e.g., 208A-208C) or a subset of the stages 208 may be truncated)
[and subsequently] performing a right shift on the first truncated-summed operand (Langhammer 1 [0036]: For example, soft logic circuitry (e.g., logic within the LAB) may right-shift the operands 201 by a bit to truncate the LSBs).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee with the truncation and shifting of Langhammer 1. One of ordinary skill in the art would be motivated to make this combination because it would control the growth of the results of an arithmetic operation as taught by Langhammer 1 reducing storage costs (Langhammer 1 [0036]). Also, as a result, arithmetic operations may pack more efficiently onto an integrated circuit with increased precision and performance as taught by Langhammer 1 (Langhammer 1 [0025]).
Lee in view of Langhammer 1 fails to teach That the right shift is performed subsequently to the truncation.
However, Okutomi does teach that the right shift of Lee in view of Langhammer 1 is performed subsequently to the truncation (Okutomi Page 11 Paragraph 6: the right shift of s bits of X. At this time, the lower s bits of X are truncated. That is, before X is divided by M (before X is shifted to the right by s bits)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 with performing the right shift subsequently to the truncation as taught by Okutomi. One of ordinary skill in the art would be motivated to make this combination because it would make sure the results are aligned properly, making calculations more accurate.
Lee in view of Langhammer 1 further in view of Okutomi fails to teach a left shifter, coupled to the leading 1 detector, configured to shift the unsigned number result based on the starting bit position to generate a normalized mantissa; a rounder, coupled to an output of the left shifter, configured to round the normalized mantissa to generate a final mantissa conforming to a target floating-point format.
However, Langhammer 2 teaches a left shifter, coupled to the leading 1 detector, configured to shift the unsigned number result based on the starting bit position to generate a normalized mantissa; (Langhammer 2 Column 5 Lines 16-18: (if signed numbers are used, leading 1's may be counted as well), and using the leading 0 count 217 to left-shift mantissa 213 at 227)
a rounder, coupled to an output of the left shifter, configured to round the normalized mantissa to generate a final mantissa conforming to a target floating-point format; (Langhammer 2 Column 5 Lines 19-21: Normalized mantissa 223 is then rounded, in a manner which may be well-known, by examining one or more rounding bits).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi with the left shifter and rounder as taught by Langhammer 2. One of ordinary skill in the art would be motivated to make this combination because it would allow for the mantissas to be normalized and rounded, increasing the flexibility of the system as the result could then be used with other conventional components.
With regards to claim 4, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 1 above. Lee further teaches wherein the fixed-point adder circuity is an adder tree (Lee [0219]: The adder tree 1300 may perform adding operations on the floating-point format multiplication result data M0_FIX-M7_FIX that is output from the floating-point-to-fixed-point converters FFCO-FFC7).
Lee fails to teach that further comprises a plurality of shifters.
However, Langhammer 1 teaches that further comprises a plurality of shifters (Langhammer 1 [0036]: For example, soft logic circuitry (e.g., logic within the LAB) may right-shift the operands 201 by a bit to truncate the LSBs).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 with the shifters as taught by Langhammer 1. One of ordinary skill in the art would be motivated to make this combination because it would control the growth of the results of an arithmetic operation as taught by Langhammer 1 reducing storage costs (Langhammer 1 [0036]). Also, as a result, arithmetic operations may pack more efficiently onto an integrated circuit with increased precision and performance as taught by Langhammer 1 (Langhammer 1 [0025]).
With regards to claim 5, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 4 above. Lee further teaches wherein each of the plurality of adders comprises a first adder, (Lee [0220]: The adder tree 1300 may be configured in a tree structure with a plurality of stages. Each of the plurality of stages may include at least one or more adders)
wherein the first adder [direct truncates a last bit of the first summed operand to generate the first truncated-summed operand,] (Lee [0220]: The adder tree 1300 may be configured in a tree structure with a plurality of stages. Each of the plurality of stages may include at least one or more adders).
Lee fails to teach and each of the plurality of shifters comprises a first shifter, [wherein the first adder] direct truncates a last bit of the first summed operand to generate the first truncated-summed operand.
However, Langhammer 1 teaches and each of the plurality of shifters comprises a first shifter, (Langhammer 1 [0036]: Therefore, in some embodiments, to control the growth of the results of an arithmetic operation, and therefore packing, the operands 201 at each stage (e.g., 208A-208C) or a subset of the stages 208 may be truncated.. For example, soft logic circuitry (e.g., logic within the LAB) may right-shift the operands 201 by a bit to truncate the LSBs)
[wherein the first adder] direct truncates a last bit of the first summed operand to generate the first truncated-summed operand, (Langhammer 1 [0036]: Therefore, in some embodiments, to control the growth of the results of an arithmetic operation, and therefore packing, the operands 201 at each stage (e.g., 208A-208C) or a subset of the stages 208 may be truncated.. For example, soft logic circuitry (e.g., logic within the LAB) may right-shift the operands 201 by a bit to truncate the LSBs).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 with the shifters as taught by Langhammer 1. One of ordinary skill in the art would be motivated to make this combination because it would control the growth of the results of an arithmetic operation as taught by Langhammer 1 reducing storage costs (Langhammer 1 [0036]). Also, as a result, arithmetic operations may pack more efficiently onto an integrated circuit with increased precision and performance as taught by Langhammer 1 (Langhammer 1 [0025]).
With regards to claim 6, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 1 above. Lee further teaches further comprising: N multipliers, wherein an output end of each of the multipliers is connected to the fixed- point adder circuity, (Lee [0213]: Specifically, the multiplying circuit 1100 may include a plurality of multipliers, for example, first to eighth multipliers MUL0-MUL7 arranged in parallel with each other; Lee Fig. 31: Fig. 31 shows the multipliers connected to the adder tree)
and wherein the fixed-point adder circuity is an adder tree (Lee [0219]: The adder tree 1300 may perform adding operations on the floating-point format multiplication result data M0_FIX-M7_FIX that is output from the floating-point-to-fixed-point converters FFCO-FFC7).
With regards to claim 7, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 1 above. Lee further teaches [and calculate] the first source operand and the second source operand [according to the maximum exponent extraction mantissas] (Lee [0219]: The adder tree 1300 may perform adding operations on the floating-point format multiplication result data M0_FIX-M7_FIX that is output from the floating-point-to-fixed-point converters FFCO-FFC7. Because the multiplication result data M0_FIX-M7_FIX have fixed-point formats in which the position of a binary point is fixed, the adder tree 1300 may be configured as a fixed-point adder tree)
Lee fails to teach at least one maximum exponent extractor circuit configured to: receive a plurality of floating-point operands determine a first floating-point operand with a largest exponent from the floating-point operands align an exponent of each of remaining floating-point operands of the floating-point operands with the largest exponent of the first floating-point operand such that a mantissa of each of the remaining floating-point operands is right shifted to generate a plurality of maximum exponent extraction mantissas and calculate [the first source operand and the second source operand] according to the maximum exponent extraction mantissas.
However, Langhammer 1 teaches at least one maximum exponent extractor circuit configured to: receive a plurality of floating-point operands (Langhammer 1 [0081]: The block floating point exponents from each block floating point tree (e.g., 800A-C) may be sorted by a circuit 902, which may select and output the maximum block floating point exponent received from the block floating point trees 800A-C);
determine a first floating-point operand with a largest exponent from the floating-point operands (Langhammer 1 [0081]: The block floating point exponents from each block floating point tree (e.g., 800A-C) may be sorted by a circuit 902, which may select and output the maximum block floating point exponent received from the block floating point trees 800A-C.);
align an exponent of each of remaining floating-point operands of the floating-point operands with the largest exponent of the first floating-point operand (Langhammer 1 [0081]: The outputs from the subtractors 904 may then feed into a set of shifters 906A-906C to normalize the block floating point mantissas. As such, each of the shifters 906A-906C may right shift a respective block floating point mantissa of a corresponding block floating point tree (e.g., 800A-800C) a number of bits corresponding to the respective output of the subtractor 904),
such that a mantissa of each of the remaining floating-point operands is right shifted to generate a plurality of maximum exponent extraction mantissas (Langhammer 1 [0081]: The outputs from the subtractors 904 may then feed into a set of shifters 906A-906C to normalize the block floating point mantissas. As such, each of the shifters 906A-906C may right shift a respective block floating point mantissa of a corresponding block floating point tree (e.g., 800A-800C) a number of bits corresponding to the respective output of the subtractor 904);
and calculate the [first source operand and the second source operand] according to the maximum exponent extraction mantissas (Langhammer 1 [0081]: embodiment of a block floating point combination tree 900 that may implement the summation of multiple block floating point trees 800).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 with the maximum exponent extractors and alignment as taught by Langhammer 1. One of ordinary skill in the art would be motivated to make this combination because it would control the growth of the results of an arithmetic operation as taught by Langhammer 1 reducing storage costs (Langhammer 1 [0036]). Also, as a result, arithmetic operations may pack more efficiently onto an integrated circuit with increased precision and performance as taught by Langhammer 1 (Langhammer 1 [0025]). Also, it would make sure that the operands are aligned, making calculations more efficient.
With regards to claim 8, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 7 above. Lee fails to teach wherein a bit number of the right shift of the mantissa of the each of the remaining floating-point operands is a difference value between the exponent of each of the remaining floating-point operands and the maximum exponent, respectively.
However, Langhammer 1 teaches wherein a bit number of the right shift of the mantissa of the each of the remaining floating-point operands is a difference value between the exponent of each of the remaining floating-point operands and the maximum exponent, respectively (Langhammer 1 [0081]: A set of subtractors 904 may couple to the circuit 902 and may then subtract each block floating point exponent from this maximum block floating point exponent. The outputs from the subtractors 904 may then feed into a set of shifters 906A-906C to normalize the block floating point mantissas).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 with the alignment as taught by Langhammer 1. One of ordinary skill in the art would be motivated to make this combination because it would control the growth of the results of an arithmetic operation as taught by Langhammer 1 reducing storage costs (Langhammer 1 [0036]). Also, as a result, arithmetic operations may pack more efficiently onto an integrated circuit with increased precision and performance as taught by Langhammer 1 (Langhammer 1 [0025]). Also, it would make sure that the operands are aligned, making calculations more efficient.
With regards to claim 10, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 7 above. Lee further teaches further comprising: a signed number converter circuit configured to: perform signed number conversion according to a symbol of each of the floating-point operands to generate signed number conversion mantissas, respectively, wherein the first source operand and the second source operand are two of the signed number conversion mantissas (Lee [0238]: Referring to FIG. 35, the first floating-point-to-fixed-point converter FFCO may receive the floating-point format first multiplication result data M0_FLT that is output from the first multiplier MUL0, and output the fixed-point format first multiplication result data M0_FIX; Lee [0240]: The 2′s complement circuit 1230 may receive the fixed-point format shifted and rounded first multiplication result data M0_FIX_SHIF_RD that is output from the round circuit 1220. The 2′s complement circuit 1230 may output the 2′s complement for the shifted and rounded first multiplication result data M0_FIX_SHIF_RD).
With regards to claim 14, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 1 above. Lee further teaches wherein inputs and outputs of the adder circuity are in floating-point format (Lee [0212]: the MAC operator 1000 of the present embodiment may include a multiplying circuit 1100, a floating-point-to-fixed-point converting circuit 1200, an adder tree 1300, an accumulator 1400, and a fixed-point-to-floating-point converter; Lee Fig. 31: shows the inputs being floating point and the output being floating point).
With regards to claim 16, Lee teaches A method operated by a multi-input multi-output adder for performing a multi-input multi-output floating-point operation, comprising: performing, by a fixed-point adder circuity of the multi-input multi-output adder, an intermediate calculation process of the floating-point operation, wherein the intermediate calculation process comprises: (Lee [0212]: FIG. 31 illustrates a MAC operator 1000 according to an embodiment of the present disclosure. The MAC operator 1000 according to the present embodiment may be applied to the PIM devices 10, 100, and 400, described with reference to FIGS. 1, 2, and 20. Referring to FIG. 31, the MAC operator 1000 of the present embodiment may include a multiplying circuit 1100, a floating-point-to-fixed-point converting circuit 1200, an adder tree 1300, an accumulator 1400, and a fixed-point-to-floating-point converter; Lee [0219]: The adder tree 1300 may perform adding operations on the floating-point format multiplication result data M0_FIX-M7_FIX that is output from the floating-point-to-fixed-point converters FFCO-FFC7. Because the multiplication result data M0_FIX-M7_FIX have fixed-point formats in which the position of a binary point is fixed, the adder tree 1300 may be configured as a fixed-point adder tree)
adding, by the fixed-point adder circuity of the multi-input multi-output adder, a first source operand and a second source operand to generate a first summed operand; (Lee [0219]: The adder tree 1300 may perform adding operations on the floating-point format multiplication result data M0_FIX-M7_FIX that is output from the floating-point-to-fixed-point converters FFCO-FFC7. Because the multiplication result data M0_FIX-M7_FIX have fixed-point formats in which the position of a binary point is fixed, the adder tree 1300 may be configured as a fixed-point adder tree)
converting, by an absolute value converter coupled to an output of the fixed-point adder circuity, an output result from the fixed-point adder circuity into an unsigned number result and outputting a symbol thereof; (Lee [0337]: FIG. 55 illustrates an embodiment of the fixed-point-to-floating-point converter 3500 in the MAC operator 3000 of FIG. 50. As described with reference to FIG. 50, the fixed-point-to-floating-point converter 3500 may convert the fixed-point format first multiplication-accumulation data M_ACC_FIX[31:0] transmitted from the accumulator (3400 of FIG. 50) into floating-point format to output floating-point format MAC result data; Lee [0339]: The 2′s complement circuit 3510 may receive the remaining 31-bit data M_ACC_FIX[30:0] of the fixed-point format multiplication-accumulation data M_ACC_FIX[31:0] transmitted from the accumulator (3400 of FIG. 50) except for the MSB, which is the sign bit, and generate and output 2′s complement of the 31-bit data M_ACC_FIX[30:0])
detecting, by a leading 1 detector coupled to an output of the absolute value converter, a starting bit position of a first 1 of the unsigned number result; (Lee [0341]: The MSB 1 detector 3530 may detect a position of the MSB 1 in the output data OUT[30:0] transmitted from the multiplexer 3520. Here, “MSB 1” may be defined as a most significant bit among the bits with a binary value of “1” in the output data OUT[30:0])
and combining, by an exponent updater, the final mantissa, the symbol from the absolute value converter, and an exponent value derived from the starting bit position to generate a final floating-point result, (Lee [0343]: the floating-point format MAC result data MAC_RST_FLT[31:0]; Lee Fig. 55: shows the sign, exponent, and mantissa being combined)
whereby the intermediate calculation process is performed by the fixed-point adder circuity without requiring normalization and rounding at each addition stage, thereby improving a hardware speed of the multi-input multi-output floating-point operation (Lee [0219]: the adder tree 1300 may be configured as a fixed-point adder tree. Accordingly, overhead of energy and latency due to alignment, normalization, and rounding in the floating-point adder tree may be reduced, and circuit area may also be reduced).
Lee fails to teach performing, by the fixed-point adder circuity, a direct truncation on at least one last bit of the first summed operand and subsequently performing, by the fixed-point adder circuity, a right shift on the first truncated-summed operand to generate a first shifted-summed operand.
However, Langhammer 1 teaches performing, by the fixed-point adder circuity, a direct truncation on at least one last bit of the first summed operand (Langhammer 1 [0036]: Therefore, in some embodiments, to control the growth of the results of an arithmetic operation, and therefore packing, the operands 201 at each stage (e.g., 208A-208C) or a subset of the stages 208 may be truncated)
[subsequently performing,] by the fixed-point adder circuity, a right shift on the first truncated-summed operand to generate a first shifted-summed operand (Langhammer 1 [0036]: For example, soft logic circuitry (e.g., logic within the LAB) may right-shift the operands 201 by a bit to truncate the LSBs).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee with the truncation and shifting of Langhammer 1. One of ordinary skill in the art would be motivated to make this combination because it would control the growth of the results of an arithmetic operation as taught by Langhammer 1 reducing storage costs (Langhammer 1 [0036]). Also, as a result, arithmetic operations may pack more efficiently onto an integrated circuit with increased precision and performance as taught by Langhammer 1 (Langhammer 1 [0025]).
Lee in view of Langhammer 1 fails to teach That the right shift is performed subsequently to the truncation.
However, Okutomi does teach that the right shift of Lee in view of Langhammer 1 is performed subsequently to the truncation (Okutomi Page 11 Paragraph 6: the right shift of s bits of X. At this time, the lower s bits of X are truncated. That is, before X is divided by M (before X is shifted to the right by s bits)).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 with performing the right shift subsequently to the truncation as taught by Okutomi. One of ordinary skill in the art would be motivated to make this combination because it would make sure the results are aligned properly, making calculations more accurate.
Lee in view of Langhammer 1 further in view of Okutomi fails to teach shifting, by a left shifter coupled to the leading 1 detector, the unsigned number result based on the starting bit position to generate a normalized mantissa; rounding, by a rounder coupled to an output of the left shifter, the normalized mantissa to generate a final mantissa conforming to a target floating-point format.
However, Langhammer 2 teaches shifting, by a left shifter coupled to the leading 1 detector, the unsigned number result based on the starting bit position to generate a normalized mantissa; (Langhammer 2 Column 5 Lines 16-18: (if signed numbers are used, leading 1's may be counted as well), and using the leading 0 count 217 to left-shift mantissa 213 at 227)
rounding, by a rounder coupled to an output of the left shifter, the normalized mantissa to generate a final mantissa conforming to a target floating-point format; (Langhammer 2 Column 5 Lines 19-21: Normalized mantissa 223 is then rounded, in a manner which may be well-known, by examining one or more rounding bits).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi with the left shifter and rounder as taught by Langhammer 2. One of ordinary skill in the art would be motivated to make this combination because it would allow for the mantissas to be normalized and rounded, increasing the flexibility of the system as the result could then be used with other conventional components.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 further in view of Lo et al. (US 20190347072 A1) hereinafter Lo.
With regards to claim 9, Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 teaches all of the limitations of claim 7 above. Lee fails to teach wherein when a number of the maximum exponent extractor circuit is multiple, the floating- point operands received by each of the maximum exponent extractor circuits are a plurality of floating-point operands that have been divided into a plurality of groups and wherein each of the maximum exponent extractor circuits is configured to receive a respective one of the plurality of groups.
However, Langhammer 1 teaches wherein when a number of the maximum exponent extractor circuit is [multiple,] (Langhammer 1 [0081]: The block floating point exponents from each block floating point tree (e.g., 800A-C) may be sorted by a circuit 902, which may select and output the maximum block floating point exponent received from the block floating point trees 800A-C).
the floating- point operands received by each of the maximum exponent extractor circuits are a plurality of floating-point operands [that have been divided into a plurality of groups] (Langhammer 1 [0081]: The block floating point exponents from each block floating point tree (e.g., 800A-C) may be sorted by a circuit 902, which may select and output the maximum block floating point exponent received from the block floating point trees 800A-C)
and wherein each of the maximum exponent extractor circuits is configured to receive a respective one [of the plurality of groups] (that have been divided into a plurality of groups] (Langhammer 1 [0081]: The block floating point exponents from each block floating point tree (e.g., 800A-C) may be sorted by a circuit 902, which may select and output the maximum block floating point exponent received from the block floating point trees 800A-C).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 with the alignment as taught by Langhammer 1. One of ordinary skill in the art would be motivated to make this combination because it would control the growth of the results of an arithmetic operation as taught by Langhammer 1 reducing storage costs (Langhammer 1 [0036]). Also, as a result, arithmetic operations may pack more efficiently onto an integrated circuit with increased precision and performance as taught by Langhammer 1 (Langhammer 1 [0025]). Also, it would make sure that the operands are aligned, making calculations more efficient.
Lee in view of Langhammer 1 fails to teach that there are multiple maximum exponent extractor circuits, [the floating- point operands received by each of the maximum exponent extractor circuits are a plurality of floating-point operands] that have been divided into a plurality of groups, [and wherein each of the maximum exponent extractor circuits is configured to receive a respective one] of the plurality of groups.
However, Lo teaches that there are multiple maximum exponent extractor circuits (Lo [0106]: selecting the shared exponent value by determining one of a maximum exponent value or a minimum exponent value based at least on the identified exponent values to define a global shared exponent and a finer granularity shared exponent for each of the grouped mantissas).
[the floating- point operands received by each of the maximum exponent extractor circuits are a plurality of floating-point operands] that have been divided into a plurality of groups (Lo [0106]: selecting the shared exponent value by determining one of a maximum exponent value or a minimum exponent value based at least on the identified exponent values to define a global shared exponent and a finer granularity shared exponent for each of the grouped mantissas)
[and wherein each of the maximum exponent extractor circuits is configured to receive a respective one] of the plurality of groups (Lo [0106]: selecting the shared exponent value by determining one of a maximum exponent value or a minimum exponent value based at least on the identified exponent values to define a global shared exponent and a finer granularity shared exponent for each of the grouped mantissas).
Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to combine the teachings of Lee in view of Langhammer 1 further in view of Okutomi further in view of Langhammer 2 with the multiple exponent extractors as taught by Lo. One of ordinary skill in the art would be motivated to make this combination because as such, finer-grained shared exponents can be realized efficiently on, for example, a block floating point accelerator that can improve accuracy as taught by Lo (Lo [0050]). Also, This would allow for multiple conversions to happen in parallel speeding up operations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jakob O Gudas whose telephone number is (571)272-0695. The examiner can normally be reached Monday-Thursday: 7:30AM-5:00PM Friday: 7:30AM-4:00PM.
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/J.O.G./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151