Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
Applicant's arguments filed 12/1/2025 have been considered but are moot in view of the new ground(s) of rejection. Please see the 35 USC 112(a) rejection below.
The 35 USC 112(a) rejection is introduced in light of the newly added claim limitations. The previous rejections which teach the claim limitations other than the newly non-enabled claim limitations highlighted in the 112 rejection below are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 9, and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Each of the above claims recites limitations pertaining to the (enumeration) terminal being reconfigured, after the enumeration process has completed, for non-enumeration functions and to output signals associated with non-enumeration functions.
The Specification (as originally filed, 12/09/2021) discusses this dual use terminal in the following paragraphs: 1060, 1061, and 1064. This embodiment, along with the claim limitations of “a resistor external to the peripheral device”, is directed to Figure 16 for support in the Drawings.
However, the Examiner contends that, despite discussing this functionality, the dual-purpose functionality of the claimed terminal is not enabled by the Specification/Drawings.
The Specification at paragraph 1061 states: “In an embodiment an external resistor is connected to the designated enumeration pin (also referred to herein as terminal), ENUM, of each peripheral device.”
However, the Specification is devoid of teachings to enable one skilled in the art to use the ENUM pin of the peripheral devices of Figure 16 as an output terminal at any point in time since the ENUM pin is directly connected to ground via a resistor 1612 externally from the peripheral device. Within the peripheral device, the terminal is connected to a current source 1610 and an ADC 1614 (or alternatively, a flash converter as described in paragraph 1061) which is used to generate the device address of the peripheral device. Neither of these internal connections support the reconfiguration of the pin for non-enumeration use or to be used as an output pin/terminal. Additionally, the ENUM pin of Figure 18 is also directly connected to ground via resistor 1806 externally from the peripheral device, and similarly lacks support within the peripheral device for reconfiguration of the ENUM pin/terminal for non-enumeration or output purposes.
Therefore, claims 1, 9, and 18 are not enabled to reconfigure the claimed terminal(s) to be used as outputs and/or for non-enumeration functions during operation of the peripheral device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-5, 7-15, 17, 18, 20-22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Booth et al. U.S. Patent No. 9,213,396 in view of Richards et al. U.S. PGPUB No. 2009/0031048 in further view of Davis U.S. Patent No. 9,214,950.
Per Claim 1, Booth discloses a peripheral device (toner bottle 105) comprising: a terminal (power connection 112) coupled to a resistor external to the peripheral device (Col. 4 lines 37-62, Figures 1 and 2; Resistors 208/210 are coupled to terminal 112 and also may be integrated into the IC package instead of internal to module 104.); a current source coupled to the terminal to provide current to the terminal, the current source included in the peripheral device (Col 7 lines 47-61, Figure 7; The operating voltage may be generated by a linear regulator, utilizing a tolerance of 5% over a range of operating currents, 0mA to 10mA. Thus a current source is inherently present in the device 105.); a controller configured to determine an address based at least in part on a voltage at the terminal generated by the current applied to the terminal, the address determined independently of signaling from an external controller in communication with the peripheral device (Col. 3 line 66 – Col. 4 line 53, Figure 2; Authentication circuit 202 utilizes the voltage provided by the voltage divider to generate a serial communication address for the authentication circuit 202.); an address register to store the address, the address to identify the peripheral device on a bus (Col. 4 lines 54-67; “stored in non-volatile memory located within a module”; Col. 3 lines 8-35, Figure 1, I2C bus); and the resistor external to the peripheral device connected via the terminal to ground (Col. 4 lines 37-62, Figures 1 and 2; Resistor 210 is coupled to ground and also may be integrated into the IC package instead of internal to module 104.).
Booth further teaches that authentication circuit 202 comprises an analog-to-digital converter for outputting an address value to be assigned to the module (Col. 4 lines 24 – Col. 5 line 6; Vcc 206 represents a reference voltage.). Despite teaching that the ADC could comprise a comparator (Col. 4 lines 42-47), Booth does not expressly teach the claimed flash converter, current usage, or plurality of reference resistors.
However, Richards similarly discloses assigning an address to a bus module through use of external voltages, resistors, and an ADC (Paragraphs 23-26). Richards further teaches the internal reference voltage one of a plurality of generated internal reference voltages generated using a plurality of reference resistors with each reference voltage of the plurality of generated internal reference voltages being associated with a different peripheral device (Paragraphs 7, 8, 27, 32, 33; Figures 3 and 4; Flash converter with a resistance ladder). Richards also teaches that voltage/current values can be used interchangeably (Paragraphs 7, 8, and 27) and that the plurality of reference resistors connected to a plurality of inverting inputs of a corresponding plurality of comparators and a resistor connected via a terminal between ground and a plurality of noninverting inputs of the plurality of comparators (Figure 3 discloses reference resistors 344 connected to inverting inputs “-“ of comparators 342 and resistor 116 connected to ground (via switch 346) and also connected to each non-inverting input of each comparator 342.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the above teachings of Booth and Richards because a flash converter is a well-known type of analog-digital converter that offers higher speed conversions compared to other types of ADC’s.
Davis further teaches a temperature compensated flash ADC (Abstract) where a resistance ladder 322 and comparators 326 are used with an input voltage 321 and reference current 324 to output a digital signal (Col. 5 line 31 – Col. 6 line 23; biasing transistors 401; Figures 3 and 4).
- It further would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine Davis’s temperature compensated flash ADC teachings with the flash ADC of Richards because Richards already teaches that voltage/current could be used interchangeably and Davis teaches the resistance ladder utilizing a reference current and biasing transistors. This would have been obvious since it has been held that the simple substitution of one known element (voltage) for another (current) to obtain predictable results is obvious to one of ordinary skill. See MPEP 2141, section III(B).
Per Claims 3, 11, and 20, Booth discloses the peripheral device as recited in claim 1 wherein the peripheral device responds to a command on the bus containing the address in an address field of the command in accordance with the command (Col. 7 lines 47-67, Figure 7).
Per Claims 4, 5, 14, 15, 21, and 22, Booth does not explicitly state the triggering step for performing the address assignment process.
However, Richards similarly discloses an address assignment technique for modules located on an I2C bus (Paragraph 30), wherein the address assignment takes place responsive to a power on condition (Paragraph 23; startup) or a reset (Paragraph 23; power-on-reset).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform the address assignment step after either a power-on condition or a reset, as taught by Richards, because systems that allow connection of new devices are often reset, or cycled power, to initialize the newly connected device and configure it for communication.
Per Claim 7, Booth discloses the peripheral device as recited in claim 1 wherein the controller determines the address based at least in part on a mapping between a resistor value of the resistor and address values, the resistor value determined based at least in part on the voltage at the terminal (Col. 4 lines 37-53).
While Booth discloses various address values corresponding to different voltages, Booth does not specifically disclose the use of a “table” for the mapping.
However, Richards discloses the use of tables to map peripheral addresses and voltages (Paragraphs 25 and 33; Figure 4).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for Booth to implement a look-up table to perform the mapping of the addresses and voltages, as taught by Richards, because a look-up table is easy to implement such a mapping when the address values and their corresponding voltage ranges are known in advance.
Per Claims 8 and 17, Booth discloses the peripheral device as recited in claim 1 further comprising a communication interface coupled to the bus, the communication interface including, a clock terminal and a serial data terminal (Col. 2 lines 51-67, Figure 1; An I2C bus protocol is implemented, comprising clock 116 and data 118 terminals).
Booth does not specifically teach serial data in/out terminals and a chip select terminal.
However, Richards discloses the slave addressing scheme being possible with a plurality of different serial buses, including I2C and Serial Peripheral Interface (SPI) bus (Paragraph 30; Serial data bus 126 may be a Serial Peripheral Interface (SPI) Bus, which inherently comprises system clock (SCLK), master out slave in (MOSI), master in slave out (MISO), and slave/chip select (SS) signals.).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the teachings of Booth with an SPI bus in place of the I2C bus, as taught by Richards. This would have been obvious since it has been held that known work in a field of endeavor may prompt variations of it for use in the same field of endeavor based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art. In this case, it would have been obvious to one of ordinary skill in the art to want to implement the slave addressing teachings of Booth in a system using an SPI bus in lieu of an I2C bus, such as the system taught by Richards. See MPEP 2141, section III(F).
Per Claim 9, Booth discloses a communication system for auto-enumeration of devices on a bus (Col. 2 lines 51-60, I2C bus), the communication system comprising: a plurality of devices coupled to the bus (Figure 1, 105 and 119); a first device (105) of the plurality of devices including a first terminal coupled to a first resistor (Col. 4 lines 37-62, Figures 1 and 2; Resistors 208/210 are coupled to terminal 112 and also may be integrated into the IC package instead of internal to module 104.), a first current source coupled to the first terminal to provide a first current to the first terminal, the first current source included in the first device (Col 7 lines 47-61, Figure 7; The operating voltage may be generated by a linear regulator, utilizing a tolerance of 5% over a range of operating currents, 0mA to 10mA. Thus, a current source is inherently present in the device 105.), a first controller configured to determine a first address based at least in part on a first voltage at the first terminal generated by the first current applied to the first terminal, the first address determined independently of signaling from an external controller in communication with the first device through the bus (Col. 3 line 66 – Col. 4 line 53, Figure 2; Authentication circuit 202 utilizes the voltage provided by the voltage divider to generate a serial communication address for the authentication circuit 202.), and a first address register to store the first address (Col. 4 lines 54-67; “stored in non-volatile memory located within a module”), and the first resistor external to the peripheral device connected via the terminal to ground (Col. 4 lines 37-62, Figures 1 and 2; Resistor 210 is coupled to ground and also may be integrated into the IC package instead of internal to module 104.); and a second device of the plurality of devices including a second terminal coupled to a second resistor, a second current source coupled to the second terminal to provide a second current to the second terminal, the second current source included in the second device, a second controller configured to determine a second address based at least in part on a second voltage at the second terminal generated by the second current applied to the second terminal, the second address determined independently of signaling from the external controller in communication with the second device through the bus, and a second address register to store the second address (The mappings provided for the first device 105 are equally applicable to the second device 119.).
Booth further teaches that authentication circuit 202 comprises an analog-to-digital converter for outputting an address value to be assigned to the module (Col. 4 lines 24 – Col. 5 line 6; Vcc 206 represents a reference voltage.). Despite teaching that the ADC could comprise a comparator (Col. 4 lines 42-47), Booth does not expressly teach the claimed flash converter, current usage, or plurality of reference resistors.
However, Richards similarly discloses assigning an address to a bus module through use of external voltages, resistors, and an ADC (Paragraphs 23-26). Richards further teaches the internal reference voltage one of a plurality of generated internal reference voltages generated using a plurality of reference resistors with each reference voltage of the plurality of generated internal reference voltages being associated with a different peripheral device (Paragraphs 7, 8, 27, 32, 33; Figures 3 and 4; Flash converter with a resistance ladder). Richards also teaches that voltage/current values can be used interchangeably (Paragraphs 7, 8, and 27) and that the first plurality of reference resistors connected to a plurality of inverting inputs of a corresponding first plurality of comparators and the first resistor connected via a terminal between ground and a first plurality of noninverting inputs of the first plurality of comparators (Figure 3 discloses reference resistors 344 connected to inverting inputs “-“ of comparators 342 and resistor 116 connected to ground (via switch 346) and also connected to each non-inverting input of each comparator 342.)
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the above teachings of Booth and Richards because a flash converter is a well-known type of analog-digital converter that offers higher speed conversions compared to other types of ADC’s.
Davis further teaches a temperature compensated flash ADC (Abstract) where a resistance ladder 322 and comparators 326 are used with an input voltage 321 and reference current 324 to output a digital signal (Col. 5 line 31 – Col. 6 line 23; biasing transistors 401; Figures 3 and 4).
- It further would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine Davis’s temperature compensated flash ADC teachings with the flash ADC of Richards because Richards already teaches that voltage/current could be used interchangeably and Davis teaches the resistance ladder utilizing a reference current and biasing transistors. This would have been obvious since it has been held that the simple substitution of one known element (voltage) for another (current) to obtain predictable results is obvious to one of ordinary skill. See MPEP 2141, section III(B).
Per Claim 10, Booth discloses utilizing a resistor (Col. 4 lines 37-53), but does not specifically teach different resistor values.
However, Richards teaches utilizing different resistor values to achieve different slave address values (Paragraph 25).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the system of Booth with varying resistor values between the two resistors, as taught by Richards, because the different resistor values allow for variations in slave addressing in the event that a common input voltage is utilized for multiple slave devices.Per Claims 12 and 13, Booth teaches coupling devices to the I2C bus, and I2C bus is well known to support up to 128 devices. Booth further teaches different voltage levels connecting the two devices (Col. 3 lines 36-58). Booth doesn’t specify a linear/non-linear spacing to the voltages, however, Richards further teaches unique external resistance values to define different analog voltages representative of desired device addresses (Figure 4).
Per Claim 18, please refer to the above rejection of claim 1 as the limitations are substantially similar and the mapping of limitations is equally applicable.
Per Claim 24, Booth discloses the method as recited in claim 18 wherein the address is based at least in part on a resistance of the resistor coupled to the terminal (Col. 4 lines 37-53).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175