Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This action is in response to application amendments filed 2-2-2026.
2. Claims 1 - 3, 5 - 11 are pending. Claim 1 has been amended. Claim 4 has been canceled. Claim 1 is independent. This application was filed on 12-10-2021.
Response to Arguments
3. Applicant’s arguments, see Arguments/Remarks Made in an Amendment, filed 8-4-2025, with respect to the rejection(s) under Soryal in view of Wright and further in view of Shinjo and Minematsu have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Soryal in view of Wright and further in view of Klier and Shinjo and JP4693245.
A. The 112 Rejection is withdrawn due to claim amendments to remove the term “real time” from the claim language.
B. The 101 Rejection for Claim 1 - 11 has been maintained due to the claim amendments still directed to an abstract idea and don’t recite significantly more to integrate the abstract idea into a practical application with a technological improvement (see details below).
C. Applicant argues on page 8 of Remarks: ... cannot suggest or teach the result of counting numerals in a matrix.
The Examiner respectfully disagrees. Klier discloses the capability for generating a total count for each character included within a character string. (see Flier paragraph [0106]: Each yaintvec is associated with a certain substring of s or t, and will be used to keep track of the total count, within that string, of each character in the alphabet. (total count “0” and “1” and any other character present); (selected: the numerals "0" and "1" in at least one row of the data matrix))
D. Applicant argues on page 8 of Remarks: ... there is no motivation to combine the
documents together, ... .
The Examiner respectfully disagrees. A 103 rejection based on multiple references is a legitimate technique according to the MPEP. The 103 rejection allows portions of the rejection citations for a claimed invention to come from different prior art references. The rejection to each independent and dependent claim includes a citation from the referenced prior art that discloses the basis for the rejection. Each obviousness combination clearly indicates the claim limitation(s) the combined referenced prior art teaches. In addition, a cited passage from the referenced prior art indicates the motivation for the obviousness combination. Each obviousness combination’s disclosure is equivalent to the Applicant’s claim limitation(s) for the claimed invention.
Achieved advantage is a valid motivation for the combination of referenced prior art. The rejection of each referenced prior art combination states a motivation for the combination, which translates to an achieved advantage for the combination.
E. Applicant argues on page 9 of Remarks: ... count of the digits is a numerical count ... .
The Examiner respectfully disagrees. Klier discloses the capability for generating a total count for each included character within a character string. (see Flier paragraph [0106]: Each yaintvec is associated with a certain substring of s or t, and will be used to keep track of the total count, within that string, of each character in the alphabet. (total count “0” and “1” and any other character present); (selected: the numerals "0" and "1" in at least one row of the data matrix))
The Examiner is reiterating the following:
Soryal discloses a checksum. (see Soryal paragraph [0018], lines 1-23: security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations; a checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm))
Wright discloses utilizing numerals (such as “0”s and “1”s) and their particular order to form a key. (see Wright col 8, lines 5-24: Each of the samples is then preferably coded to form coded data or preferably a parity bit set; one parity bit is chosen for each half of each sample to make the overall parity even; a sample containing the following bits "1011" would be reduced to a parity digit "10"; The first half of the sample "10" includes only an odd number of 1 bits, thus another "1" must be added to make the parity even; The second half of the sample "11" includes an even number of "1" bits so that adding a "0" bit will maintain the even parity; Thus the sample "1011" is coded into the dibit "10"; Each sample is then similarly coded to form a new array of coded data with the dibits (CD0, CD1, . . . CD39) replacing the corresponding samples (NO, N1, . . . N39) of the array 134; For each row and column new array, a checksum may then preferably be performed to combine the entries of coded data of each row and column to form respective row and column vectors; (selected: the numerals "0" and "1" in at least one row of the data matrix so that the number of appearances of each numeral is sequentially placed); (bits comprising 0s and 1s are sequentially processed to determine an output stream (such as a row of data) comprising input data and parity bits associated with the processed (counted) bits 0s and 1s inputted))
And, Wright discloses the generation of a checksum value within can be utilized for verification operations. (see Wright col 8, lines 5-24: Each of the samples is then preferably coded to form coded data or preferably a parity bit set; one parity bit is chosen for each half of each sample to make the overall parity even; a sample containing the following bits "1011" would be reduced to a parity digit "10"; The first half of the sample "10" includes only an odd number of 1 bits, thus another "1" must be added to make the parity even; The second half of the sample "11" includes an even number of "1" bits so that adding a "0" bit will maintain the even parity; Thus the sample "1011" is coded into the dibit "10"; Each sample is then similarly coded to form a new array of coded data with the dibits (CD0, CD1, . . . CD39) replacing the corresponding samples (NO, N1, . . . N39) of the array 134; For each row and column new array, a checksum may then preferably be performed to combine the entries of coded data of each row and column to form respective row and column vectors; (selected: the numerals "0" and "1" in at least one row of the data matrix so that the number of appearances of each numeral is sequentially placed); (bits comprising 0s and 1s are sequentially processed to determine an output stream (such as a row of data) comprising input data and parity bits associated with the processed (counted) bits 0s and 1s inputted))
Claim Rejections - 35 USC § 101
4. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
5. Claims 1 - 3, 5 - 11 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites “counting at least one of: the numerals "0" and "1" in at least one row of the data matrix, the numerals "0" and "1" in at least one column of the data matrix, the numerals "0" and "1" in at least one left diagonal of the data matrix, and the numerals "0" and "1" in at least one right diagonal of the data matrix; ordering the number of appearances of each numeral to form a key; and sequentially positioning the key so as to assemble the checksum”. The associated dependent claims, claims 2, 3, 5 - 11, do not correct the 101 deficiencies
The above limitations correspond to generic computer components (such as the processing circuitry) performing generic computer functions such as counting and processing inputs. Accordingly, the claim recites an abstract idea. Additional claims recite the additional elements of “XOR” operations, “XNOR” operations, and dividing a data portion into two data portions, to perform the processing steps. However, these additional elements are recited at a high-level of generality and processed by generic computers or computer components such that they amount to no more than mere instructions to apply the exception using a generic computer. Mere instructions to apply an exception using a generic computer cannot provide an inventive concept. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Considering the claim as a whole, looking at the elements individually and in an ordered combination, does not integrate the abstract idea into a practical application using the considerations set forth above. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements are recited at a high-level of generality and performed by generic computer components such that they amount to no more than mere instructions to apply the exception using a generic computer. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. There are no well-understood, routine, and conventional additional elements recited in the claim. Thus, the claimed elements, either individually, or in the ordered combination do not add significantly more to the abstract idea.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1 - 3, 9 - 11 are rejected under 35 U.S.C. 103 as being unpatentable over Soryal et al. (US PGPUB No. 20200067983) in view of Wright et al. (US Parent No. 5,615,222) and further in view of Klier et al. (US PGPUB No. 20050267885) and Shinjo et al. (Patent No. WO 2009090697 A1) and JP4693245 (Patent No. JP 4693245 B2).
Regarding Claim 1, Soryal discloses a computer implemented method for verifying a data source and executing program instructions comprising: comprising:
a) receiving, by a processing circuit, the data source associated with the program instructions; (see Soryal paragraph [0037]: Discrepancy detector 252 of security controller 120 is a computer program that detects discrepancies between one or more security sequences 282 (data utilized for checksum) received and/or generated by security controller 120.; (security sequence(s) received); paragraph [0056]: Processing circuitry 420 (e.g., processor 260 of FIG. 2) performs or manages the operations of the component. Processing circuitry 420 may include hardware and/or software. Examples of a processing circuitry include one or more computers, one or more microprocessors, one or more applications, etc. In certain embodiments, processing circuitry 420 executes logic (e.g., instructions) to perform actions (e.g., operations), such as generating output from input.; paragraph [0023]: Network controller 130 may store security configurations for each type of network node 140 that may be generated by network controller 130. For example, network controller 130 may include a database that stores a security configuration for each of a certain number of potential network nodes, including network node 140, for network 110.; (data source for information))
d) each numeral to form a key; (Soryal para 18-22, sequence may be encoded into a longer sequence… that includes the key), and e) sequentially positioning the key to assemble matrix; (see Soryal paragraph [0018], lines 1-23: security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations; a checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm); paragraph [0022], lines 1-11: controller generates security sequence using a checksum algorithm; Security sequence represents a security configuration of network node; Network controller generates security sequence in response to receiving key from security controller; Security sequence may be encoded into a longer sequence that includes the key; (key positioned in sequence with other parameter values, sequentially positioned the key)) and
e) verifying whether the checksum generated from the data matrix is comparable to a stored checksum associated with the data source wherein the data source is verified. (see Soryal paragraph [0030]: After receiving security sequence 160 from network controller 130 and security sequence 162 from network node 140, security controller 120 generates security sequence 164 (checksum) based on the stored security configuration for network node 140. Security controller 120 then compares security sequence 160, security sequence 162, and security sequence 164. Based on the comparison, if security controller 120 detects a discrepancy between security sequence 160, security sequence 162, and security sequence 164, which may be any difference between security sequence 160, security sequence 162, and/or security sequence 164, security controller 120 determines that the security confirmation of network node 140 has been modified. In the event security controller 120 determines that network node 140 has been modified, security controller 120 may generate an alarm to an operator of network 110 and/or isolate network node 140 from network 110.; paragraph [0018], lines 1-23: security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations; a checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm); paragraph [0022], lines 1-11: controller generates security sequence using a checksum algorithm; including a data source) in real time. (see Soryal paragraph [0018]: A security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations. A checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm). The checksum algorithm will output a different checksum for any change made to the checksum algorithm's input. ... A security sequence may represent a security configuration of a node of network 110.))
Soryal does not specifically disclose for f) executing the program instructions by the processing circuit only upon verification between the generated checksum and the stored checksum and preventing execution of the program instructions if the data source is not verified.
However, JP4693245 discloses:
f) executing the program instructions by the processing circuit only upon verification between the generated checksum and the stored checksum; and preventing execution of the program instructions if the data source is not verified. (see JP4693245 paragraph [0013]: The comparison is performed as follows. A checksum generated at the end of execution of the first instruction is stored in the CPU memory as a final checksum. In order to confirm whether or not an illegal operation of the CPU has been performed between the execution of the first instruction and the loading of the next second instruction to the CPU, as described above, In parallel, a start checksum is generated. In the first step, a), the start checksum is compared by the comparator with the final checksum stored in memory from the first instruction executed previously. When the CPU does not perform an illegal operation, the start checksum and the final checksum match, and the value of the comparison result is zero. The comparator outputs a signal, and according to this signal, the currently available checksum is stored in the memory as a new final checksum in the second step, b) after the execution of the second instruction. That is, in this case, the execution of the second instruction is not interrupted. However, if a non-zero value is obtained by comparing the start checksum and the final checksum, it must be estimated that the CPU has been tampered with. Therefore, the output signal of the comparator does not proceed to the second step, b), and in the example shown in FIG. 2, the error message c) that causes the instruction processing to abort is issued.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for f) executing the program instructions by the processing circuit only upon verification between the generated checksum and the stored checksum and preventing execution of the program instructions if the data source is not verified. as taught by JP4693245. One of ordinary skill in the art would have been motivated to employ the teachings of JP4693245 for the benefits achieved from enhanced security of a system that enables program instruction only after a verification sequence for checksum parameters. (see JP4693245 paragraph [0013])
Furthermore, Soryal does not specifically disclose for b) converting the data source into a binary file organized as a data matrix in which numerals “0” and “1” are presented and ordering the number of appearances of each numeral
However, Wright discloses:
b) converting, by the processing circuit, the data source into a binary file structured as a data matrix in which numerals “0” and “1” are presented within each cell of the data matrix and ordering the number of appearances of each numeral. (see Wright col 8, lines 5-24: Each of the samples is then preferably coded to form coded data or preferably a parity bit set; one parity bit is chosen for each half of each sample to make the overall parity even; a sample containing the following bits "1011" would be reduced to a parity digit "10"; The first half of the sample "10" includes only an odd number of 1 bits, thus another "1" must be added to make the parity even; The second half of the sample "11" includes an even number of "1" bits so that adding a "0" bit will maintain the even parity; Thus the sample "1011" is coded into the dibit "10"; Each sample is then similarly coded to form a new array of coded data with the dibits (CD0, CD1, . . . CD39) replacing the corresponding samples (NO, N1, . . . N39) of the array 134; For each row and column new array, a checksum may then preferably be performed to combine the entries of coded data of each row and column to form respective row and column vectors; (selected: the numerals "0" and "1" in at least one row of the data matrix); (bits comprising 0s and 1s are sequentially processed to determine an output stream (such as a row of data) comprising input data and parity bits associated with the processed (counted) bits 0s and 1s inputted))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for b) converting the data source into a binary file organized as a data matrix in which numerals “0” and “1” are presented as taught by Wright. One of ordinary skill in the art would have been motivated to employ the teachings of Wright to sum parameters utilizing a sequential order for data processing and generating a parameter such as a checksum value. (see Wright col 8, lines 5-24)
Although Soryal does disclose the generation of a checksum value utilizing a set of generated parameters, Soryal does not specifically disclose the generation of a checksum utilizing the procedure for c) counting at least one of:
the numerals "0" and "1" in at least one row of the data matrix,
the numerals "0" and "1" in at least one column of the data matrix,
the numerals "0" and "1" in at least one left diagonal of the data matrix, and
the numerals "0" and "1" in at least one right diagonal of the data matrix, and ordering the number of appearances of each numeral.
Soryal-Wright does not specifically disclose for c) in the data matrix performing a numeric count of at least one of:
the numerals "0" and "1" in at least one row of the data matrix,
the numerals "0" and "1" in at least one column of the data matrix,
the numerals "0" and "1" in at least one left diagonal of the data matrix, and the numerals "0" and "1" in at least one right diagonal of the data matrix
However, Flier discloses for c) in the data matrix performing a numeric count of at least one of: the numerals "0" and "1" in at least one row of the data matrix, and for d) the numeric count.
the numerals "0" and "1" in at least one column of the data matrix,
the numerals "0" and "1" in at least one left diagonal of the data matrix, and the numerals "0" and "1" in at least one right diagonal of the data matrix. (see Flier paragraph [0106]: Each yaintvec is associated with a certain substring of s or t, and will be used to keep track of the total count, within that string, of each character in the alphabet. (total count “0” and “1” and any other character present); (selected: the numerals "0" and "1" in at least one row of the data matrix))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for c) in the data matrix performing a numeric count of at least one of: the numerals "0" and "1" in at least one row of the data matrix, and for d) the numeric count as taught by Flier. One of ordinary skill in the art would have been motivated to employ the teachings of Flier for the benefits achieved from the flexibility of a system that enables multiple parameters such as a total count characters in the generation and processing of checksum values. (see Flier paragraph [0106])
Furthermore, Soryal does not specifically disclose for d) sequentially placing the number of appearances resulting from the numeric count of each numeral in at least one row, column, left diagonal, and a right diagonal to generate a row key, a column key, a left diagonal key, and a right diagonal key, respectively.
However, Shinjo discloses wherein for d) sequentially placing the number of appearances resulted from processing of each numeral in at least one row, column, left diagonal, and a right diagonal to generate a row key, a column key, a left diagonal key, and a right diagonal key, respectively. (see Shinjo page 5: combining a plurality of keys as a key string and making the last key of the key string unique without duplication, an index key composed of a plurality of key strings is obtained as a unique key. Configure as. Then, the second position information indicating the position of the storage area where the unique key is arranged is stored in the leaf node of the above-mentioned coupled node tree. The search key is a combination of a plurality of keys as a key string, and the last key of the key string is a unique search key string. The branch node has a first discrimination position indicating the position information of the key to be compared in the search key string for performing the bit string search and a second discrimination position indicating the discrimination bit position of the key.)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for d) sequentially placing the number of appearances resulted from the numeric count of each numeral in at least one row, column, left diagonal, and a right diagonal to generate a row key, a column key, a left diagonal key, and a right diagonal key, respectively as taught by Shinjo. One of ordinary skill in the art would have been motivated to employ the teachings of Shinjo for the flexibility of a system that enables multiple key string sequences within a bit sequence for key sequence processing. (see Shinjo page 5)
Regarding Claim 2, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 1, including counting the numerals is performed in a predetermined order. (see Soryal paragraph [0018], lines 1-23: security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations; a checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm); paragraph [0022], lines 1-11: controller generates security sequence using a checksum algorithm; Security sequence represents a security configuration of network node; Network controller generates security sequence in response to receiving key from security controller; Security sequence may be encoded into a longer sequence that includes the key; (key positioned in sequence with other parameter values); Network controller transmits security sequence to security controller; paragraph [0027], lines 1-10: Network node may run a dynamic algorithm to generate security sequence; Security sequence may be a long checksum; Security sequence may be encoded into a longer sequence that includes key; (key inserted within the sequence of parameters comprising the checksum))
Soryal does not specifically disclose counting the numerals "0" and "1".
However, Flier discloses wherein counting the numerals "0" and "1" is performed. (see Flier paragraph [0106]: Each yaintvec is associated with a certain substring of s or t, and will be used to keep track of the total count, within that string, of each character in the alphabet. (total count “0” and “1” and any other character present); (selected: the numerals "0" and "1" in at least one row of the data matrix))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for counting the numerals "0" and "1" as taught by Flier. One of ordinary skill in the art would have been motivated to employ the teachings of Flier for the benefits achieved from the flexibility of a system that enables multiple parameters such as a total count characters in the generation and processing of checksum values. (see Flier paragraph [0106])
Regarding Claim 3, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 2, Hwherein the predetermined order is defined by at least one of a user or a processor on which the checksum is generated. (see Soryal paragraph [0034], lines 1-20: Memory of security controller stores, permanently and/or temporarily, received and transmitted information, as well as system software, control software, other software for security controller, and a variety of other information; Memory may store information for execution by processor; Memory stores sequence generator, discrepancy detector, key generator, host tracker, and database; Memory includes any one or a combination of volatile or non-volatile local or remote devices suitable for storing information; Memory may include any suitable information for use in the operation of security controller; (selected: processor utilized to generate security sequence (checksum))
Regarding Claim 9, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 1, wherein the data matrix is converted from data source selected from a group of data sources consisting of document, calculation, a password, a list, an audio, a video, a digital file, a communication stream, a predefined source, and/or a random source. (see Soryal paragraph [0034], lines 1-20: Memory of security controller stores, permanently and/or temporarily, received and transmitted information, as well as system software, control software, other software for security controller, and a variety of other information; Memory may store information for execution by processor; Memory stores sequence generator, discrepancy detector, key generator, host tracker, and database; Memory includes any one or a combination of volatile or non-volatile local or remote devices suitable for storing information; Memory may include any suitable information for use in the operation of security controller; (selected: processor utilized to generate security sequence (checksum); (selected: data source selected from a predefined source))
Regarding Claim 10, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 9, wherein the data source is divided into at least two data portions and wherein each data portion from which a checksum is formed. (Soryal paragraph [0032], lines 1-10: security controller 120 that may be used by the system; Security controller 120 includes interface 220, memory 240, and processor 260. Memory 240 includes sequence generator 250, discrepancy detector 252, key generator 254, host tracker 256, and database 280; Database 280 includes security sequences 282 and keys 284. Security sequences 282 include security sequence 160, security sequence 162, and security sequence 164; Keys 284 include key 170 and key 172; (multiple security sequences generated from different key parameters (two different keys)))
Soryal does not specifically disclose data converted into a matrix.
However, Wright discloses data portion converted into a matrix. (see Wright col 8, lines 5-24: Each of the samples is then preferably coded to form coded data or preferably a parity bit set; one parity bit is chosen for each half of each sample to make the overall parity even; a sample containing the following bits "1011" would be reduced to a parity digit "10"; The first half of the sample "10" includes only an odd number of 1 bits, thus another "1" must be added to make the parity even; The second half of the sample "11" includes an even number of "1" bits so that adding a "0" bit will maintain the even parity; Thus the sample "1011" is coded into the dibit "10"; Each sample is then similarly coded to form a new array of coded data with the dibits (CD0, CD1, . . . CD39) replacing the corresponding samples (NO, N1, . . . N39) of the array; For each row and column new array, a checksum may then preferably be performed to combine the entries of coded data of each row and column to form respective row and column vectors; (selected: the numerals "0" and "1" in at least one row of the data matrix so that the number of appearances of each numeral is sequentially placed))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for data converted into a matrix as taught by Wright. One of ordinary skill in the art would have been motivated to employ the teachings of Wright for the benefits achieved from a system that enables the processing of checksum parameters in a sequential order. (see Wright col 8, lines 5-24)
Regarding Claim 11, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 1.
Soryal does not specifically disclose the format of the data matrix is a format selected from a group of formats consisting of binary, decimal, hexadecimal, octal, ASCII, and a combination thereof.
However, Wright discloses wherein the format of the data matrix is a format selected from a group of formats consisting of binary, decimal, hexadecimal, octal, ASCII, and a combination thereof. (see Wright col 8, lines 5-24: Each of the samples is then preferably coded to form coded data or preferably a parity bit set; one parity bit is chosen for each half of each sample to make the overall parity even; a sample containing the following bits "1011" would be reduced to a parity digit "10"; The first half of the sample "10" includes only an odd number of 1 bits, thus another "1" must be added to make the parity even; The second half of the sample "11" includes an even number of "1" bits so that adding a "0" bit will maintain the even parity; Thus the sample "1011" is coded into the dibit "10"; Each sample is then similarly coded to form a new array of coded data with the dibits (CD0, CD1, . . . CD39) replacing the corresponding samples (NO, N1, . . . N39) of the array 134; For each row 137 and column 139 new array 135 a checksum may then preferably be performed to combine the entries of coded data of each row and column to form respective row and column vectors; (selected: the numerals "0" and "1" in at least one row of the data matrix so that the number of appearances of each numeral is sequentially placed; (selected: format consisting of binary))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for the format of the data matrix is a format selected from a group of formats consisting of binary, decimal, hexadecimal, octal, ASCII, and a combination thereof as taught by Wright. One of ordinary skill in the art would have been motivated to employ the teachings of Wright for the benefits achieved from a system that enables the processing of checksum parameters in a sequential order. (see Wright col 8, lines 5-24)
8. Claims 5 - 7 are rejected under 35 U.S.C. 103 as being unpatentable over Soryal in view of Wright and further in view of Flier and Shinjo and JP4693245 and Gamel et al. (Patent No. CN 102799495 A).
Regarding Claim 5, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 1, including the data source. (see Soryal paragraph [0018]: A security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations. A checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm). The checksum algorithm will output a different checksum for any change made to the checksum algorithm's input. ... A security sequence may represent a security configuration of a node of network 110.)
Soryal does not specifically disclose performing a XOR operator with a checksum.
However, Gamel discloses wherein further comprising performing a XOR operator on the checksum generated from the data. (see Gamel paragraph [0025], lines 1-8: for generating a checksum of device also comprises an input of the current payload symbol; selector is configured to the first reservoir or the second reservoir coupled to the input of the device; checksum processor in first reservoir coupled to the input of the device and provides a first payload check sum, and the second reservoir is coupled to the input of the device and providing a second checksum of payload while processing the second number of payload symbols when processing the first number of payload symbols; paragraph [0068], lines 1-8: XOR operation or XNOR operation used for combining the current payload symbol and the previous coding symbol or the initialization symbol; the current payload symbol and the previous coding symbol or the initialization symbol may comprise a symbol unit of a certain number (or position), wherein the unit (or bitwise combinations) can be used for combining the current payload symbol and the previous coding symbol or the initialization symbol; (XOR or XNOR operations utilized for checksum processing))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for performing a XOR operator with a checksum as taught by Gamel. One of ordinary skill in the art would have been motivated to employ the teachings of Gamel for the benefits achieved from a system that enables the utilization of XOR or XNOR operations in the processing of checksum parameters. (see Gamel paragraph [0025], lines 1-8; paragraph [0068], lines 1-8)
Regarding Claim 6, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 1, including a data source. (see Soryal paragraph [0018]: A security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations. A checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm). The checksum algorithm will output a different checksum for any change made to the checksum algorithm's input. ... A security sequence may represent a security configuration of a node of network 110.)
Soryal does not specifically disclose performing a XNOR operator with a checksum.
However, Gamel discloses wherein further comprising performing a XNOR operator on the checksum generated from the data. (see Gamel paragraph [0025], lines 1-8: for generating a checksum of device also comprises an input of the current payload symbol; selector is configured to the first reservoir or the second reservoir coupled to the input of the device; checksum processor in first reservoir coupled to the input of the device and provides a first payload check sum, and the second reservoir is coupled to the input of the device and providing a second checksum of payload while processing the second number of payload symbols when processing the first number of payload symbols; paragraph [0068], lines 1-8: XOR operation or XNOR operation used for combining the current payload symbol and the previous coding symbol or the initialization symbol; the current payload symbol and the previous coding symbol or the initialization symbol may comprise a symbol unit of a certain number (or position), wherein the unit (or bitwise combinations) can be used for combining the current payload symbol and the previous coding symbol or the initialization symbol; (XOR or XNOR operations utilized for checksum processing))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for performing a XNOR operator with a checksum as taught by Gamel. One of ordinary skill in the art would have been motivated to employ the teachings of Gamel for the benefits achieved from a system that enables the utilization of XOR or XNOR operations in the processing of checksum parameters. (see Gamel paragraph [0025], lines 1-8; paragraph [0068], lines 1-8)
Regarding Claim 7, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 1, including a data source. (see Soryal paragraph [0018]: A security sequence is a checksum (e.g., a long checksum) that is used to detect modifications in security configurations. A checksum is a set of values that is the output of running a checksum algorithm (e.g., a dynamic algorithm). The checksum algorithm will output a different checksum for any change made to the checksum algorithm's input. ... A security sequence may represent a security configuration of a node of network 110.)
Soryal does not specifically disclose performing a XOR and a XNOR operators with a checksum.
However, Gamel discloses wherein further comprising performing a XOR and a XNOR operators with a checksum generated from the data. (see Gamel paragraph [0025], lines 1-8: for generating a checksum of device also comprises an input of the current payload symbol; selector is configured to the first reservoir or the second reservoir coupled to the input of the device; checksum processor in first reservoir coupled to the input of the device and provides a first payload check sum, and the second reservoir is coupled to the input of the device and providing a second checksum of payload while processing the second number of payload symbols when processing the first number of payload symbols; paragraph [0068], lines 1-8: XOR operation or XNOR operation used for combining the current payload symbol and the previous coding symbol or the initialization symbol; the current payload symbol and the previous coding symbol or the initialization symbol may comprise a symbol unit of a certain number (or position), wherein the unit (or bitwise combinations) can be used for combining the current payload symbol and the previous coding symbol or the initialization symbol; (XOR or XNOR operations utilized for checksum processing))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for performing a XOR and a XNOR operators with a checksum as taught by Gamel. One of ordinary skill in the art would have been motivated to employ the teachings of Gamel for the benefits achieved from a system that enables the utilization of XOR or XNOR operations in the processing of checksum parameters. (see Gamel paragraph [0025], lines 1-8; paragraph [0068], lines 1-8).
9. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Soryal in view of Wright and further in view of Flier and Shinjo and JP4693245 and Bernsen et al. (Patent No. EP 3644637 A1).
Regarding Claim 8, Soryal-Wright-Flier-Shinjo-JP4693245 discloses the method as claimed in claim 1.
Soryal does not specifically disclose padding a checksum with either predefined or random data.
However, Bernsen discloses wherein further comprising padding the checksum with either predefined or random data. (see Bernsen paragraph [0053], lines 1-14: the integrity unit cryptographically processes, while using the secret integrity key, a combination of the checksum for a predetermined one of the checksum fields and a predetermined part of the link data; The cryptographic processing may be encryption or the application of a hash-based message authentication code (HMAC); The checksum may be calculated as defined in the communication protocol, and may be concatenated with a block number or block address, and optionally further link data, i.e. a predetermined selection of link data that varies from block to block; Further such combination may include padding data or a salt; The primary function of salts is to defend against dictionary attacks or against its hashed equivalent, a pre-computed rainbow table attack; If padding data or a salt is used, the value has to be shared between the base station and the user device; (padding with random data))
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Soryal for padding a checksum with either predefined or random data as taught by Bernsen. One of ordinary skill in the art would have been motivated to employ the teachings of Bernsen for the benefits achieved from a system that enables the utilization of random padding in the processing of checksum parameters. (see Bernsen paragraph [0053], lines 1-14)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLTON JOHNSON whose telephone number is (571)270-1032. The examiner can normally be reached Work: 12-9PM (most days).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shewaye Gelagay can be reached on 571-272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CJ/
May 18, 2026
/FATOUMATA TRAORE/Primary Examiner, Art Unit 2436
Prosecution Insights