DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/26/2026 has been entered.
Response to Amendment
Applicant's Amendment filed 06/26/2026 has been fully considered and entered.
The objection to claim 17 set forth in the Office Action mailed 05/07/2026 is withdrawn in view of Applicant’s Amendment.
Response to Arguments
Applicant's arguments filed 06/26/2026 have been fully considered but they are not persuasive with respect to independent claims 1, 11, and 17 and their dependent claims.
Applicant’s arguments with respect to independent claim(s) 53 and its dependent claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
To increase clarity for the arguments and rejections, the following structure of Watts is specified:
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The Applicant argues on pages 7-8 of the Remarks dated 6/26/2026 that claim 1 requires the laser circuitry to be attached to the top surface of the PIC and that Watts does not teach or suggest this arrangement. The examiner disagrees. A portion of the interpreted laser circuitry is attached to the top surface of the interpreted PIC (Photonics SOI, page 4 of the Final Rejection dated 05/07/2026) since the top surface is interpreted as the upper boundary of the interpreted PIC and the laser and Photonics SOI are attached at said boundary. See the rejection below for additional details.
The Applicant argues on pages 8-9 of the Remarks dated 6/26/2026 that claim 11 requires top-surface optical coupling. The examiner disagrees. A surface is defined as the exterior or upper boundary of an object or body, for example, the surface of the ocean or the surface of a sphere. A surface does not require flatness or planarity. As such, the Photonics SOI creates an upper boundary through which the laser light is coupled and does not need to consider the direction of the light coupling. See the rejection below for additional details.
The Applicant argues on page 9 of the Remarks dated 6/26/2026 that claim 17 requires a portion of the second surface of the PIC (i.e., the surface facing the laser circuitry and interpreted as equivalent to the upper boundary of the Photonics SOI) is open to air and points to SOI 104 as a SOI never open to air during manufacturing steps where the other components also exist and are assembled. The examiner disagrees. The examiner did not interpret SOI 104 as the PIC. On page 10 of the Final Rejection dated 05/07/2026, the PIC is interpreted as the "Photonics SOI" which is clearly labelled as extending upwards from the Photonics SOI-Glass Wafer interface in at least Fig. 2, 9, and 14 which are listed in the rejection and does not narrow in on SOI 104 which is a much smaller portion of Photonics SOI and is only labelled in Fig. 3. Since the manufacturing argument depends upon a different SOI than the examiner's interpretation, the argument is overcome with reference to Fig. 13 which shows the structure before the encapsulation shown in Fig. 14. In Fig. 13 then, at least a portion of the upper boundary of the Photonics SOI is open to the air. See rejection below for details.
The Applicant argues on page 9 of the Remarks dated 6/26/2026 that claim 53 requires a surface of the laser circuitry closest to the PIC to be coplanar with a surface of the EIC that is closest to the PIC. The examiner agrees that the equivalent surfaces of Watts are not coplanar since the CMOS die is raised up by Backmetal2 and copper bonds and since Watts does not show an embodiment without these metal structures. However, Applicant's argument with respect to claim 53 is moot because the new ground of rejection does not rely on any reference applied in the prior art rejection for any teaching or matter specifically challenged in the argument. See the rejection below for details.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 11, 36-38, 47-48, and 50 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watts et al. in US 20190243081 A1 (hereinafter "Watts").
Regarding claim 1, Watts discloses a laser package, comprising:
a substrate having a substrate surface and further having a cavity that extends into the substrate surface (the substrate is interpreted as the combination of the PCB/Package and the Glass Wafer shown in Fig. 2 and 13; the cavity is interpreted as the space where the Photonics SOI exists, see also Fig. 2 and 13);
a photonic integrated circuit (PIC), wherein a first surface of the PIC is attached to a bottom of the cavity (Photonics SOI is interpreted as the PIC, see Fig. 2 and 13; see Para. 26-27 and Fig. 4, “wafer-level bonding”);
laser circuitry attached to a second surface of the PIC, wherein the second surface of the PIC is opposite the first surface (laser module 170 is interpreted as laser circuitry; see Para. 35 and Fig. 9 for attachment; see Annotated Fig. 13 above for the upper boundary of Photonics SOI which is interpreted as the second surface of the PIC); and
a heat spreader, wherein the heat spreader is closer to the laser circuitry than to the PIC (heatsink 204 is interpreted as the heat spreader; see Fig. 2 and 13 where heatsink 204 is closer to laser 170 than to the Photonics SOI).
Regarding claim 11, Watts discloses an electronic device, comprising:
a substrate having a substrate surface and further having a cavity in the substrate surface (the substrate is interpreted as the combination of the PCB/Package and the Glass Wafer shown in Fig. 2 and 13; the cavity is interpreted as the space where the Photonics SOI exists, see also Fig. 2 and 13);
a photonic integrated circuit (PIC), wherein a first surface of the PIC is attached to the substrate within the cavity (Photonics SOI is interpreted as the PIC, see Fig. 2 and 13; see Para. 26-27 and Fig. 4, “wafer-level bonding”);
laser circuitry, having a first laser circuitry surface and a second laser circuitry surface, wherein the first laser circuitry surface is vertically stacked over and attached to a first portion of a second surface of the PIC, the second surface of the PIC is opposite the first surface of the PIC, the second laser circuitry surface is opposite the first laser circuitry surface (laser module 170 is interpreted as laser circuitry; see Para. 35 and Fig. 9 for attachment; the surface of the laser touching Photonics SOI is interpreted as the first laser circuitry surface; the surface of the laser touching/facing the heatsink is interpreted as the second laser circuitry surface; the upper portion of the Photonics SOI touching/facing the laser is interpreted as the second surface of the PIC; the bottom portion of the Photonics SOI not touching/facing the laser, i.e., facing the Glass Wafer, is interpreted as the first surface of the Photonics SOI; see Fig. 2 and 13; see Annotated Fig. 13 above), and the laser circuitry is to couple light into the PIC through the second surface of the PIC (the laser 170 necessarily couples light into the Photonics SOI through the interpreted second surface);
an integrated circuit having a portion vertically stacked over and attached to a second portion of the second surface of the PIC (CMOS Die is interpreted as the integrated circuit, note Para. 37; see Fig. 2 and 13 which show vertical stacking above the Photonics SOI and attachment via some backmetal contacts and copper pillars, note Para. 36); and
a heat spreader above the second laser circuitry surface, wherein a distance between the heat spreader and the laser circuitry is smaller than a distance between the heat spreader and the PIC (heatsink 204 is interpreted as the heat spreader; see Fig. 2 and 13 where heatsink 204 is closer, and thus necessarily having a shorter distance, to laser 170 than to the Photonics SOI).
Regarding claim 36, Watts discloses the electronic device of claim 11 as discussed above, wherein a distance between the heat spreader and the integrated circuit is smaller than a distance between the heat spreader and the PIC (heatsink 204 is interpreted as the heat spreader; see Fig. 2 and 13 where heatsink 204 has a shorter distance to CMOS Die than to the Photonics SOI).
Regarding claims 37 and 38, Watts discloses the electronic device of claim 36 and 11 respectively as discussed above, wherein:
a footprint of the PIC is within a footprint of the heat spreader, and
a footprint of the integrated circuit is within the footprint of the heat spreader (see Fig. 2 and 13 where the heatsink has horizontal overlap with the laser and CMOS die in the views shown; these overlaps are interpreted as the overlapping footprints).
Regarding claim 47, Watts discloses the laser package of claim 1 as discussed above, wherein light output by the laser circuitry is to be coupled into the PIC through the second surface of the PIC (the laser 170 necessarily couples light into the Photonics SOI through the interpreted second surface).
Regarding claims 48 and 50, Watts discloses the laser package of claims 1 and 11 respectively as discussed above, wherein at least a portion of the second surface of the PIC is open to air (in Fig. 13, no encapsulation has taken place, so the intermediate product has at least a portion of the interpreted second surface of the Photonics SOI open to air).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watts et al. in US 20190243081 A1 (hereinafter "Watts") as applied above, and in view of Mahgerefteh et al. in US 20170179680 (hereinafter "Mahgerefteh").
Regarding claim 3, Watts discloses the laser package of claim 1 as discussed above, but fails to teach:
wherein the second surface of the PIC includes a first grating coupler (GC) and the laser circuitry includes a second GC at a surface of the laser circuitry that is closest to the PIC.
Mahgerefteh teaches a similar device (see Para. 60-65):
wherein the second surface of the PIC (the surface of Si PIC 104 including second surface grating 108) includes a first grating coupler (GC) (second surface grating 108 is interpreted as a grating coupler; see Fig. 1) and the laser circuitry (laser 102) includes a second GC (first surface grating 106 is interpreted as a grating coupler) at a surface of the laser circuitry that is closest to the PIC (the surface of 102 containing 106 facing 104; the surface is interpreted as being the closest since there is no intervening structure between the gratings; see Fig. 1).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the grating-to-grating system of Mahgerefteh in the package of Watts for the purpose of increasing the alignment tolerance thereby achieving a device that can be assembled passively thus saving manufacturing time.
Regarding claim 15, Watts discloses the electronic device of claim 11 as discussed above, but fails to teach:
wherein the second surface of the PIC includes a first grating coupler (GC), and the first laser circuitry surface includes a second GC.
Mahgerefteh teaches a similar device (see Para. 60-65):
wherein the second surface of the PIC (the surface of Si PIC 104 including second surface grating 108) includes a first grating coupler (GC) (second surface grating 108 is interpreted as a grating coupler; see Fig. 1), and the first laser circuitry surface includes a second GC (the first laser circuitry surface is interpreted as the surface of laser 102 containing 106 facing 104; the surface is interpreted as being the closest since there is no intervening structure between the gratings; see Fig. 1).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the grating-to-grating system of Mahgerefteh in the package of Watts for the purpose of increasing the alignment tolerance thereby achieving a device that can be assembled passively thus saving manufacturing time.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watts et al. in US 20190243081 A1 (hereinafter "Watts") as applied above, and in view of Bettman et al. in US 20200144151 A1 (hereinafter "Bettman").
Regarding claim 12, Watts discloses the electronic device of claim 11 as discussed above, but fails to teach:
further comprising a pedestal vertically stacked between and attached to the heat spreader and the second laser circuitry surface.
Bettman teaches using a pedestal to adjust heights relative to heat spreaders within a similar device.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the pedestal of Bettman in the package of Watts for the purpose of adjusting the device to handle height mismatches and/or a variety of laser and/or IC heights thereby achieving an even platform for the heatsink thereby increasing stability and potential component diversity. (The examiner notes that modifying the thermal design by adjusting spacing of components is well-known; see, for example, US 20220107229 A1, Para. 2 and 12)
Regarding claim 13, Watts/Bettman discloses the electronic device of claim 12 as discussed above, suggests, but fails to explicitly teach, further comprising a thermal interface material vertically stacked between the second laser circuitry surface and the pedestal. Watts, Para. 39 teaches “a thermal paste or other thermally conducting compound”, which is interpreted as thermal interface material, between the laser and heatsink. A person having ordinary skill in the art would have found it obvious before the time of filing to provide the interpreted thermal interface material between the pedestal and the laser in the device of Watts/Bettman for the purpose of increasing overall thermal flow to the heatsink thereby achieving increased heat dissipation and which is especially beneficial in heat-sensitive applications.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watts et al. in US 20190243081 A1 (hereinafter "Watts") as applied above, and in view of Meade et al. in US 20190271819 A1 (hereinafter "Meade").
Regarding claim 14, Watts discloses the electronic device of claim 11 as discussed above, further comprising a thermal interface material (Para. 39 states “a thermal paste or other thermally conducting compound”, which is interpreted as thermal interface material, between the laser and heatsink), but fails to teach:
a thermo-electric cooler, wherein the thermo-electric cooler is vertically stacked between the thermal interface material and a portion of the heat spreader.
wherein the thermal interface material is vertically stacked between the second laser circuitry surface and the thermo-electric cooler.
Meade teaches thermo-electric coolers (TEC 3000) as a means of dissipating heat from a laser to a heat sink (see Fig. 9 and Para. 31; laser is 1230).
Taken together, Watts/Meade suggest a device comprising:
a thermo-electric cooler, wherein the thermo-electric cooler is vertically stacked between the thermal interface material and a portion of the heat spreader.
wherein the thermal interface material is vertically stacked between the second laser circuitry surface and the thermo-electric cooler, since Meade places the TEC between the laser and the heat sink, and since Watts suggests using a thermal interface material between components.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the TEC of Meade in the laser package of Watts for the purpose of more efficiently removing heat generated by the laser thereby achieving increased temperature control near heat-sensitive and/or heat-generating components.
Additionally, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the placed the thermal interface material between any components, as suggested by Watts, including a laser and a TEC as well as a TEC and a heat spreader in the laser package of Watts/Meade for the purpose of more efficiently moving unwanted laser-generated heat to the TEC and heat spreader thereby achieving reduced temperatures near heat-sensitive and/or heat-generating components.
Claim(s) 17 and 52 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watts et al. in US 20190243081 A1 (hereinafter "Watts") as applied above, and in view of Bulumulla et al. in US 20200166704 A1 (hereinafter "Bulumulla").
Regarding claim 17, Watts discloses a method for assembling a laser package, the method comprising:
attaching laser circuitry to a second surface of the PIC, wherein the second surface of the PIC is opposite the first surface of the PIC (laser module 170 is interpreted as laser circuitry; see Para. 35 and Fig. 9 for attachment; the second surface of the PIC is interpreted as the surface of the Photonics SOI closest to the laser; the first surface of the PIC is interpreted as the surface of the Photonics SOI closest to the Glass Wafer; see Fig. 2 and 13), and wherein at least a portion of the second surface of the PIC is open to air (in Fig. 13, no encapsulation has taken place, so the intermediate product has at least a portion of the interpreted second surface of the Photonics SOI open to air); and
providing a heat spreader over the laser circuitry, wherein a distance between the heat spreader and the laser circuitry is smaller than a distance between the heat spreader and the PIC (heatsink 204 is interpreted as the heat spreader; see Fig. 2 and 13 where heatsink 204 is closer to laser 170 than to the Photonics SOI and thus necessarily has a smaller distance to the laser than to the Photonics SOI).
Watts suggests loosening alignment requirements by attaching the interpreted PIC to the interpreted substrate before forming the cavity around the PIC and thus fails to explicitly teach:
positioning a first surface of a photonic integrated circuit (PIC) within a cavity in a substrate, wherein the cavity extends from a front surface of the substrate into the substrate.
Bulumulla teaches that PIC may be positioned into already formed cavities, such as:
positioning a first surface of a photonic integrated circuit (PIC) within a cavity in a substrate, wherein the cavity extends from a front surface of the substrate into the substrate (see claim 20 and Fig. 1Q);
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have positioned the PIC into a cavity as taught by Bulumulla in the laser package of Watts for the purpose of avoiding dicing after attachment thereby preventing debris accumulation near or on sensitive components.
The examiner notes that the claim does not require a specific order of the performance of the steps, only that the steps be performed. See MPEP 2111.01(II).
Regarding claim 52, Watts/Bulumulla discloses the method of claim 17 as discussed above, wherein light that is output by the laser circuitry is to be coupled into the PIC through the second surface of the PIC (the laser 170 necessarily couples light into the Photonics SOI through the interpreted second surface).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watts et al. in US 20190243081 A1 (hereinafter "Watts") in view of Bulumulla et al. in US 20200166704 A1 (hereinafter "Bulumulla") as applied above, and in view of Meade et al. in US 20190271819 A1 (hereinafter "Meade").
Regarding claim 28, Watts/Bulumulla discloses the method of claim 17 as discussed above, wherein:
the laser circuitry has a first laser circuitry surface and a second laser circuitry surface (the first laser circuitry surface is interpreted as the surface of laser module 170 closest to the Photonics SOI; the second laser circuitry surface is interpreted as the surface closest to the heatsink; see Fig. 2 and 13),
the second laser circuitry surface is opposite the first laser circuitry surface (see Fig. 2 and 13),
attaching the laser circuitry to the second surface of the PIC includes attaching the first laser circuitry surface to the second surface of the PIC (laser module 170 is interpreted as laser circuitry; see Para. 35 and Fig. 9 for attachment; the second surface of the PIC is interpreted as the surface of the Photonics SOI closest to the laser; the first surface of the PIC is interpreted as the surface of the Photonics SOI closest to the Glass Wafer; see Fig. 2 and 13), but fails to teach that:
the method further comprises:
providing a thermo-electric cooler over the second laser circuitry surface.
Meade teaches thermo-electric coolers (TEC 3000) as a means of dissipating heat from a laser to a heat sink (see Fig. 9 and Para. 31; laser is 1230) and is thus interpreted as (when incorporated with Watts) teaching:
providing a thermo-electric cooler over the second laser circuitry surface.
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the TEC of Meade in the laser package of Watts/Bulumulla for the purpose of more efficiently removing heat generated by the laser thereby achieving increased temperature control near heat-sensitive and/or heat-generating components.
Claim(s) 1, 11, 49, 51, and 53-55 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byrd et al. in US 20190044002 A1 (hereinafter "Byrd") as evidenced by Kobrinsky in US 20140203175 A1 (hereinafter "Kobrinsky").
Regarding claim 1, Byrd discloses a laser package, comprising:
a substrate having a substrate surface and further having a cavity that extends into the substrate surface (substrate 130 has a substrate surface and further has a cavity that extends into the substrate surface; see Fig. 10; the cavity is specifically interpreted as the area where PIC 105 exists and 130 does not);
a photonic integrated circuit (PIC 105), wherein a first surface of the PIC is attached to a bottom of the cavity (a first surface of 105 is indirectly attached to the bottom of the cavity with copper stop layer 170); and
a heat spreader, wherein the heat spreader is closer to the laser circuitry than to the PIC (heat sink 135 is interpreted as a heat spreader; see Fig. 10 where 135 is closer to anything stacked on top of the PIC than to the PIC itself).
Byrd does not teach in Fig. 10 that laser circuitry is attached to a second surface of the PIC, wherein the second surface of the PIC is opposite the first surface.
Byrd does teach in Para. 0049:
“In some embodiments a laser chip may be installed on each of the transmitting PICs (e.g., the laser may be flip-chipped on the transmitting PIC, so that a waveguide on the laser chip is aligned with a waveguide on the transmitting PIC).”
This suggests that a laser chip may be installed on the PIC directly using flip-chip bonding. Byrd does not identify that Fig. 10 is an included embodiment where the laser can be installed on the PIC and such a laser is not labelled in Fig. 10.
Additionally, this arrangement with a laser and EIC on a PIC in a cavity was already known in the art before the effective filing date as evidenced by Kobrinsky in Fig. 7 (CPU/TXRX is interpreted as EIC; LZR 742 is a laser; PLC 740 is interpreted as a PIC; cavity is in package 710).
Per Byrd’s own paragraph, a person having ordinary skill in the art would have found it obvious before the effective filing date of the claimed invention to have tried installing the laser chip on the PIC of Byrd for the purpose of providing light emission means thereby increasing the device’s capabilities.
Regarding claim 49, Byrd/Kobrinsky discloses the laser package of claim 1 as discussed above, further comprising:
an electronic integrated circuit (EIC) coupled with the second surface of the PIC (analog ASIC 115 is interpreted as an EIC coupled with the second surface of the PIC; see Fig. 10),
wherein a surface of the laser circuitry that is closest to the PIC is coplanar with a surface of the EIC that is closest to the PIC (see Fig. 10 where laser and analog ASIC would necessarily reside on the same surface because of flip-chip bonding and thus be coplanar; Additionally, Kobrinsky also has a coplanar arrangement in Fig. 3B where laser 320 and transceiver 330 exist on PLC 330).
Regarding claim 11, Byrd discloses an electronic device, comprising:
a substrate having a substrate surface and further having a cavity in the substrate surface (substrate 130 has a substrate surface and further has a cavity that extends into the substrate surface; see Fig. 10; the cavity is specifically interpreted as the area where PIC 105 exists and 130 does not);
a photonic integrated circuit (PIC), wherein a first surface of the PIC is attached to the substrate within the cavity (a first surface of 105 is indirectly attached to the substrate within the cavity with copper stop layer 170);
an integrated circuit having a portion vertically stacked over and attached to a second portion of the second surface of the PIC (analog ASIC is interpreted as an integrated circuit having a portion vertically stacked over and attached to a second portion of the second surface of 105); and
a heat spreader above the second laser circuitry surface, wherein a distance between the heat spreader and the laser circuitry is smaller than a distance between the heat spreader and the PIC (heat sink 135 is interpreted as a heat spreader; see Fig. 10 where 135 has a smaller distance to anything stacked on top of the PIC than to the PIC itself).
Byrd does not teach in Fig. 10 that laser circuitry, having a first laser circuitry surface and a second laser circuitry surface, wherein the first laser circuitry surface is vertically stacked over and attached to a first portion of a second surface of the PIC, the second surface of the PIC is opposite the first surface of the PIC, the second laser circuitry surface is opposite the first laser circuitry surface, and the laser circuitry is to couple light into the PIC through the second surface of the PIC.
Byrd does teach in Para. 0049:
“In some embodiments a laser chip may be installed on each of the transmitting PICs (e.g., the laser may be flip-chipped on the transmitting PIC, so that a waveguide on the laser chip is aligned with a waveguide on the transmitting PIC).”
This suggests that a laser chip may be installed on the PIC directly using flip-chip bonding. Byrd does not identify that Fig. 10 is an included embodiment where the laser can be installed on the PIC and such a laser is not labelled in Fig. 10. Flip-chip bonding would mean the laser and PIC necessarily face each other. The waveguide on the laser and the waveguide on the PIC would only be aligned in order to couple light from the laser circuitry and into the PIC through the second surface of the PIC.
Additionally, this arrangement with a laser and EIC on a PIC in a cavity was already known in the art before the effective filing date as evidenced by Kobrinsky in Fig. 7 or laser and transceiver (a type of EIC) on a PLC in Fig. 3B.
Per Byrd’s own paragraph, a person having ordinary skill in the art would have found it obvious before the effective filing date of the claimed invention to have tried installing the laser chip on the PIC of Byrd for the purpose of providing light emission means thereby increasing the device’s capabilities. See MPEP 2143(I)(E).
Regarding claim 51, Byrd discloses the electronic device of claim 11 as discussed above, wherein the first laser circuitry surface is coplanar with a surface of the integrated circuit that is closest to the PIC (see Fig. 10 where laser and analog ASIC would necessarily reside on the same surface and thus be coplanar).
Regarding claim 53, Byrd discloses a laser package, comprising:
a substrate having a substrate surface and further having a cavity that extends into the substrate surface (substrate 130 has a substrate surface and further has a cavity that extends into the substrate surface; see Fig. 10; the cavity is specifically interpreted as the area where PIC 105 exists and 130 does not);
a photonic integrated circuit (PIC), wherein a first surface of the PIC is attached to a bottom of the cavity (a first surface of 105 is indirectly attached to the substrate within the cavity with copper stop layer 170);
a heat spreader, wherein the heat spreader is closer to the laser circuitry than to the PIC (heat sink 135 is interpreted as a heat spreader; see Fig. 10 where 135 is closer to anything stacked on top of the PIC than to the PIC itself); and
an electronic integrated circuit (EIC) coupled with the second surface of the PIC (analog ASIC 115 is interpreted as EIC coupled with the second surface of 105; see Fig. 10).
Byrd does not teach in Fig. 10 that:
laser circuitry attached to a second surface of the PIC, wherein the second surface of the PIC is opposite the first surface; and
wherein a surface of the laser circuitry that is closest to the PIC is coplanar with a surface of the EIC that is closest to the PIC.
Regarding the laser circuitry:
Byrd does teach in Para. 0049:
“In some embodiments a laser chip may be installed on each of the transmitting PICs (e.g., the laser may be flip-chipped on the transmitting PIC, so that a waveguide on the laser chip is aligned with a waveguide on the transmitting PIC).”
This suggests that a laser chip may be installed on the PIC directly using flip-chip bonding. Byrd does not identify that Fig. 10 is an included embodiment where the laser can be installed on the PIC and such a laser is not labelled in Fig. 10.
Additionally, this arrangement with a laser and EIC on a PIC in a cavity was already known in the art before the effective filing date as evidenced by Kobrinsky in Fig. 7 (CPU/TXRX is interpreted as EIC; LZR 742 is a laser; PLC 740 is interpreted as a PIC; cavity is in package 710).
Per Byrd’s own paragraph, a person having ordinary skill in the art would have found it obvious before the effective filing date of the claimed invention to have tried installing the laser chip on the PIC of Byrd for the purpose of providing light emission means thereby increasing the device’s capabilities.
Regarding the coplanarity:
Since the laser is flip-chip bonded to the same surface of the PIC 105 as the analog ASIC 115, then the surface of the laser circuitry that is closest to the PIC is necessarily coplanar with a surface of the interpreted EIC that is closest to the PIC.
Regarding claim 54, Byrd/Kobrinsky discloses the laser package of claim 53 as discussed above, wherein light output by the laser circuitry is to be coupled into the PIC through the second surface of the PIC (see Para. 49 which aligns and flip-chip bonds a laser on to the PIC which necessarily results in light output by the laser circuitry to be coupled into the PIC through the second surface of the PIC).
Regarding claim 55, Byrd/Kobrinsky discloses the laser package of claim 53 as discussed above, wherein at least a portion of the second surface of the PIC is open to air (the interpreted second surface 105 is not fully encapsulated as shown in Fig. 10 thus it is necessarily open to air).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARBY M THOMASON whose telephone number is (703)756-5817. The examiner can normally be reached Mon.-Fri. 8am-5pm.
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/DARBY M. THOMASON/Examiner, Art Unit 2874
/MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874
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