Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
The instant application having Application No. 17/550,736 has claims 1-20 pending filed on 12/14/2021; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
Acknowledgement Of References Cited By Applicant
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statements dated November 5 2025, December 8 2025, December 26 2025, February 23 2026 and March 24, 2026 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C (2), copies of the PTOL-1449 initialed and dated by the examiner are attached to the instant office action.
Response to Arguments
This Office Action is in response to applicant’s communication filed on October 30, 2025 in response to PTO Office Action dated July 30, 2025. The Applicant’s remarks and amendments to the claims and/or specification were considered with the results that follow.
Claim Rejections
Claim Rejections - 35 USC § 103
35 USC § 103 Rejection of claims 1-20
Claims 1-6, 8-12 and 14-18 were rejected in the Office Action under 35 U.S.C. §103 as being unpatentable over Grosz (US Patent Publication No. 2020/0210104), Therene (US Patent Publication No. 2020/0133898) and Jakobsson (US Patent Publication No. 2022/0368596). Furthermore, claim 7 was rejected under 35 U.S.C. §103 as being unpatentable over Grosz, Therene, Jakobsson and Troia (US Patent Publication No. 2020/0311314). Lastly, claims 13, 19 and 20 were rejected under 35 U.S.C. §103 as being unpatentable over Grosz, Therene, Jakobsson and Shiner (US Patent Publication No. 20220131700).
CLAIM 1
Applicant argues on page 5 in regards to the independent claim 1, “Therene's media access manager provides information describing the host I/Os received from the host system to an artificial intelligence engine, and schedules host I/Os based on predictions of host system behavior. Notably, however, the cited portions of Therene, and Therene as a whole, fail to disclose receiving, over a network connection established under control of an internal host of a solid state drive, configuration data for controlling at least one operation of the very same internal host-where the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity. Indeed, Therene fails to disclose the more general concept of receiving configuration data that specifies an amount of resources usable by an internal host of a solid state drive to participate in any type of activity. Moreover, the cited portions of Grosz and Jakobbson fail to make up for the deficiencies of Therene in these regards. Thus, Grosz, alone or in combination with Therene and Jakobsson, fails to disclose "receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host, wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity" as claimed in amended claim 1 “.
Examiner respectfully disagrees with arguments on page 5 in regards to the independent claim 1. The combination of Grosz (20200210104), Therene (US Patent Publication No. 2020/0133898) and Jakobsson (US Patent Publication No. 2022/0368596) teaches all the limitations of the independent claim 1. Therene (Paragraph [0007], Paragraph [0043] and Paragraph [0131]) teaches “a transceiver configured to: receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host (a System-on-Chip (SoC) is described that includes a media interface to access storage media of a storage system, a host interface to communicate with a host system, and an artificial intelligence engine where the SoC may include a transceiver interface configured to enable storage over a wired or wireless network, the media access manager may provide indications of host I/Os for storage media access to the AI engine which may use the indications of host I/O activity as inputs for the AI models to predict or forecast subsequent host system behavior (configuration data for controlling at least one operation of the internal host) and based on this prediction of host system behavior, the media access manager may schedule the host I/O and/or internal I/Os of the storage system, as well as adapt to user-specific workloads) ” of the amended independent claim 1. Also, Therene (Paragraph [0117], Paragraph [0118], Paragraph [0119] and Paragraph [0121]) teaches “wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity” of the amended independent claim 1. Thus, it would be obvious to one of ordinary skill in the art that the combination of Grosz (20200210104), Therene (US Patent Publication No. 2020/0133898) and Jakobsson (US Patent Publication No. 2022/0368596) teaches the limitation “receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host, wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity”. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Thus, the applicant’s arguments against Therene are incorrect.
Applicant argues on page 6 in regards to the independent claim 1, “Additionally, Jakobbson, alone or in combination with Grosz and Therene, fail to disclose ‘wherein the internal host is configured to generate, independent of the host system, based on the amount, and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space,’ as claimed in amended claim 1. While Jakobbson generally discuses resource usage in the context of storage of graphs, the cited portions of Jakobbson and Jakobbson as a whole, fail to disclose, teach, or suggest using configuration data to specify an amount of resources usable by an internal host to participate in at least one proof of space activity, and to generate commands related to proof of space based on the amount specified “.
Examiner respectfully disagrees with arguments on page 6 in regards to the independent claim 1. The combination of Grosz (20200210104), Therene (US Patent Publication No. 2020/0133898) and Jakobsson (US Patent Publication No. 2022/0368596) teaches all the limitations of the independent claim 1. Jaqkobsson (Paragraph [0154] and Fig.7) teaches “wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space (a system for providing proof of space which may include a graph generating device in communication with a registration authority, a graph using device configured to use a graph generated by the graph generating device (wherein the internal host is configured to generate, independent of the host system), the graph using device is in communication with a challenge generator, the challenge generator sends a challenge to the graph using device, the graph using device is configured to generate an output based on the challenge, the output is sent to verifier, which verifies the output provided by the graph using device (based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space) where the various devices and entities may communicate with each other over a network and the challenge generator and the verifier are shown as separate entities) ” of the amended independent claim 1. Thus, it would be obvious to one of ordinary skill in the art that the combination of Grosz (20200210104), Therene (US Patent Publication No. 2020/0133898) and Jakobsson (US Patent Publication No. 2022/0368596) teaches the limitation “wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space”. Thus, the applicant’s argument against Jakobsson is incorrect.
CLAIMS 10 and 17.
Applicant argues on page 6 in regards to the independent claims 10 and 17, “The arguments set forth against the rejection of claim 1 are hereby applied to the rejections of claims 10 and 17, which include similar features as found in amended claim 1. Thus, Grosz, alone or in combination with Therene and Jakobsson, fails to disclose the features as recited in claims 1, 10, and 17 and those claims depending therefrom.“
Examiner respectfully disagrees with arguments on page 6 in regards to the independent claims 10 and 17. As specified supra for the independent Claim 1, the combination of the Grosz (20200210104), Therene (US Patent Publication No. 2020/0133898) and Jakobsson (US Patent Publication No. 2022/0368596) teaches all the limitations of the independent claims 10 and 17 respectively. The claims 10 and 17 are not allowable.
Dependent Claims 2-9, 11-16 and 18-20
Applicant argues on page 6 in regards to the dependent claims 2-9, 11-16 and 18-20, “The remaining cited references fail to make up for the deficiencies of Grosz, Therene, and Jakobsson. Therefore, the Examiner is respectfully requested to withdraw the rejections under 35 U.S.C. § 103 and issue a Notice of Allowance “.
Examiner respectfully disagrees with arguments on page 6 in regards to the dependent claims 2-9, 11-16 and 18-20. As specified supra for the independent Claims 1, 10 and 17 the claims 2-9, 11-16 and 18-20 are not allowable.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Independent Claim 1
As per the independent claim 1, the claim recites “An apparatus, comprising …
wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space”. It is not clear which “amount” is meant by the claim limitation. As per specifications, Paragraph [0013] “in response to a challenge, a correct response to the challenge, generated within a threshold period of time from the challenge, can be seen as a result of the response being generated using the lookup tables stored in a data storage device. Storing the lookup tables occupies an amount of data storage space”. Paragraph [0017] “… a plot suitable for proof of space includes data used in challenge-response activities. Such data of a plot typically includes a set of lookup tables with numbers that appear to be random and that are generated from a small amount of initial data”. The Claim language may not be "ambiguous, vague, incoherent, opaque, or otherwise unclear in describing and defining the claimed invention." Packard, 751 F.3d at 1311. The applicant is required to make clear and precise the terms that are used to define the invention whereby the metes and bounds of the claimed invention can be ascertained (Refer MPEP 2173.05(a)). Thus, the above-mentioned limitations render the independent claim 1 indefinite because it is unclear which “amount” is meant by the claim limitations.
Independent Claims 10 and 17
The independent claims 10 and 17 have similar limitations as the independent claim 1 and are thus rejected under 35 U.S.C. 112(b) as indefinite for the same reasons as specified supra for the independent claim 1.
Dependent Claims 2-9, 11-16 and 18-20
The dependent claims 2-9, 11-16 and 18-20 depend directly or indirectly on the independent claims 1, 10 and 17 respectively and are thus rejected for the same reasons as specified supra for the independent claims 2-9, 11-16 and 18-20.
For the reasons specified supra, the claims 1-20 are rejected under 35 U.S.C. 112(b), as being indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12, 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Grosz et al (US PGPUB 20200210104) in view of Therene et al (US PGPUB 20200133898) and in further view of Jakobsson Bjorn Markus (US PGPUB 20220368596).
As per claim 1:
Grosz teaches:
“An apparatus, comprising” (Paragraph [0011] (a memory system including))
“a solid state drive, having” (Paragraph [0011] (having a solid-state drive
(SSD)))
“a host interface configured to receive at least read commands and write commands from a host system” (Paragraph [0020] and Paragraph [0023] (a host adaptive memory device optimization can be used where the current host command activity (read commands and write commands from a host system) is measured and one or more communication interfaces can be used to transfer data between the memory device and the host))
“and a processing device configured to control executions of the read commands to retrieve data from memory cells of the solid state drive and executions of the write commands to store data into the memory cells” (Paragraph [0025] (the memory controller can receive instructions from the host via communication interface, and can communicate with the memory array, such as to transfer data to (e.g., write or erase) or from (e.g., read) one or more of the memory cells of the memory array)).
Grosz does not EXPLICITLY disclose: a transceiver configured to: receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host; wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity; wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space.
However, in an analogous art, Therene teaches:
“a transceiver configured to: receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host” (Paragraph [0007], Paragraph [0043] and Paragraph [0131] (a System-on-Chip (SoC) is described that includes a media interface to access storage media of a storage system, a host interface to communicate with a host system, and an artificial intelligence engine where the SoC may include a transceiver interface configured to enable storage over a wired or wireless network, the media access manager may provide indications of host I/Os for storage media access to the AI engine which may use the indications of host I/O activity as inputs for the AI models to predict or forecast subsequent host system behavior (configuration data for controlling at least one operation of the internal host) and based on this prediction of host system behavior, the media access manager may schedule the host I/O and/or internal I/Os of the storage system, as well as adapt to user-specific workloads))
“wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity” (Paragraph [0117], Paragraph [0118], Paragraph [0119] and Paragraph [0121] (the information describing the host I/Os are provided to an artificial intelligence engine which may be associated with the storage system, a prediction of host behavior is received from the artificial intelligence engine including parameters regarding a next host I/O issued by the host system, a parameter for device-level management of the storage media is altered based on the prediction of host system behavior where the parameter may include a threshold for thermal management of storage media devices, or additionally, a threshold for garbage collection or data migration may be preempted or suspended to allow full host I/O performance for an access operation (specifies an amount of resources usable by the internal host) and the media I/Os that correspond to host I/Os of the host system are performed in accordance with the altered parameter for device-level management)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Therene and apply them on teachings of Grosz for the apparatus “a transceiver configured to: receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host; wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity”. One would be motivated as the SoC also includes a media access manager, AI engine, and AI models, which may be implemented separately as shown or combined with a storage component, data interface, the media access manager may interact with the AI engine to generate a prediction of host behavior with respect to future storage media access and schedule, based on the prediction, internal operations to optimize storage media performance (Therene, (Paragraph [0131])).
Grosz and Therene do not EXPLICITLY disclose: wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space.
However, in an analogous art, Jakobsson teaches:
“wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space” (Paragraph [0154] and Fig.7 (a system for providing proof of space which may include a graph generating device in communication with a registration authority, a graph using device configured to use a graph generated by the graph generating device (wherein the internal host is configured to generate, independent of the host system), the graph using device is in communication with a challenge generator, the challenge generator sends a challenge to the graph using device, the graph using device is configured to generate an output based on the challenge, the output is sent to verifier, which verifies the output provided by the graph using device (based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space) where the various devices and entities may communicate with each other over a network and the challenge generator and the verifier are shown as separate entities)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Jakobsson and apply them on teachings of Grosz and Therene for the apparatus “wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space”. One would be motivated as this would provide various improvements over existing Proof of Work schemes by allowing a larger number of participants, making the consensus-based protocol more stable and the Proof of Space technique provides the benefit like, of an improved digital currency that is not as speculation driven to be achieved (Jakobsson, (Paragraph [0057])).
As per claim 2:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 1 above.
Jakobsson further teaches:
“wherein the internal host is configured to detect the network connection and use the network connection to participate in the atleast one proof of space activity” (Paragraph [0152] and Paragraph [0226] (the processor executes software program code stored in the memory in order to control the performance of processing operations and proof of space activities (including a ledger entry, email, some type of security event description, etc) where the processing device also comprises a network interface that supports communication over one or more networks)).
As per claim 3:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 2 above.
Jakobsson further teaches:
“wherein the commands related to proof of space include write commands to store in the memory cells to store a plot in the memory cells ” (Paragraph [0361] (for Proof of Space (PoS) based mining protocols is to use available space on a storage medium to store graphs (store a plot in the memory cells) and other data on an archival drive or other storage medium in a manner that the mining process can access the information but the information relating to mining is not visible to other processes))..
As per claim 4:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 3 above.
Grosz further teaches:
“wherein the internal host is further configured to perform computations to generate the plot” (Paragraph [0028] (the memory controller is configured to generate or update the model by computing an average or other statistical measure in relation to the commands after given time intervals or after a predetermined number of commands)).
As per claim 5:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 3 above.
Grosz further teaches:
“wherein the plot includes a plurality of lookup tables” (Paragraph [0042] (the memory manager can include a set of management tables configured to maintain various information associated with one or more components of the memory device)).
Jakobsson further teaches:
“and the commands related to proof of space include read commands to retrieve values from the lookup tables to generate a response to a proof of space challenge” (Paragraph [0088] (if the entire graph is stored, and the challenge is to determine whether the value at node position matches the target pattern or has some target format, the value at node can be looked up and compared))..
As per claim 6:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 3 above.
Grosz further teaches:
“further comprising: firmware stored in the memory cells, wherein the internal host is implemented via the processing device executing the firmware” (Paragraph [0038] and Paragraph [0041] (the memory manager can include, among other things, circuitry or firmware associated with various memory management functions and the memory manager internally generates host commands)).
As per claim 8:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 1 above.
Gosz further teaches:
“a logic circuit configured to implement the internal host; an internal host interface coupled between the logic circuit and the processing device” (Paragraph [0035] (the array controller can include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device and the memory operations can be based on internally generated by the memory manager)).
As per claim 9:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 1 above.
Jakobsson further teaches:
“wherein the transceiver is configured to establish the network connection to a cryptocurrency network with a blockchain using proof of space to regulate cryptocurrency activities” (Paragraph [0180], Paragraph [0238] and Paragraph [0366] (the processing device includes network interface circuitry, which is used to interface the processing device with the network and other system components, may comprise conventional transceivers, the proof of space is coupled to a specific device type or which are included with the authority node stored in the blockchain, Proof of Space (PoS) based mining proposals for cryptocurrencies have been proposed , a fair and sustainable cryptocurrency can be developed which has benefits beyond the financial transfer aspects)).
As per claim 10:
Grosz teaches:
“A method, comprising” (Paragraph [0016] (a method for host adaptive memory
device optimization))
“detecting, by an internal host of a memory sub-system, a network connection”
(Paragraph [0044] and Paragraph [0062] (one or more memory operations can be performed on larger or smaller groups of memory cells and one or more of the techniques or methodologies can be perform in a standalone device or can be connected via network to other machines))
“communicating, by the memory sub-system using the network connection without assistance from a host system connected to a host interface of the memory sub-system” (Paragraph [0035] and Paragraph [0062] (the array controller can be configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device where the memory operations can be based on internally generated commands by the memory manager and can be connected via network to other machines)).
Grosz does not EXPLICITLY disclose: receiving, over the network connection, configuration data for controlling at least one operation of the internal host; wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity; communicating, by the memory sub-system using the network connection, with a cryptocurrency network; and generating, by the internal host independent of the host system, and based on a type of proof of space activity specified for the internal host in the configuration data, commands to operate on memory cells in the memory sub-system in participation in proof of space activities in the cryptocurrency network.
However, in an analogous art, Therene teaches:
“receiving, over the network connection, configuration data for controlling at least one operation of the internal host” (Paragraph [0007] and Paragraph [0131] (a System-on-Chip (SoC) is described that includes a media interface to access storage media of a storage system, a host interface to communicate with a host system, and an artificial intelligence engine where the SoC also includes a hardware-based processor and a memory storing processor-executable instructions that, responsive to execution by the hardware-based processor, implement a media access manager to receive host input/outputs (I/Os) from the host system for access to the storage media of the storage system via the host interface and the SoC may also include communication interfaces which may also include or implement wired or wireless communication through transceivers))
“wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity” (Paragraph [0117], Paragraph [0118], Paragraph [0119] and Paragraph [0121] (the information describing the host I/Os are provided to an artificial intelligence engine which may be associated with the storage system, a prediction of host behavior is received from the artificial intelligence engine including parameters regarding a next host I/O issued by the host system, a parameter for device-level management of the storage media is altered based on the prediction of host system behavior where the parameter may include a threshold for thermal management of storage media devices, or additionally, a threshold for garbage collection or data migration may be preempted or suspended to allow full host I/O performance for an access operation (specifies an amount of resources usable by the internal host) and the media I/Os that correspond to host I/Os of the host system are performed in accordance with the altered parameter for device-level management)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Therene and apply them on teachings of Grosz for the method “receiving, over the network connection, configuration data for controlling at least one operation of the internal host; wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity”. One would be motivated as the SoC also includes a media access manager, AI engine, and AI models, which may be implemented separately as shown or combined with a storage component, data interface, the media access manager may interact with the AI engine to generate a prediction of host behavior with respect to future storage media access and schedule, based on the prediction, internal operations to optimize storage media performance (Therene, (Paragraph [0131])).
Grosz and Therene do not EXPLICITLY disclose: communicating, by the memory sub-system using the network connection, with a cryptocurrency network; and generating, by the internal host independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands to operate on memory cells in the memory sub-system in participation in proof of space activities in the cryptocurrency network.
However, in an analogous art, Jakobsson teaches:
“communicating, by the memory sub-system using the network connection, with a cryptocurrency network” (Paragraph [0180] and Paragraph [0238] ((the processing device includes network interface circuitry, which is used to interface the processing device with the network and other system components and the Proof of Space (PoS) based mining proposals for cryptocurrencies have been proposed))
“and generating, by the internal host independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands to operate on memory cells in the memory sub-system in participation in proof of space activities in the cryptocurrency network” (Paragraph [0154] and Paragraph [0180] and Fig.7 (a system for providing proof of space which may include a graph generating device in communication with a registration authority, a graph using device configured to use a graph generated by the graph generating device (wherein the internal host is configured to generate, independent of the host system), the graph using device is in communication with a challenge generator, the challenge generator sends a challenge to the graph using device, the graph using device is configured to generate an output based on the challenge, the output is sent to verifier, which verifies the output provided by the graph using device (based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands related to proof of space) where the various devices and entities may communicate with each other over a network, the challenge generator and the verifier are shown as separate entities and addressing the need of generating secure and equitable cryptocurrencies that inhibit undesirable behavior, encourage desirable behavior, and reduce energy consumption)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Jakobsson and apply them on teachings of Grosz and Therene for the method “communicating, by the memory sub-system using the network connection, with a cryptocurrency network; and generating, by the internal host independent of the host system, based on the amount and based on a type of proof of space activity specified for the internal host in the configuration data, commands to operate on memory cells in the memory sub-system in participation in proof of space activities in the cryptocurrency network”. One would be motivated as by allowing more participants, the Proof of Space technique provides the benefit like, of an improved digital currency that is not as speculation driven to be achieved (Jakobsson, (Paragraph [0057])).
As per claim 11:
Grosz, Therene and Jakobsson teach the method as specified in the parent claim 10 above.
Grosz further teaches:
“receiving the configuration data of the internal host from a user of the memory sub- system” (Paragraph [0022] and Paragraph [0026] (a host and a memory device configured to communicate over a communication interface where the host can include a variety of products including IoT devices consisting of user mobile communication device and user mobile phone etc. to support processing, communications, or control of the memory device and the memory controller is configured to maintain a host model of host interactions with the memory device))
“storing the configuration data in the memory cells” (Paragraph [0025] (the memory controller can receive instructions from the host via communication interface, and can communicate with the memory array such as to transfer data to one or more of the memory cells))
“controlling the internal host according to the configuration data” (Paragraph [0026] (the memory controller can also implement host adaptive optimization where the memory controller is configured to maintain a host model of host interactions with the memory device and this can be used to tailor a variety of memory device operations to meet this behavior)).
As per claim 12:
Grosz, Therene and Jakobsson teach the method as specified in the parent claim 11 above.
Grosz further teaches:
“wherein the configuration data is received via the host interface from the host system via a user interface running in the host system” (Paragraph [0022] (a host and a memory device configured to communicate over a communication interface where the host can include a variety of products including IoT devices consisting of user mobile communication device and user mobile phone etc.))
As per claim 14:
Grosz, Therene and Jakobsson teach the method as specified in the parent claim 11 above.
Grosz further teaches:
“wherein the configuration data specifies whether the internal host is allowed to operate autonomously and independent from the host system” (Paragraph [0035] (the array controller can include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the memory device and the memory operations can be based on internally generated by the memory manager independent of the host system commands))
“a condition to allow the internal host to operate autonomously, or an account identification, or any combination thereof” (Paragraph [0040] (the memory controller can be configured to actively detect and recover from error occurrences (e.g., bit errors, operation errors, crash conditions, stalls, hang ups, etc.) associated with various operations or storage of data, while maintaining integrity of the data transferred between the host and the memory device or maintaining integrity of stored data)).
Also, Jakobsson further teaches:
“a limit on resources usable by the internal host to participate in proof of space activities” (Paragraph [0148] (the Proof Of Space (PoSpace) techniques may be used to avoid/protect against spam, in order for a sender to send an email message to a recipient, the sender is required to provide a proof of space that relates to the message (a limit on resources) and the recipient will then determine whether the proof of space is valid)).
As per claim 15:
Grosz, Therene and Jakobsson teach the method as specified in the parent claim 10 above.
Grosz further teaches:
“generating, by the internal host independent of the host system, a plot; and writing, by the internal host, the plot to the memory cells” (Paragraph [0035] and Paragraph [0042] (the array controller can include the memory operations which can be based on internally generated by the memory manager independent of the host system commands and the memory manager can include a set of management tables (plots) configured to maintain various information associated with various information associated with a memory array or one or more memory cells coupled to the memory controller (writing, by the internal host, the plot to the memory cells))).
As per claim 16:
Grosz, Therene and Jakobsson teach the method as specified in the parent claim 10 above.
Jakobsson further teaches:
“receiving, via the network connection, a proof of space challenge” (Paragraph [0163] and Paragraph [0226] (a challenge is received as input via a network interface that supports communication over one or more networks)).
“and generating, by the internal host, a response to the proof of space challenge using the plot stored in the memory cells” (Paragraph [0164] (an output is generated using the received challenge and a stored graph and generating the output includes answering the received challenge by discovering some property of the stored graph)).
As per claim 17:
Grosz teaches:
“a memory sub-system, comprising” (Paragraph [0011]
(a memory system including))
“a data storage medium” (Paragraph [0011]
(memory arrays or devices can be combined together to form a storage volume such as a solid-state drive (SSD)))
“an interface configured to be coupled to a peripheral bus to receive commands from a host system” (Paragraph [0020] and Paragraph [0023] (a host adaptive memory device optimization can be used where the current host command activity (read commands and write commands from a host system) is measured and one or more communication interfaces can be used to transfer data between the memory device and the host))
“and a processing device configured to control executions of the commands to retrieve data from and store data to the data storage medium” (Paragraph [0025] (the memory controller can receive instructions from the host via communication interface, and can communicate with the memory array, such as to transfer data to (e.g., write or erase) or from (e.g., read) one or more of the memory cells of the memory array)).
Grosz does not EXPLICITLY disclose: a transceiver configured to: receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host; wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity; wherein the internal host is configured to generate, independent of the host system, based on the amount and based on a type of proof of space activity; specified for the internal host in the configuration data, commands to generate or farm plots of proof of space using a portion of the data storage medium.
However, in an analogous art, Therene teaches:
“a transceiver configured to: receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host” (Paragraph [0007], Paragraph [0043] and Paragraph [0131] (a System-on-Chip (SoC) is described that includes a media interface to access storage media of a storage system, a host interface to communicate with a host system, and an artificial intelligence engine where the SoC may include a transceiver interface configured to enable storage over a wired or wireless network, the media access manager may provide indications of host I/Os for storage media access to the AI engine which may use the indications of host I/O activity as inputs for the AI models to predict or forecast subsequent host system behavior (configuration data for controlling at least one operation of the internal host) and based on this prediction of host system behavior, the media access manager may schedule the host I/O and/or internal I/Os of the storage system, as well as adapt to user-specific workloads))
“wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity” (Paragraph [0117], Paragraph [0118], Paragraph [0119] and Paragraph [0121] (the information describing the host I/Os are provided to an artificial intelligence engine which may be associated with the storage system, a prediction of host behavior is received from the artificial intelligence engine including parameters regarding a next host I/O issued by the host system, a parameter for device-level management of the storage media is altered based on the prediction of host system behavior where the parameter may include a threshold for thermal management of storage media devices, or additionally, a threshold for garbage collection or data migration may be preempted or suspended to allow full host I/O performance for an access operation (specifies an amount of resources usable by the internal host) and the media I/Os that correspond to host I/Os of the host system are performed in accordance with the altered parameter for device-level management)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Therene and apply them on teachings of Grosz for the memory sub-system “a transceiver configured to: receive, over a network connection established under control of an internal host of the solid state drive, configuration data for controlling at least one operation of the internal host; wherein the configuration data specifies an amount of resources usable by the internal host to participate in at least one proof of space activity”. One would be motivated as the SoC also includes a media access manager, AI engine, and AI models, which may be implemented separately as shown or combined with a storage component, data interface, the media access manager may interact with the AI engine to generate a prediction of host behavior with respect to future storage media access and schedule, based on the prediction, internal operations to optimize storage media performance (Therene, (Paragraph [0131])).
Grosz and Therene do not EXPLICITLY disclose: specified for the internal host in the configuration data, commands to generate or farm plots of proof of space using a portion of the data storage medium.
However, in an analogous art, Jakobsson teaches:
“specified for the internal host in the configuration data, commands to generate or farm plots of proof of space using a portion of the data storage medium” (Paragraph [0054], Paragraph [0059], Paragraph [0062] and Paragraph [0075] (a component such as a processor or a memory internal host) described as being configured to perform a task (based on generating commands) may be implemented as a general component that is temporarily configured to perform the task at a given time, the proof-of-space technique described herein can be variously adapted for several other applications, the proof of space is to determine the value of node Vi where in order to compute the value of node Vi, then the predecessor node is examined, where the predecessor node has a value (Vi-1) and the values for the first and second godparents are used to generate the value Vi building the graph gradually)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Jakobsson and apply them on teachings of Grosz and Therene for the apparatus “specified for the internal host in the configuration data, commands to generate or farm plots of proof of space using a portion of the data storage medium”. One would be motivated as by allowing more participants, the Proof of Space technique provides the benefit like, of an improved digital currency that is not as speculation driven to be achieved (Jakobsson, (Paragraph [0057])).
As per claim 18:
Grosz, Therene and Jakobsson teach the memory sub-system as specified in the parent claim 17 above.
Grosz further teaches:
“wherein the memory sub-system is a solid state drive; and the data storage medium includes memory cells formed on at least one integrated circuit die” (Paragraph [0011], Paragraph [0024] and Paragraph [0025] (the memory device includes a memory controller, a solid-state drive (SSD), and a memory array consisting of one or more of the memory cells on one or more individual memory die)).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Grosz et al (US PGPUB 20200210104) in view of Therene et al (US PGPUB 20200133898) and in further view of Jakobsson Bjorn Markus (US PGPUB 20220368596) and Troia et al (US PGPUB 20200311314).
As per claim 7:
Grosz, Therene and Jakobsson teach the apparatus as specified in the parent claim 6 above.
Therene further teaches:
“an integrated circuit memory device configured to provide at least a portion of the memory cells to store the firmware” (Paragraph [0030] (the storage drive firmware is used to manage a data path of the storage drive in an end-to-end manner and the firmware of the storage drive typically schedules storage media access to facilitate these internal tasks against the storage media access associated with the data commands of the device)).
Grosz, Therene and Jakobsson do not EXPLICITLY disclose: the integrated circuit memory device having a security manager configured to prevent unauthorized access to the portion of the memory cells and to detect corruptions or changes in the firmware stored in the portion of the memory cells.
However, in an analogous art, Troia teaches:
“the integrated circuit memory device having a security manager configured to prevent unauthorized access to the portion of the memory cells and to detect corruptions or changes in the firmware stored in the portion of the memory cells” (Paragraph [0043] and Paragraph [0046] (the data stored in memory array can include sensitive data, such as host firmware and/or code to be executed for sensitive applications, once the secure array has been defined, circuitry can generate a cryptographic hash associated with the secure array, which may be referred to herein as a golden hash, using authenticated and antireplay protected commands, the golden hash may be stored in inaccessible portion of memory array which can be used during the process of validating the data of the secure array and if the comparison indicates the run-time cryptographic hash and golden hash do not match, this may indicate that the data stored in the secure array has been changed due to a hacker or a fault in the memory)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Troia and apply them on teachings of Grosz, Therene and Jakobsson for the Apparatus “the integrated circuit memory device having a security manager configured to prevent unauthorized access to the portion of the memory cells and to detect corruptions or changes in the firmware stored in the portion of the memory cells”. One would be motivated as many threats can affect the data stored in a memory like faults may occur in the array and/or circuitry of the memory, which can result in errors occurring in the data or a hacker or other malicious user may attempt to perform activities to make unauthorized changes to the data for malicious purposes which can cause significant financial loss, and/or can present significant safety and/or security issues (Troia, (Paragraph [0017])).
Claims 13, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Grosz et al (US PGPUB 20200210104) in view of Therene et al (US PGPUB 20200133898) and in further view of Jakobsson Bjorn Markus (US PGPUB 20220368596) and Shiner et al (US PGPUB 20220131700).
As per claim 13:
Grosz, Therene and Jakobsson teach the method as specified in the parent claim 12 above.
Grosz further teaches:
“wherein the configuration data specifies data to generate a plot” (Paragraph [0028] (the memory controller is configured to generate or update the model by computing an average or other statistical measure in relation to the commands after given time intervals or after a predetermined number of commands)).
Grosz, Therene and Jakobsson do not EXPLICITLY disclose: wherein the data specifies an account identification in a cryptocurrency network that includes a cryptographic key to represent part of an initial data.
However, in an analogous art, Shiner teaches:
“wherein the data specifies an account identification in a cryptocurrency network that includes a cryptographic key to represent part of an initial data” (Paragraph [0055] and Paragraph [0084] (during the validation of the identity of the computing device, the owner/subscriber of the computing device is identified through the ownership management service of the security server and the additional data can be used to generate a cryptographic key to represent the identity of the memory device and/or the owner/subscriber of the computing device)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Shiner and apply them on teachings of Grosz, Therene and Jakobsson for the Apparatus “wherein the data specifies an account identification in a cryptocurrency network that includes a cryptographic key to represent part of an initial data”. One would be motivated as the combination of the security features of the memory device and the security services of the security server allows various parties involved in the use of the memory device and/or the computing device having the confidence in the integrity of data stored in the memory device (Shiner, (Paragraph [0041])).
As per claim 19:
Grosz, Therene and Jakobsson teach the memory sub-system as specified in the parent claim 18 above.
Grosz further teaches:
“wherein the memory sub-system includes a memory device having the memory cells” (Paragraph [0011] (the memory device includes a memory controller, a solid-state drive (SSD), and a memory array consisting of one or more of the memory cells))
“the memory device is configured to store firmware executable by the processing device to implement the internal host and the configuration data of the internal host” (Paragraph [0038] and Paragraph [0041] (the memory manager can include, among other things, circuitry or firmware associated with various memory management functions and the memory manager internally generates host commands)).
Grosz, Therene and Jakobsson do not EXPLICITLY disclose: and the memory device is configured to determine integrity of the firmware and the configuration data of the internal host, and control write access to the memory cells based on privileges represented by cryptographic keys.
However, in an analogous art, Shiner teaches:
“and the memory device is configured to determine integrity of the firmware and the configuration data of the internal host, and control write access to the memory cells based on privileges represented by cryptographic keys” (Paragraph [0395] and Paragraph [0396] (the access controller of the memory device is configured to require the verification of a privilege to request the memory device to execute a command to make a change in firmware stored in the memory device, the cryptographic key can be previously configured, or generated in response to validating the identity data from the memory device of the endpoint and the security server can generate a verification code for the command using the cryptographic key for the firmware store to update the endpoint)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to take the teachings of Shiner and apply them on teachings of Grosz, Therene and Jakobsson for the memory sub-system “and the memory device is configured to determine integrity of the firmware and the configuration data of the internal host, and control write access to the memory cells based on privileges represented by cryptographic keys”. One would be motivated as by simply using the memory devices having the security features, the security of the computing devices that use the memory devices can be improved without much effort on the designers and/or manufacturer of the computing devices (Shiner, (Paragraph [0045])).
As per claim 20:
Grosz, Therene, Jakobsson and Shiner teach the memory sub-system as specified in the parent claim 19 above.
Therene further teaches:
“wherein the transceiver and the internal host are configured to use the transceiver to establish the network connection to a network without assistance from the host system” (Paragraph [0007] and Paragraph [0131] (a System-on-Chip (SoC) is described that includes a media interface to access storage media of a storage system, a host interface to communicate with a host system, and an artificial intelligence engine where the SoC also includes a hardware-based processor and a memory storing processor-executable instructions that, responsive to execution by the hardware-based processor, implement a media access manager to receive host input/outputs (I/Os) from the host system for access to the storage media of the storage system via the host interface and the SoC may also include communication interfaces, such as a transceiver interface for controlling or communicating with components of a local on-chip or off-chip communication transceiver)).
Also, Jakobsson further teaches:
“wherein the transceiver is configured to establish the network connection to a cryptocurrency network” (Paragraph [0180], Paragraph [0238] and Paragraph [0366] (the processing device includes network interface circuitry, which is used to interface the processing device with the network and other system components, may comprise conventional transceivers, the proof of space is coupled to a specific device type, Proof of Space (PoS) based mining proposals for cryptocurrencies have been proposed)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Steinmetz et al, (US PGPUB 20230185482), A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During a burn-in operation of the memory sub-system in a manufacturing facility, the memory sub-system is configured to perform read/write operations for the generation of a proof of space plot. After the burn-in operation, the memory sub-system is provided as a product of the manufacturing facility; and the proof of space plot stored in the memory sub-system is provided as a by-product.
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAMAL K DEWAN whose telephone number is (571)272-2196. The examiner can normally be reached on Mon-Fri 8:00 AM – 5:00 PM (EST). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TONY MAHMOUDI can be reached on 571-272-4078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kamal K Dewan/
Examiner, Art Unit 2163
/TONY MAHMOUDI/Supervisory Patent Examiner, Art Unit 2163
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