Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/9/2026 has been entered.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-8 and 10, 12-17 are rejected under 35 U.S.C 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1
According to the first part of the analysis, in the instant case, claims 1, 3-9 are directed to a microprocessor and claims 10, 12-18 are directed to a method. Therefore, claims 1-18 are directed to either a process, machine, manufacture or composition of matter.
Regarding claim 1
Step 2A Prong 1
“determining based on a prediction (abstract idea (e.g. evaluation that can practically be performed in the human mind or by a human using pen and paper) – a mental process. See MPEP 2106.04(a)(2) III C).
Claim 1 therefore recites an abstract idea.
Step 2A Prong 2
This judicial exception is not integrated into a practical application. Additional elements:
“A microprocessor comprising logic configured to cause:” (understood to be mere instructions to implement an abstract idea on a computer, or merely use a computer as a tool to perform an abstract idea – see MPEP 2106.05(f)).
“prediction from a machine learning model and wherein the machine learning model is trained specific to a particular algorithmic computation and a particular datatype.” (This step is adding the words “apply it” (or an equivalent) with the judicial exception, or merely applying a machine learning model as a tool to perform the abstract idea – see MPEP 2106.05(f)).
providing, as input to a machine learning model, a pair comprising a low precision input floating point number and, from an algorithmic computation, a low precision result floating point number and provided to an arithmetic logic unit in the microprocessor (extra solution activity as disclosed in MPEP 2106.05(g)).
The additional elements as disclosed above alone or in combination do not integrate the judicial exception into practical application as they are extra solution activity in combination with generic computer functions implemented to perform the disclosed abstract idea above.
Step 2B
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
“A microprocessor comprising logic configured to cause:” (understood to be mere instructions to implement an abstract idea on a computer, or merely use a computer as a tool to perform an abstract idea – see MPEP 2106.05(f)).
“prediction from a machine learning model and wherein the machine learning model is trained specific to a particular algorithmic computation and a particular datatype.” (This step is adding the words “apply it” (or an equivalent) with the judicial exception, or merely applying a machine learning model as a tool to perform the abstract idea – see MPEP 2106.05(f)).
providing, as input to a machine learning model, a pair comprising a low precision input floating point number and, from an algorithmic computation, a low precision result floating point number and provided to an arithmetic logic unit in the microprocessor (The recited limitation appears to be nothing more than well, understood, routine and conventional activity of receiving and transmitting data as identified by court MPEP 2106.05(d)).
The additional elements as disclosed above in combination of the abstract idea are not sufficient to amount to significantly more than the judicial exception as they are well, understood, routine and conventional activity in combination of generic computer functions being implemented with generic computer elements in a high level of generality to perform the disclosed abstract idea above.
Regarding claim 3
Step 2A Prong 1
“predict a high precision result floating point number of the algorithmic computation” and “wherein the compensation floating point number indicates a difference between the low precision result floating point number of the algorithmic computation and the high precision result floating point number” (abstract idea – mental process” (abstract idea – mental process, performing predictions can be done in the human mind (e.g. evaluation)).
Step 2A Prong 2 and 2B
This judicial exception is not integrated into a practical application. Additional elements:
“wherein the machine learning model is trained to predict a high precision result floating point number of the algorithmic computation;” (This step is adding the words “apply it” (or an equivalent) with the judicial exception, or merely using the machine learning model as a tool to perform the abstract idea – see MPEP 2106.05(f)).
Regarding claim 4
Step 2A Prong 1
“combining the compensation value with the low precision result floating point number to compensate for roundoff error in the algorithmic computation.” (abstract idea - a mental process (e.g. evaluation that can practically be performed in the human mind or by a human using pen and paper). See MPEP 2106.04(a)(2)).
Step 2A Prong 2 and 2B
This judicial exception is not integrated into a practical application. Additional elements:
“wherein the microprocessor is further configured to cause:” (understood to be mere instructions to implement an abstract idea on a computer, or merely use a computer as a tool to perform an abstract idea – see MPEP 2106.05(f)).
Regarding claim 5
Step 2A Prong 1: None
Step 2A Prong 2 and 2B
This judicial exception is not integrated into a practical application. Additional elements:
“wherein training the machine learning model comprises training the machine learning model using a training dataset comprising: pairs of low precision values where each pair contains a low precision result from the algorithmic computation, and pairs of high precision values that correspond to the pairs of low precision values.” (This step is adding the words “apply it” (or an equivalent) with the judicial exception, or merely applying the machine learning model as a tool to perform the abstract idea – see MPEP 2106.05(f)).
Regarding claim 6
Step 2A Prong 1: None
Step 2A Prong 2 and 2B
This judicial exception is not integrated into a practical application. Additional elements:
“wherein the machine learning model comprises a neural network.” (merely specifies a particular technological environment in which the abstract idea is to take place, ie. a field of use, and thus does not integrate the abstract idea into a practical application nor cannot provide significantly more than the abstract idea itself - see MPEP 2106.05(h)).
Regarding claim 7
Step 2A Prong 1: None
Step 2A Prong 2 and 2B
This judicial exception is not integrated into a practical application. Additional elements:
“wherein the machine learning model includes one or more rectified linear unit (ReLU) activation functions that are associated with one or more nodes of the machine learning model.” (merely specifies a particular technological environment in which the abstract idea is to take place, ie. a field of use, and thus does not integrate the abstract idea into a practical application nor cannot provide significantly more than the abstract idea itself - see MPEP 2106.05(h)).
Regarding claim 8
Step 2A Prong 1: None
Step 2A Prong 2 and 2B
This judicial exception is not integrated into a practical application. Additional elements:
“wherein the machine learning model includes multiple distinct activation functions that are associated with one or more nodes of the machine learning model.” (merely specifies a particular technological environment in which the abstract idea is to take place, ie. a field of use, and thus does not integrate the abstract idea into a practical application nor cannot provide significantly more than the abstract idea itself - see MPEP 2106.05(h)).
Claims 10, 12-17 are method claims having similar limitations as of apparatus claims 1, 2-17. Therefore they are rejected under the same rational.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 6, 10, 11, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Swagath Venkataramani et al. (US 20200005125), in view of Khailany et al. (US 20220067530).
Regarding claim 1, Swagath teaches:
“A microprocessor comprising logic configured to cause:
providing, as input to a machine learning model, a pair comprising a low precision input floating point number and, from an algorithmic computation, a low precision result floating point number (par. 15, par. 0027-29, par. 32; par. 34; the low precision input is X and Y and the low precision dot product result is X.Y)
determining, based on a prediction from a machine learning model and provided to an arithmetic logic unit in the microprocessor, a compensation value that that compensates for roundoff error in an algorithmic computation” (abstract, par. 14-15. Par.0031-0033 and 0035, A compensated deep neural network (DNN) is provided that performs Dot product operation on quantized value and estimates/predicts compensation of the quantized Dot product to reduce error in calculation. The Dot product calculation and compensation is performed on a processing element including a MAC unit and the output value along with the compensation instruction is provided to another processing element which implies the compensation value estimated/predicted by the DNN and provided to an arithmetic logic unit of the microprocessor.).
“wherein the machine learning model is trained specific to the algorithmic computation and a particular datatype.” (Swagath teaches that DNNs operate in two phases: training and inference [para. 0002] and DNN re-training is suggested as a strategy to minimize accuracy loss due to quantization [para. 0014]. Thus, it is implied that the DNN model regarding the invention has been trained (e.g. for a model to be re-trained it must first be trained). Regarding the datatype: “Some embodiments of the disclosure provide compensated-DNN, in which errors introduced by quantization are dynamically compensated during execution. Numbers in compensated-DNN are represented in Fixed Point with Error Compensation (FPEC) format. The bits in FPEC are split between computation bits and compensation bits.” [para. 0015]).
Swagath discloses using a numeric format of floating point and fixed point in combination (par. 15, par. 20) but does not specifically disclose the low precision inputs/values are floating point number.
Khailany discloses providing as input to the machine learning model low precision floating point numbers (par. 25 and 34).
It would have been obvious to a person of ordinary skill in art before the effective filling date of the invention to implement the teaching of Khailany into the method of Swagath to have the format of the numeric calculation in floating point format. A person of ordinary skill of the art would have been motivated to perform the combination for being able to perform quantization operation of values in any numeric format in the machine learning models/DNN since the models are capable of performing operations in different numeric format for performing efficient arithmetic operations/calculation of a computer.
Regarding claim 4, Swagath teaches combining the compensation value with the low precision result to compensate for roundoff error in the algorithmic computation.” ([0015], “In some embodiments, a low-overhead sparse compensation scheme based on the compensation bits is used to estimate the error accrued during MAC operations, which is then added to the MAC output to minimize the impact of quantization.” The compensation bits are added to the MAC output (low precision result) to approximate the error and later add it back to the MAC output to compensate for quantization (roundoff) error).
Swagath discloses using a numeric format of floating point and fixed point in combination (par. 15, par. 20) but does not specifically disclose the low precision inputs/values are floating point number.
Khailany discloses providing as input to the machine learning model low precision floating point numbers (par. 25 and 34).
Regarding claim 6, Swagath teaches“wherein the machine learning model comprises a neural network.” ([0015], “Some embodiments of the disclosure provide compensated-DNN, in which errors introduced by quantization are dynamically compensated during execution.”).
Regarding claims 10, 13 and 15, they are method claims having similar limitations as of apparatus claims 1, 4 and 6. Therefore they are rejected under the same rational.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Swagath in view of Khailany and in view of Van Baalen et al. (US 20200302298 A1, hereinafter "Van Baalen").
Regarding claim 3, Swagath teaches “wherein the compensation value indicates a difference between the low precision result value of the algorithmic computation and the high precision result value” ([0034], The compensation unit evaluates the quantization error (i.e. the difference between low and high result values) at the dot-product output using the compensation bits. “This involves shifting the X vector component using EMB bits of xi (at shifter 421) and the Y vector component using EMB bits of yi (at shifter 422) and appropriately adding/subtracting (at adder 424) them from the compensation sum (at adder 426 and ErrComp register 428) based on the respective EDB bits.”
Swagath in view of Khailany do not disclose: “wherein the machine learning model is trained to predict a high precision result value of the algorithmic computation;”
However, Van Baalen discloses in the same field of endeavor: “wherein the machine learning model is trained to predict a high precision result value of the algorithmic computation;” ([Abstract and 0017], Neural networks trained to perform various functions on a target computing device are generated by a computer learning environment that trains a neural network using a training data set. “Various embodiments include methods and neural network computing devices implementing the methods for methods for method for generating an approximation neural network correcting for errors due to approximation operations.” and “A CLE computing device may have a precision or “bit-width” (e.g., capable of 32-bit floating point (FP) operations) as well as processing resources (e.g., energy, FLOPS, etc.) great than the precision or bit-width and processing resources of the target computing device on which the trained neural network will be implemented.”).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to improve the performance of neural networks executing using low-precision values by reducing errors resulting from post-training approximations [Van Baalen: para. 0019].
Regarding claim 12, This claim recites a method that performs the steps of the method described in claim 3 and therefore is rejected under the same rationale/reasons of claim 3.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Swagath in view Khailnay and further in view of Jain “Compensated-DNN: Energy Efficient Low-Precision Deep Neural Networks by Compensating Quantization Errors”.
Regarding claim 5, Swagath in view of Khaliany do not specifically disclose wherein training the machine learning model comprises training the machine learning model using a training dataset comprising: pairs of low precision values where each pair contains a low precision result from the algorithmic computation, and pairs of high precision values that correspond to the pairs of low precision values.
However, Jain teaches wherein training the machine learning model comprises training the machine learning model using a training dataset comprising :pairs of low precision values where each pair contains a low precision result from the algorithmic computation, and pairs of high precision values that correspond to the pairs of low precision values (page 2, right column, section 3.2; page 3, left column, “Determining FxP Range and Resolution”, right column, section 4.1; page 5, left column, 4.4 entire section including algorithm 1 until section 5; the cited section discloses how model is initially executed on a set of data for in a DNN with non-quantized mode to collect statistics of the model on a validation set which implies collecting high precision input and output data of the model then the data is being quantized to learn the compensation value training the model and comparing with the actual output for loss calculation which implies training with pairs of low precision value and low precision output).
It would have been obvious to a person of ordinary skill in art before the effective filling date of the invention to implement the teaching of Jain into the combined teaching of Khailany and Swagath to have pair od high precision and low precision value for training the model. A person of ordinary skill of the art would have been motivated to perform the combination for being able to perform training of the compensated DNN given the data statistics needed for correct evaluation of performance of the model for being able to generate proper compensation value and provide efficient operation of the DNN without loosing accuracy.
Regarding claim 14,This claim recites a method that performs the steps of the method described in claim 5 and therefore is rejected under the same rationale/reasons of claim 5.
Claims 7-9 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Swagath in view of Khailany in view of "Troia" (US 20210065754 A1).
Regarding claim 7, Swagath teaches: “wherein the machine learning model” ([Abstract], “A compensated deep neural network is provided”).
Swagath in view of Khailany do not disclose: “wherein the machine learning model includes one or more rectified linear unit (ReLU) activation functions that are associated with one or more nodes of the machine learning model.”
However, Troia teaches: “wherein the machine learning model includes one or more rectified linear unit (ReLU) activation functions that are associated with one or more nodes of the machine learning model.” ([0018], “In a number of embodiments, the activation functions can be pre-defined activation functions and/or custom activation functions.” ReLU is included/listed as a pre-defined activation function, among other common activation functions).
It would be obvious to one of ordinary skill in the art before the effective filing data of the claimed invention to have a machine learning model which utilizes one or more activation functions (e.g. ReLU) for the model to predict/calculate high precision results and compensation values.
Regarding claim 8, Troia teaches “wherein the machine learning model includes multiple distinct activation functions that are associated with one or more nodes of the machine learning model.” ([0081], there are multiple distinct activation functions selected for each layer of the machine learning model. “An activation function can be selected among pre-defined and custom activation functions based on the result of the previous AI operation and a different activation function can be selected for each layer.” Regarding nodes, memory arrays may be individual nodes that may store data and/or weights to be combined with input data and summed (operated on) then passed to an activation function [para. 0032]).
Regarding claim 9, Troia teaches “wherein the one or more nodes include gates that are configured to select one or more activation functions of the multiple distinct activation functions to combine into an approximation of a target algorithmic computation.” ([0108 and FIG. 8], the memory arrays can be considered as nodes [para. 0032] and according to FIG. 8, the sensing circuitry of a memory device shows there are two pass gates 8172-1 and 8172-2 that are coupled to the operation selection logic 8178. Recall that activation functions are located in registers on the memory device [para. 0017]. Regarding being configured to select one or more distinct activation functions to be combined, [0081] “In some examples, the number of activation functions 6122-1, . . . , 6122-13 can be modified (e.g., changed) to a custom activation function. As discussed in connection with FIG. 3B, a custom activation function can be created based on a result of a previous AI operation. In some examples, a custom activation function can be based on a result of a previous AI operation and one or more of the number of activation functions 6122-1, . . . , 6122-13. An activation function can be selected among pre-defined and custom activation functions based on the result of the previous AI operation and a different activation function can be selected for each layer.” Activation functions from the disclosed, non-exhaustive list of activation functions 6122-1,…, 6122-13 [para. [0080]. All hidden/intermediate layers (along with their multiple distinct activation functions) are combined into the output layer/node of a neural network to obtain the output value or result. Regarding an approximation of a target algorithmic computation, [0098] “Operations described herein can include operations associated with a processing in memory (PIM) capable device. PIM capable device operations can use bit vector based operations. As used herein, the term “bit vector” is intended to mean a physically contiguous number of bits on a bit vector memory device (e.g., a PIM device) stored physically contiguous in a row of an array of memory cells. Thus, as used herein a “bit vector operation” is intended to mean an operation that is performed on a bit vector that is a contiguous portion of virtual address space (e.g., used by a PIM device)”. Also, the compute operations may include addition and subtraction [para. 0090]. Target algorithmic computation is the expected output of the machine learning model after the input values have been operated on).
Regarding claims 16-18, These claims recite a method that performs the steps of the methods described in claim 7-9 and therefore are rejected under the same rationale/reasons of claims 7-9.
Response to Arguments
Applicant's arguments filed 11/26/2025 along with claims amendment have been fully considered and the argument regarding 101 and 103 rejections are not persuasive.
In Remarks applicant Agues:
Argument Regarding 101 rejection: Applicant argues that the claimed invention is improving accuracy and stability in of the internal operation of the microprocessor in an by unconventional way therefore the claimed invention is integrated in practical application and therefore patent eligible.
Response to argument: Examiner respectfully disagrees with applicant. Applicant argues the claimed invention avoids any conversion of data which is unconventional and improves accuracy of the system by generating the compensation value. The claimed limitations as recited do not specifically disclose any claimed limitations that specifically discloses any internal operation of a microprocessor or how that operation is improving accuracy or stability in the internal operation in an unconventional manner. Also applicant’s argument regarding conversion of data is convention and the claimed invention not performing that is unconventional is not persuasive the aspect of conversion of data performing operation without conversion is nothing more than a abstract idea itself as mental process or mathematical operation in the aspect of numerical calculation. The claim limitation as recites rather discloses determining a compensation of roundoff error which is a mental process because a person mentally with the aid of pen and paper calculate any roundoff error in a calculation and determine a compensation that would be needed for the roundoff error. The claim only recites performing the operation using a generic machine learning model without any specific detail or technical detail or any unconventional manner/technique that is being performed in the claim to achieve the claimed improvement as claimed. In fact the claim does not disclose any detail or any steps how this unconventional improvement is being performed rather having a generic allegation that claimed invention if performing an unconventional improvement. Therefore the claimed improvement as recited in the instant independent claim is nothing more than an abstract idea. Similarly applicant’s argument that all the claims are eligible subject matter is not persuasive.
Argument and response regarding 103 Rejection:
Applicant’s argument regarding 103 rejection has been considered, however they are moot in view of the new ground of rejection.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDULLAH AL KAWSAR whose telephone number is (571)270-3169. The examiner can normally be reached M-F 7:30am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Wiley can be reached at (571) 272-4150. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABDULLAH AL KAWSAR/ Supervisory Patent Examiner, Art Unit 2127
