DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/23/2025 has been entered.
Other Reference: 10637665 Blockchain-based digital identity management system.
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (subject to any rejection below).
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for indicating allowanability:
For Claims 22, the prior art discloses and/or renders obvious the limitations from Claim 1. The prior art does not appear to disclose the limitations from Claims 22.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-22 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is not showing of support for the amended limitations and new Claim, from the original disclosure. If support is not shown, then these limitations must be removed from the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 10, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (US 20200119903) and further in view of Agrawal (US 20230168825) and Jakobsson (US 11418402)
Claim 1. Tarango discloses An apparatus (e.g., computing system 400, 0042 Fig. 4), comprising:
a solid state drive (e.g., SSD, 0020), having:
a host interface configured to receive at least read commands and write commands from a host system (e.g., SSD/host interface, 0026; host applications that use the SSD as mass storage invoke the SSD's footprint/application in system memory via an API with the LBA for the affected block(s) being specified through the API. The SSD footprint/application then performs the LBA-to-PBA mapping and issues the corresponding command (e.g., read, program) with the PBA to the SSD., 0033);
memory cells formed on at least one integrated circuit die (e.g., memory cells integrated amongst the interconnect wiring of a semiconductor chip, 0041);
a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells (e.g., main memory controller 417 interfaces with the system memory 402 to write/read data to/from system memory 402, 0043); and
a computation accelerator adapted to perform a type of computations involved in generation of (e.g., enable any on-board SSD accelerators as desired (e.g., cyclic redundancy check (CRC)/error correction coding (ECC) accelerator, encryption/decryption accelerator, media channel queue accelerator, performance trace analysis accelerators, numerical computation accelerators). , 0029)(further, Tarango discloses configuration of a hardware accelerator within the solid state drive (0049) register space is to implement any of the following: i) enabling a memory chip within the solid state drive; and, ii) enabling a static or dynamic hardware accelerator within the solid state drive (0050). computing system can also include other types of processing units that are tangential to cores 415 such as: 1) an artificial intelligence processing unit to execute neuro-network synapse-based operations to learn and optimize based on state; 2) at least one reconfigurable processing unit composed of an array of memory blocks and accelerators to compute specialized operations (0043). SSD's internal command queue state (0035). SSD has encryption/decryption accelerator (0029). ; encryption; configuration of a hardware accelerator within the solid state drive (0055). One of ordinary skill would have known according to Tarango, that the accelerators included in the SSD do perform/implement computations on-board).
Tarango does not disclose, but Thomas discloses
wherein the type of computations involved in generation of proof of space plots include matrix computations (e.g., Processor 132 further includes accelerators 146 configured to perform acceleration for various data-processing functions, such as look-ups, matrix multiplication,,… 0058, Fig. 2; SSD, 0054; accelerators 189 perform acceleration for various data-processing functions, such as table lookups, matrix multiplication, cryptography, 0079 ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Cousineau, with Thomas, providing the benefit of techniques for efficient performance of cryptographic operations (e.g., encryption, decryption, and/or generation of secure hash values) may provide technical benefits that include reliably supporting multiple modes of operation with a streamlined, unified, and/or efficient design (see Thomas, 0034) addressing the problem in the art cryptographic operations relating to security and other functions may require and/or consume substantial computing resources (0004).
Tarango in view of Thomas does not disclose, but Agrawal discloses
proof of space plots; wherein generated proof of space plots are configured to be used to generate a proof of space response to a proof of space challenge (eg., 0053 - FIG. 1 and may be used by a proof generator of a trusted circuit (e.g., proof generator 116 of trusted circuit 110 illustrated in FIG. 1) to satisfy challenges, or validation requests, for data stored in the storage device)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal providing the benefit of when a participating device in the distributed data storage system generates a challenge to verify the existence of data in the distributed data storage system, the participating device may transmit a query including an address at which the data is expected to be located to the storage device on which the data is expected to be located… improving the efficiency of operations involved in generating and returning proofs of storage in the distributed data storage system (see Agrawal, 0054) data can be offloaded for storage in the distributed data storage system and from which requests to prove the existence of data on a storage device in the distributed data storage system can be issued (0062).
Tarango in view of Thomas and Agrawal does not disclose, but Jakobsson discloses
wherein the proof of space response proves that the solid state drive has a predetermined amount of data storage space (eg., col 20:51-55 FIG. 8 - of a process for initializing a graph for providing proof of space. process 800 is executed by graph generating device 702 of FIG. 7. The process begins at 802, when an initial graph is generated at a device; col 21:10-20 - At 804, at least a portion of the initial graph is stored on the device.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal with Jakobsson, providing the benefit of an improved Proof of Space … spare computation resources (e.g., on their mobile phones, tablets, electrical outlets, etc.), they can be utilized (see Jakobsson, col 4:31-55).
Claim 10. Tarango discloses A method (e.g., computing system 400, 0042 Fig. 4), comprising:
receiving, in a solid state drive from a host system connected to a host interface of the solid state drive, configuration data (e.g., SSD/host interface, 0026; host applications that use the SSD as mass storage invoke the SSD's footprint/application in system memory via an API with the LBA for the affected block(s) being specified through the API. The SSD footprint/application then performs the LBA-to-PBA mapping and issues the corresponding command (e.g., read, program) with the PBA to the SSD., 0033);
memory cells formed on at least one integrated circuit die (e.g., memory cells integrated amongst the interconnect wiring of a semiconductor chip, 0041);
performing, by the solid state drive according to the configuration data cells (e.g., each SSD commonly includes a controller and associated memory to execute logic 111_1 through 111_X that oversees the operation of the SSD, 0014); and
accelerating, using a computation accelerator of the solid state drive, the computations of proof of space activities. device (e.g., enable any on-board SSD accelerators as desired (e.g., cyclic redundancy check (CRC)/error correction coding (ECC) accelerator, encryption/decryption accelerator, media channel queue accelerator, performance trace analysis accelerators, numerical computation accelerators). , 0029). (further, Tarango discloses configuration of a hardware accelerator within the solid state drive (0049) register space is to implement any of the following: i) enabling a memory chip within the solid state drive; and, ii) enabling a static or dynamic hardware accelerator within the solid state drive (0050). computing system can also include other types of processing units that are tangential to cores 415 such as: 1) an artificial intelligence processing unit to execute neuro-network synapse-based operations to learn and optimize based on state; 2) at least one reconfigurable processing unit composed of an array of memory blocks and accelerators to compute specialized operations (0043). SSD's internal command queue state (0035). SSD has host interface… and on-board SSD accelerators… ECC accelerator, numerical computation accelerators (0029). One of ordinary skill would have known according to Tarango, that the accelerators included in the SSD do perform/implement computations on-board).
Tarango does not disclose, but Thomas discloses
activities (e.g., Processor 132 further includes accelerators 146 configured to perform acceleration for various data-processing functions, such as look-ups, matrix multiplication,,… 0058, Fig. 2; SSD, 0054; accelerators 189 perform acceleration for various data-processing functions, such as table lookups, matrix multiplication, cryptography, 0079 ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, providing the benefit of techniques for efficient performance of cryptographic operations (e.g., encryption, decryption, and/or generation of secure hash values) may provide technical benefits that include reliably supporting multiple modes of operation with a streamlined, unified, and/or efficient design (see Thomas, 0034) addressing the problem in the art cryptographic operations relating to security and other functions may require and/or consume substantial computing resources (0004).
Tarango in view of Thomas does not disclose, but Agrawal discloses
computations of proof of space ; wherein the proof of space activities prove that the solid state drive has a predetermined amount of data storage space (eg., 0053 - FIG. 1 and may be used by a proof generator of a trusted circuit (e.g., proof generator 116 of trusted circuit 110 illustrated in FIG. 1) to satisfy challenges, or validation requests, for data stored in the storage device; 0021 proofs of replication that mathematically prove the existence of some number of copies of data, or proofs of space-time)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal providing the benefit of when a participating device in the distributed data storage system generates a challenge to verify the existence of data in the distributed data storage system, the participating device may transmit a query including an address at which the data is expected to be located to the storage device on which the data is expected to be located… improving the efficiency of operations involved in generating and returning proofs of storage in the distributed data storage system (see Agrawal, 0054) data can be offloaded for storage in the distributed data storage system and from which requests to prove the existence of data on a storage device in the distributed data storage system can be issued (0062).
Tarango in view of Thomas and Agrawal does not disclose, but Jakobsson discloses
wherein the proof of space response proves that the solid state drive has a predetermined amount of data storage space (eg., col 19:10-19 - Alice needs to show that she has this graph relative to the email and to Bob (i.e., proof that she has stored something, such as the graph). If she did not have the graph, then other users would not accept/receive email from her. Proving she has the graph stored proves that she has a certain right to send emails. Bob would then verify that the sender has a certain amount of storage space,)
wherein the proof of space response proves that the solid state drive has a predetermined amount of data storage space (eg., col 20:51-55 FIG. 8 - of a process for initializing a graph for providing proof of space. process 800 is executed by graph generating device 702 of FIG. 7. The process begins at 802, when an initial graph is generated at a device; col 21:10-20 - At 804, at least a portion of the initial graph is stored on the device.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal with Jakobsson, providing the benefit of an improved Proof of Space … spare computation resources (e.g., on their mobile phones, tablets, electrical outlets, etc.), they can be utilized (see Jakobsson, col 4:31-55).
Claim 17. Tarango discloses A memory sub-system (e.g., computing system 400, 0042 Fig. 4), comprising:
a data storage medium (e.g., SSD, 0020)
an interface configured to be coupled to a peripheral bus to receive commands from a host system; (e.g., SSD/host interface, 0026; host applications that use the SSD as mass storage invoke the SSD's footprint/application in system memory via an API with the LBA for the affected block(s) being specified through the API. The SSD footprint/application then performs the LBA-to-PBA mapping and issues the corresponding command (e.g., read, program) with the PBA to the SSD., 0033);
memory cells formed on at least one integrated circuit die (e.g., memory cells integrated amongst the interconnect wiring of a semiconductor chip, 0041);
a processing device configured to control executions of the commands to retrieve data from and store data to the data storage medium (e.g., main memory controller 417 interfaces with the system memory 402 to write/read data to/from system memory 402, 0043); and
a computation accelerator adapted to perform a type of computations involved in generation of more efficient than the processing device (e.g., enable any on-board SSD accelerators as desired (e.g., cyclic redundancy check (CRC)/error correction coding (ECC) accelerator, encryption/decryption accelerator, media channel queue accelerator, performance trace analysis accelerators, numerical computation accelerators). , 0029). (further, Tarango discloses configuration of a hardware accelerator within the solid state drive (0049) register space is to implement any of the following: i) enabling a memory chip within the solid state drive; and, ii) enabling a static or dynamic hardware accelerator within the solid state drive (0050). computing system can also include other types of processing units that are tangential to cores 415 such as: 1) an artificial intelligence processing unit to execute neuro-network synapse-based operations to learn and optimize based on state; 2) at least one reconfigurable processing unit composed of an array of memory blocks and accelerators to compute specialized operations (0043). SSD's internal command queue state (0035). SSD has host interface… and on-board SSD accelerators… ECC accelerator, numerical computation accelerators (0029). One of ordinary skill would have known according to Tarango, that the accelerators included in the SSD do perform/implement computations on-board).
Tarango does not disclose, but Thomas discloses
in cryptocurrency activities (e.g., Processor 132 further includes accelerators 146 configured to perform acceleration for various data-processing functions, such as look-ups, matrix multiplication,,… 0058, Fig. 2; SSD, 0054; accelerators 189 perform acceleration for various data-processing functions, such as table lookups, matrix multiplication, cryptography, 0079 ).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Cousineau, with Thomas, providing the benefit of techniques for efficient performance of cryptographic operations (e.g., encryption, decryption, and/or generation of secure hash values) may provide technical benefits that include reliably supporting multiple modes of operation with a streamlined, unified, and/or efficient design (see Thomas, 0034) addressing the problem in the art cryptographic operations relating to security and other functions may require and/or consume substantial computing resources (0004).
Tarango in view of Thomas does not disclose, but Agrawal discloses
to use the computation accelerator to perform at least a portion of computations (eg., [0028] FIG. 1 depicts an example storage device 100 having a trusted circuit 110 for generating anonymous signatures for data stored on the storage device interposed on a write path to storage circuitry of the storage device,)
comprising at least one of plot generation or plot farming (eg., [0032] Proof generator 116 generally is configured to generate anonymous digital signatures evidencing the storage of data to storage circuitry 120 and to validate the existence of data written to storage circuitry 120 upon request.).
wherein the plot generation is configured to generate proof of space plots for proof of space calculations or the plot farming is configured to generate a proof of space response to a proof of space challenge (eg., 0053 - FIG. 1 and may be used by a proof generator of a trusted circuit (e.g., proof generator 116 of trusted circuit 110 illustrated in FIG. 1) to satisfy challenges, or validation requests, for data stored in the storage device; 0035 - proof generator 116 can sign information related to the latest block of the blockchain)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal providing the benefit of when a participating device in the distributed data storage system generates a challenge to verify the existence of data in the distributed data storage system, the participating device may transmit a query including an address at which the data is expected to be located to the storage device on which the data is expected to be located… improving the efficiency of operations involved in generating and returning proofs of storage in the distributed data storage system (see Agrawal, 0054) data can be offloaded for storage in the distributed data storage system and from which requests to prove the existence of data on a storage device in the distributed data storage system can be issued (0062) cryptocurrency systems (0002).
Tarango in view of Thomas and Agrawal does not disclose, but Jakobsson discloses
wherein the memory sub-system is further configured to generate write commands to store the proof of space plots (eg., col 20:51-55 FIG. 8 - of a process for initializing a graph for providing proof of space. process 800 is executed by graph generating device 702 of FIG. 7. The process begins at 802, when an initial graph is generated at a device; col 21:10-20 - At 804, at least a portion of the initial graph is stored on the device.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal with Jakobsson, providing the benefit of an improved Proof of Space … spare computation resources (e.g., on their mobile phones, tablets, electrical outlets, etc.), they can be utilized (see Jakobsson, col 4:31-55).
5. Claims 2, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and further in view of Murck (US 20220083683)
Claim 2. Tarango in view of Thomas and Agrawal and Jakobsson does not disclose, but Murck discloses
wherein the computation accelerator is configured to accelerate Basic Linear Algebra Subprograms (BLAS) (e.g., GPU-accelerated basic linear algebra (BLAS) library, 0070).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, and Thomas and Agrawal and Jakobsson with Murck, providing the benefit of distributed self-governing computer system to correlate transactions on a blockchain computer system with transactions on a private computer system (see Murck, 0001) a distributed blockchain computer system which can correlate transactions on the distributed blockchain computer system with transactions in a private computer system (0015).
Claim 11 is rejected for reasons similar to Claim 2 above.
6. Claims 3,5,6,7,13,14 are rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and further in view of Murck (US 20220083683) and Cousineau (US 10729030)
Claim 3. Tarango in view of Thomas, Agrawal and Jakobsson and Murck does not disclose, but Cousineau discloses
, wherein the computation accelerator includes a Multiply-Accumulate (MAC) Unit (e.g., include multiply-accumulate operations, linear algebra operations, col 14:54-55).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, in view of Thomas, Agrawal and Jakobsson and Murck with Cousineau, providing the benefit of especially suited to, or beneficial for, the performance of specific types of mathematical operations (see Cousineau, col 14:52-55) hardware accelerator 504 may include application-specific hardware circuitry 506 designed to perform a specific computing task (col 14:3-5) such that the performance of the application is more efficient (e.g., in terms of computing resources, electrical resources, etc.) than when executed otherwise (col 13:65- col 14:2).
Claim 5. Tarango in view of Thomas, Agrawal and Jakobsson and Murck does not disclose, but Cousineau discloses
wherein the Multiply-Accumulate (MAC) Unit includes a logic circuit configured to perform multiplication and accumulation operations (e.g., mathematical operations, which may include multiply-accumulate operations, col 14:53-55).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, in view of Thomas, Agrawal and Jakobsson and Murck with Cousineau, providing the benefit of especially suited to, or beneficial for, the performance of specific types of mathematical operations (see Cousineau, col 14:52-55) hardware accelerator 504 may include application-specific hardware circuitry 506 designed to perform a specific computing task (col 14:3-5) such that the performance of the application is more efficient (e.g., in terms of computing resources, electrical resources, etc.) than when executed otherwise (col 13:65- col 14:2) customized or special-purpose designed to perform, in hardware, any type or form of computation-intensive computing task to thereby alleviate a burden on one or more general-purpose central processing units (i.e., by performing the computing task on a separate chip than the central processing unit and/or by performing the computing task more efficiently in hardware than in software) (see col 14:59-65).
Claim 6. Tarango in view of Thomas, Agrawal and Jakobsson and Murck does not disclose, but Cousineau discloses
wherein the computation accelerator is further adapted to perform cryptographic operations involved in cryptocurrency activities (e.g., cryptographic accelerators, col 15:42-45). (further, Consineau discloses the hardware accelerator may offload at least a portion of the computing task from the central processing unit by executing, via the application-specific hardware circuitry, the portion of the computing task (col 3:1-5) hardware accelerator 504 of expansion card 500 may be customized or special-purpose designed to perform, in hardware, one or more specific computing tasks … hardware accelerator 504 of expansion card 500 may be especially suited to, or beneficial for, the performance of specific types of mathematical operations (col 14:36-65) an SSD carrier card or a device carrier card (col 19:38-40)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, in view of Thomas, Agrawal and Jakobsson and Murck with Cousineau, providing the benefit of especially suited to, or beneficial for, the performance of specific types of mathematical operations (see Cousineau, col 14:52-55) hardware accelerator 504 may include application-specific hardware circuitry 506 designed to perform a specific computing task (col 14:3-5) such that the performance of the application is more efficient (e.g., in terms of computing resources, electrical resources, etc.) than when executed otherwise (col 13:65- col 14:2) customized or special-purpose designed to perform, in hardware, any type or form of computation-intensive computing task to thereby alleviate a burden on one or more general-purpose central processing units (i.e., by performing the computing task on a separate chip than the central processing unit and/or by performing the computing task more efficiently in hardware than in software) (see col 14:59-65).
Claim 7. Tarango in view of Thomas and Agrawal and Jakobsson does not disclose, but Murck discloses
wherein the solid state drive has an internal host configured to perform operations of the cryptocurrency activities (e.g., Computer device memory 250 may also store operating system 280 or the equivalent, 0073, 0076; blockchain execution module 400 creates one or more distributed, self-governing blockchain computer system 130, 0031; proof-of-stake blockchain computer systems which generate the tokens or cryptocurrency required to operate the network, 0032).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, and Thomas and Agrawal and Jakobsson with Murck, providing the benefit of distributed self-governing computer system to correlate transactions on a blockchain computer system with transactions on a private computer system (see Murck, 0001) a distributed blockchain computer system which can correlate transactions on the distributed blockchain computer system with transactions in a private computer system (0015).
Claim 13 is rejected for reasons similar to Claim 5 above.
Claim 14. Tarango in view of Thomas, Agrawal and Jakobsson and Murck does not disclose, but Cousineau discloses
receiving, in the solid state drive, commands from the host system to pre-process data using the computation accelerator; and executing, by the solid state drive, the commands using the computation accelerator (e.g., hardware accelerator may offload at least a portion of the computing task from the central processing unit by executing, via the application-specific hardware circuitry, the portion of the computing task, col 3:1-5).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, in view of Thomas, Agrawal and Jakobsson and Murck with Cousineau, providing the benefit of especially suited to, or beneficial for, the performance of specific types of mathematical operations (see Cousineau, col 14:52-55) hardware accelerator 504 may include application-specific hardware circuitry 506 designed to perform a specific computing task (col 14:3-5) such that the performance of the application is more efficient (e.g., in terms of computing resources, electrical resources, etc.) than when executed otherwise (col 13:65- col 14:2).
7. Claims 4, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and Murck (cited above) and Cousineau (US 10729030), and further in view of Dazzi (US 10831691)
Claim 4. Tarango in view of Thomas and Agrawal and Jakobsson and Murck and Cousineau does not disclose, but Dazzi discloses
wherein the Multiply-Accumulate (MAC) Unit includes a crossbar array of memristors configured to perform multiplication and accumulation operations via analog circuitry (e.g., processing elements may be in-memory computational units such as memristor crossbar arrays and/or digital units, col 3:55-57).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, and Thomas and Agrawal and Jakobsson with Murck, and Cousineau with Dazzi, providing the benefit of enable to implement an interconnection topology that is flexible enough to be used for the majority of the CNN architectures and which can scale with the depth of the networks. Thus, the present subject matter may enable a scalable solution. This may particularly be advantageous as the size of a neural network can vary depending on the type of classification that needs to be performed and on the attainable accuracy, and thus the infrastructure must also be scalable (see col 3:45-54).
Claim 12 is rejected for reasons similar to Claims 3 and 4 above.
8. Claims 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and further in view of Murck (cited above) and Cousineau (US 10729030) and Yang (US 2023005323269)
Claim 8. Tarango in view of Thomas and Agrawal and Jakobsson and Murck does not disclose, but Yang discloses
wherein the operations of the cryptocurrency activities include plot generation and plot farming (e.g., mining… generating plots of data… long term storage, 0050; a cryptocurrency minor can utilize their new SSD in a QLC mode to store a first number of plots, e.g., forty 100 GB plots in 4 TB of capacity. Those plots are continuously programmed and erased with the SSD operating in the QLC mode, 0052).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas and Agrawal and Jakobsson with Murck, with Yang, providing the benefit of to memory devices that are optimized for use in the mining of certain types of cryptocurrencies (see Yang, 0001, 0049).
Claim 9. Tarango discloses an integrated circuit memory device configured to provide at least a portion of the memory cells to store firmware, software, or an operating system, or any combination thereof (e.g., SSD controller, through execution of the SSD's local firmware, processes the commands , 0020)
and to detect corruptions or changes in data stored in the portion of the memory cells (e.g., program code is to program register space within the solid state drive. The register space is to implement any of the following: i) enabling a memory chip within the solid state drive; and, ii) enabling a static or dynamic hardware accelerator within the solid state drive. The register space is to implement any of the following: i) whether error detection is to be enabled; ii) what type of error detection is to be applied; and, ii) controller status or state to be enabled or/and applied, 0050).
Tarango in view of Thomas does not disclose, but Agrawal discloses
the computation accelerator including a cryptographic engine used by a security manager of the integrated circuit memory device to prevent unauthorized access to the portion of the memory cells (e.g., 0021 - A cryptographic proof may represent computation as an arithmetic circuit of addition and multiplication gates and involve one or more operations having a computational cost similar to that of public-key encryption per gate of the circuit. Because the cryptographic proof involves public-key cryptographic operations on a per-gate basis, ; 0079 - a trusted circuit having a private signing key securely stored thereon, the trusted circuit being configured to: compute a hash over data stored in a plurality of data blocks)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal providing the benefit of when a participating device in the distributed data storage system generates a challenge to verify the existence of data in the distributed data storage system, the participating device may transmit a query including an address at which the data is expected to be located to the storage device on which the data is expected to be located… improving the efficiency of operations involved in generating and returning proofs of storage in the distributed data storage system (see Agrawal, 0054) data can be offloaded for storage in the distributed data storage system and from which requests to prove the existence of data on a storage device in the distributed data storage system can be issued (0062) cryptocurrency systems (0002).
9. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and further in view of Murck (US 20220083683) and Cousineau (US 10729030) and Bowman (US 20160379212)
Claim 15. Tarango in view of Thomas and Agrawal and Jakobsson and Murck and Cousineau does not disclose, but Bowman discloses
participating, by the solid state drive according to the configuration data, in cryptocurrency activities in a cryptocurrency network when the host system is in a low power mode, a sleep mode, or a hibernation mode (e.g., Bitcoin proof of work algorithm is estimated to consume on the order of $10 in electricity per transaction block validated. In contrast, a proof of wait technique in accordance with an embodiment consumes very little power during a wait period, calculated in accordance with an embodiment. Note that during this wait period, a processor and/or an entire verifier system may be placed into a low power state, to further reduce power consumption., 0011).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas and Agrawal and Jakobsson with Murck, and Cousineau with Bowman, providing the benefit of avoid performing expensive busy work while preserving the integrity of transaction validation (see Bowman, 0010) an energy efficient function is provided to enable validations to occur in a distributed ledger system (0007).
10. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and further in view of Murck (US 20220083683) and Cousineau (US 10729030) and Bowman (US 20160379212) and Yang (US 2023005323269)
Claim 16. Tarango in view of Thomas and Agrawal and Jakobsson and Murck and Cousineau and Bowman does not disclose, but Yang discloses
wherein the operations of the cryptocurrency activities include plot generation and plot farming (e.g., mining… generating plots of data… long term storage, 0050; a cryptocurrency minor can utilize their new SSD in a QLC mode to store a first number of plots, e.g., forty 100 GB plots in 4 TB of capacity. Those plots are continuously programmed and erased with the SSD operating in the QLC mode, 0052).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, and Thomas and Agrawal and Jakobsson with Murck, and Cousineau and Bowman with Yang, providing the benefit of to memory devices that are optimized for use in the mining of certain types of cryptocurrencies (see Yang, 0001, 0049).
11. Claims 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and further in view of and Yang (US 2023005323269) and Murck (US 20220083683)
Claim 18. Tarango in view of Thomas and Agrawal and Jakobsson does not disclose, but Yang discloses
wherein the operations of the cryptocurrency activities include plot generation and plot farming in a cryptocurrency network (e.g., mining… generating plots of data… long term storage, 0050; a cryptocurrency minor can utilize their new SSD in a QLC mode to store a first number of plots, e.g., forty 100 GB plots in 4 TB of capacity. Those plots are continuously programmed and erased with the SSD operating in the QLC mode, 0052).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas and Agrawal and Jakobsson with Yang, providing the benefit of to memory devices that are optimized for use in the mining of certain types of cryptocurrencies (see Yang, 0001, 0049).
Tarango in view of Thomas and Agrawal and Jakobsson and Thomas does not disclose, but Murck discloses
and the portion of the computations includes operations performed via Basic Linear Algebra Subprograms (BLAS). ) (e.g., GPU-accelerated basic linear algebra (BLAS) library, 0070).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, and Thomas and Agrawal and Jakobsson and Yang with Murck, providing the benefit of distributed self-governing computer system to correlate transactions on a blockchain computer system with transactions on a private computer system (see Murck, 0001) a distributed blockchain computer system which can correlate transactions on the distributed blockchain computer system with transactions in a private computer system (0015).
12. Claims 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and further in view of and Yang (US 2023005323269) and Murck (US 20220083683) and Cousineau (US 10729030)
Claim 19. Tarango et al does not disclose, but Cousineau discloses
wherein the computation accelerator includes a Multiply-Accumulate (MAC) Unit and a cryptographic engine Unit (e.g., include multiply-accumulate operations, col 14:54-55).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, et al with Cousineau, providing the benefit of especially suited to, or beneficial for, the performance of specific types of mathematical operations (see Cousineau, col 14:52-55) hardware accelerator 504 may include application-specific hardware circuitry 506 designed to perform a specific computing task (col 14:3-5) such that the performance of the application is more efficient (e.g., in terms of computing resources, electrical resources, etc.) than when executed otherwise (col 13:65- col 14:2).
13. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tarango (US 20200226080) and in view of Thomas (cited above) and Agrawal (cited above) and Jakobsson (US 11418402) and Yang (US 2023005323269) and Murck (cited above) and Cousineau (US 10729030) and further in view of Bowman (US 20160379212)
Claim 20. Tarango in view of Thomas and Agrawal and Jakobsson and Yang and Murck and Conusineau does not disclose, but Bowman discloses
discloses operable to participate in the cryptocurrency activities when the host system is in a low power mode, a sleep mode, or a hibernation mode (e.g., Bitcoin proof of work algorithm is estimated to consume on the order of $10 in electricity per transaction block validated. In contrast, a proof of wait technique in accordance with an embodiment consumes very little power during a wait period, calculated in accordance with an embodiment. Note that during this wait period, a processor and/or an entire verifier system may be placed into a low power state, to further reduce power consumption., 0011).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, and Thomas, and Agrawal and Jakobsson Yang with Murck, and Conusineau with Bowman, providing the benefit of avoid performing expensive busy work while preserving the integrity of transaction validation (see Bowman, 0010) an energy efficient function is provided to enable validations to occur in a distributed ledger system (0007).
Response to Arguments
Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive.
For USC 103 rejection, for Claim 1, Applicant argues that the cited references do not disclose the amended limitations. The Office disagrees. The present OA renders these limitations as obvious under the current rejections.
Tarango in view of Thomas and Agrawal does not disclose, but Jakobsson discloses
wherein the proof of space response proves that the solid state drive has a predetermined amount of data storage space (eg., col 20:51-55 FIG. 8 - of a process for initializing a graph for providing proof of space. process 800 is executed by graph generating device 702 of FIG. 7. The process begins at 802, when an initial graph is generated at a device; col 21:10-20 - At 804, at least a portion of the initial graph is stored on the device.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the SSD with an accelerator on a semiconductor chip ad disclosed by Tarango, with Thomas, with Agrawal with Jakobsson, providing the benefit of an improved Proof of Space … spare computation resources (e.g., on their mobile phones, tablets, electrical outlets, etc.), they can be utilized (see Jakobsson, col 4:31-55).
Applicant’s arguments for Claims 10 and 17 are similar to Claim 1, addressed above.
Applicant’s arguments for Claims 2-9, 11-16, 18-20 are based on dependency from Claims 1, 10 and 17, addressed above.
Conclusion
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135