DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-17, and 22-24 are pending. Claim 2 is cancelled.
Response to Arguments
Regarding 35 U.S.C. 101:
Applicant’s amendments and arguments regarding the rejection of claims 1-9, 12-17, and 22-24 under 35 U.S.C. 101 have been fully considered and are found to be persuasive as examiner finds the claims supported by the specification reflect an improvement to the technology of resource allocation through per-tenant capability advertising of accelerator operations. The rejections of claims under 35 U.S.C. 101 are withdrawn.
Regarding: Prior Art Rejections:
Applicant’s amendments and arguments regarding the rejection of claims 1-17, and 22-24 under 35 U.S.C. 103 have been fully considered and are moot due to new grounds of rejection. Applicant’s cancellation of claim 2 render the prior rejection of claim 2 moot.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 3-17, and 22-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 as amended recites the limitation: “wherein the hardware accelerator device is to advertise the one or more available operations and/or capabilities of the one or more work queues, independent of capabilities of the hardware accelerator device, to the one or more tenants on a per-tenant basis”. It is unclear what is meant to be independent of capabilities of the hardware accelerator device as capabilities of the hardware accelerator device. The claim may be interpreted with advertising being performed independent of the capabilities as a separate function or that the advertised capabilities themselves may be independent from the hardware accelerator device since “capabilities of the hardware accelerator device” is not equated to the previously claimed “one or more available operations and/or capabilities of the one or more work queues”. Amendments clarifying the independence and capability relationship is requested.
Claims 3-17 and 22-24 inherit the deficiencies of claim 1 and are rejected for the same reasons as claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-11, 16-17, and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kelkar et al. US 20230153159 A1, hereinafter “Kelkar”, in view of Bass et al. US 20130152099 A1, hereinafter “Bass” in view of Jana et al. US 20170236128 A1, hereinafter “Jana”.
Kelkar is cited in a previous rejection. Bass was cited in IDS filed on 05/01/2023.
Regarding claim 1, Kelkar teaches the invention substantially as claimed including:
An apparatus comprising:
a hardware accelerator device to advertise one or more available operations and/or capabilities for each of one or more work queues of the hardware accelerator device to one or more tenants (Abstract; A local hardware (HW) accelerator card may provide, via a communication interface, a listing of acceleration services from the local HW accelerator card. The listing of acceleration services may include a first set of acceleration services provided by one or more accelerators of the local HW accelerator card and a second set of acceleration services provided by one or more accelerators of a remote HW accelerator card. [0028] a HW accelerator card attached to a computer device may be able to serve and expose acceleration services from locally and remotely connected HW accelerator cards to the computing device; [0029] processors which retrieve the listings from the HW accelerator cards will be able to determine and leverage more accelerator services offered by the accelerators on the HW accelerator cards; [0030]; [0031]; Fig. 3; [0046]; [0057] the acceleration service listing of each computing devices may be generated by ASM software running on one or more HW accelerator cards; [0059]; [0072] the software executing on processor 812 may be provided with a listing of acceleration services available locally (i.e., by the accelerators of HW accelerator card 818) or remotely (i.e., by other remote accelerators of HW accelerators connected via a network,) from HW accelerator card 818. In another example, the software or another program, such as an operating system, executing on the computing device may request the listing. i.e., tenant(s)), wherein the hardware accelerator device is to advertise the one or more available operations and/or capabilities of the one or more work queues, independent of capabilities of the hardware accelerator device ([0028] a HW accelerator card attached to a computer device may be able to serve and expose acceleration services from … remotely connected HW accelerator cards to the computing device; Examiner notes: services from remote accelerator cards are independent from the local hardware accelerator card); and
logic circuitry, coupled to the hardware accelerator device (Fig 2 Compute complex 212 coupled within Hardware Accelerator Card 118; [0041] a hardware accelerator card may be one or more special-purpose processors, such as application-specific integrated circuits (ASICs)), to control access to the one or more available operations and/or capabilities of the one or more work queues on a per-tenant basis ([0040] Referring to FIG. 2., the HW accelerator card 118 may include a compute complex 212, memory 214, and accelerators 228a, 228b, and 228c. The compute complex may include one or more compute units 213. The compute complex may control the general operation of the other components of the hardware accelerator, such as by distributing processing tasks amongst the accelerators 228a-228c and communicating with other devices in computing device 110, such as processor 112. In some instances, the compute complex may coordinate, or otherwise assist with, service aggregation, as described herein.; [0042]; [0044] the Accelerated Services Manager (ASM) 219 may be executed by the one or more compute units 213 of the compute complex to control, or otherwise assist with, service aggregation of HW accelerator card 118. [0059]; [0004] systems may be limited in their ability to access acceleration services offered by hardware accelerator cards due to the limited number of hardware accelerator cards that may be connected to the systems).
While Kelkar teaches acceleration service listings with “acceleration services” referring to the capabilities and functionalities offered by accelerators for workloads and data processing (See at least [0030], [0045-0048], and [0059]), Kelkar does not explicitly teach for each of one or more work queues of the hardware accelerator device.
However, Bass teaches for each of one or more work queues of the hardware accelerator device (Fig 1 Queues 104-106; [0010] Efficient utilization of a finite number of hardware accelerators requires a queue management system to prioritize processing jobs and ensure fairness in allocating available processing acceleration resources amongst the LPARs; [0012] For each type of hardware acceleration engine there is assigned a dedicated queue).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Kelkar with Bass because Bass’s teachings of utilizing hardware accelerator queues for managing hardware accelerator task offloading usage would have provided Kelkar’s system with the advantage and capability to maintain a queue for each service listing to better organize workloads requesting performance of some of the tenant’s operations using shared resources (see Bass, [0003] Hardware accelerators may perform certain tasks more efficiently then processors running a software routine. One aspect of hardware acceleration is that algorithmic operations are performed on data using specially designed hardware rather than generic hardware, as is the case with software running on a microprocessor).
Kelkar and Bass do not explicitly teach wherein the hardware accelerator device is to advertise the one or more available operations and/or capabilities of the one or more work queues, independent of capabilities of the hardware accelerator device to the one or more tenants on a per-tenant basis.
However, Jana teaches wherein the hardware accelerator device is to advertise the one or more available operations and/or capabilities to the one or more tenants on a per-tenant basis ([0012] The services composition system achieves several important goals. It is a predictive personalized service in that it anticipates a user's needs and proactively takes intelligent actions and recommends valuable and timely personalized information. The system is additionally an adaptive system that learns from past actions of all users and adjusts its behavior to provide superior service quality; [0013] Based on an expert system learning algorithm trained using prior customer service creation requests, one or more of the virtualized network function resources are suggested to the customer for use in composing the new network service).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Jana’s user specific service composition system with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of catering specific sets of system services/capabilities to meet different customer requirements and use cases (see Jana [0010] The presently described system enables cloud providers to establish a services ecosystem for facilitating mass marketing of existing and new network services. The system lowers barriers to entry for enterprise customers and small business customers to create new services; [0023] The disclosed services composition system utilizes an ecosystem populated with an array of NFV models that facilitate interlinking or combining to provide a richer set of value added services. Combining products and services in unique ways that have not been thought of provides opportunities that can be monetized and meet customer needs more holistically).
Regarding claim 3, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar further teaches wherein a device driver is to configure the hardware accelerator device to advertise different operations and/or capabilities of the one or more work queues on a per-tenant basis (Fig 2 compute unit 213; [0001] processors may be hardcoded with software, such as drivers, to communicate with particular hardware accelerator cards; [0041] The one or more compute units of the compute complex 212 may comprise one or more general-purpose processors and/or special-purpose processors; [0044] the ASM 219 may be executed by the one or more compute units 213 of the compute complex to control, or otherwise assist with, service aggregation of HW accelerator card 118).
Regarding claim 4, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar further teaches wherein the one or more tenants comprise one or more of: one or more virtual machines (VMs), one or more containers, or one or more applications ([0071] Software running on a processor 812 of a computing device may request an acceleration service or services from a HW acceleration card 818 to process a workload).
Regarding claim 5, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar further teaches wherein the hardware accelerator device is to advertise a first portion of the one or more available operations and/or capabilities of the one or more work queues to a first tenant or a first class of tenant of the one or more tenants (Fig 5 Computing Device 410 is advertised remote Service Listings 510 Encoding, Hashing, and Encryption (remote)), wherein the hardware accelerator device is to advertise a second portion of the one or more available operations and/or capabilities of the one or more work queues to a second tenant or a second class of tenants of the one or more tenants, wherein the first portion and the second portion are different portions (Fig 5 Computing Device 420 is advertised remote Service Listings 520 Encoding, Hashing, and Encryption (remote)).
In addition, Bass teaches one or more work queues of the hardware accelerator device (Fig 1 Queues 104-106; [0010] Efficient utilization of a finite number of hardware accelerators requires a queue management system to prioritize processing jobs and ensure fairness in allocating available processing acceleration resources amongst the LPARs; [0012] For each type of hardware acceleration engine there is assigned a dedicated queue).
Regarding claim 6, Kelkar, Bass, and Jana teach the apparatus of claim 5.
Bass further teaches a first work queue from the one or more work queues to support the first portion of the one or more available operations and/or capabilities and a second work queue from the one or more work queues to support the second portion of the one or more available operations and/or capabilities ([0012] For each type of hardware acceleration engine there is assigned a dedicated queue; [0026] A person of skill in the art will appreciate that many types of hardware accelerator engines could be employed using embodiments of the present invention and are not limited to the type shown in FIG. 7. FIG. 1 shows one queue (Q1, Q2 . . . Qn) for each type of hardware acceleration engine 107, 108 and 109; Examiner notes: each different type of hardware acceleration engine represents a different type of available operation/capability).
Regarding claim 7, Kelkar, Bass, and Jana teach the apparatus of claim 6.
Kelkar further teaches wherein the first work queue and the second work queue comprise an overlapping set of operations and/or capabilities (Fig 3 Service Listings 328a and 328b both contain Function 1 and Function 5; Examiner notes: work queues dedicated to utilize services from listings a and b will have overlap of functions 1 and 5).
Regarding claim 8, Kelkar, Bass, and Jana teach the apparatus of claim 6.
Bass further teaches wherein the first work queue and the second work queue comprise an overlapping set of tenants or class of tenants (Fig 7 LPARs CPUn 710-712 share queuing system PB Interface 703; [0010] a queue management system to prioritize processing jobs and ensure fairness in allocating available processing acceleration resources amongst the LPARs; wherein the LPARs are software applications and correspond to the tenants).
Regarding claim 10, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar further teaches one or more execution engines to execute the one or more available operations and/or execute one or more operations to support the capabilities of the one or more work queues ([0042] The accelerators 228a-228c may each be comprised of one or more processors capable of providing particular acceleration services).
Regarding claim 11, Kelkar, Bass, and Jana teach the apparatus of claim 10.
Kelkar further teaches wherein the hardware accelerator device comprises the one or more execution engines ([0040] HW accelerator card 118 may include a compute complex 212, memory 214, and accelerators 228a, 228b, and 228c; [0042] The accelerators 228a-228c may each be comprised of one or more processors capable of providing particular acceleration services; Examiner notes: HW accelerator card includes accelerators 228a-c. Therefore, the HW accelerator card (hardware accelerator device) also includes the processors located in accelerators 228a-c (one or more execution engines)).
Regarding claim 16, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Bass further teaches a processor, having one or more processor cores, comprises the hardware accelerator device and/or the logic circuitry ([0004] Hardware accelerators may be attached directly to the processor complex).
Regarding claim 17, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar further teaches wherein the logic circuitry controls access to the one or more available operations and/or capabilities on a per-tenant basis by one or more of: configuration or enforcement ([0040] The compute complex may control the general operation of the other components of the hardware accelerator, such as by distributing processing tasks amongst the accelerators 228a-228c (i.e., configuration of task allocations) and communicating with other devices in computing device 110, such as processor 112. In some instances, the compute complex may coordinate, or otherwise assist with, service aggregation, as described herein (i.e., advertising services)).
Regarding claim 18, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar further teaches wherein the hardware accelerator device comprises the logic circuitry (Fig 2 Compute Complex 212 within Hardware Accelerator Card 118).
Regarding claim 19, it is the one or more non-transitory computer-readable media of claim 1. Therefore, it is rejected for the same reasons as claim 1.
Kelkar further teaches one or more non-transitory computer-readable media comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations ([0043] on-transitory computer readable medium capable of storing information accessible by the processor 120, such as a hard-drive, solid state drive, tape drive, optical storage, memory card, ROM, RAM, DVD, CD-ROM, write-capable, and read-only memories).
Regarding claims 20 and 21, they are the non-transitory computer-readable media of claims 2 and 3. Therefore, they are rejected for the same reasons as claims 2 and 3 respectively.
Regarding claim 22, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Bass further teaches wherein the one or more work queues are to utilize a single, unique process address space identifier (PASID) per-tenant ([0032] Job Requestor 101 may at any time request that one or more jobs associated with a particular identifier be removed from any and all of the queues, in any and all queue positions).
Regarding claim 23, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Bass further teaches wherein a work queue of the one or more work queues is a job submission mechanism for the hardware accelerator device (Fig 1 Q1, Q2, Q3 feeds jobs into hw acc eng type 1, 2, n).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kelkar et al. US 20230153159 A1 in view of Bass et al. US 20130152099 A1 in view of Jana et al. US 20170236128 A1, hereinafter “Jana” in further view of Wood et al. US 20220276893 A1, hereinafter “Wood”.
Regarding claim 9, Kelkar, Bass, and Jana teach the apparatus of claim 6.
Bass further teaches wherein the first work queue or the second work queue comprise one or more of: a dedicated work queue or a shared work queue (Fig 7 LPARs CPUn 710-712 share queuing system PB Interface 703).
Kelkar, Bass, and Jana do not explicitly teach wherein the first work queue or the second work queue comprise one or more of: a dedicated work queue.
However, Wood further teaches wherein the first work queue or the second work queue comprise one or more of: a dedicated work queue ([0063] each tenant is assigned a tenant-specific work item queue 504, e.g. tenant 202A corresponds to tenant-specific work item queue 504A, tenant 202B corresponds to tenant-specific work item queue 504B. etc).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Kelkar, Bass, and Jana with Wood because Wood’s teaching of dedicating a work queue to each tenant would have provided the existing system with the advantage and capability to more efficiently manage task scheduling in resource-sharing multi-tenant systems preventing resource starvation (see Wood, [0004] some tenants may request thousands if not millions of operations in a short period of time Queuing these operations to be processed sequentially may stall the remaining tenants tor minutes or even hours at a time. This unfairness leads to a poor customer experience, and depending on whether a service level agreement is in place, may have financial consequences; [0010] operations are first added as work items to a tenant-specific work item queue (hereafter ‘tenant queue’). Operations that have been added to a tenant queue are considered to be scheduled, in that the operation is scheduled to be executed at a later time. Operations wait in the tenant queue until they are moved, one batch at a time, to the execution queue for processing).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kelkar et al. US 20230153159 A1 in view of Bass et al. US 20130152099 A1 in view of Jana et al. US 20170236128 A1, hereinafter “Jana” in further view of Baxter et al. US 20200387404 A1, hereinafter “Baxter”.
Regarding claim 12. Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar, Bass, and Jana do not explicitly teach wherein the logic circuitry is to control access to the one or more available operations and/or capabilities on a per-tenant class basis.
However, Baxter teaches wherein the logic circuitry is to control access to the one or more available operations and/or capabilities on a per-tenant class basis ([0012] When a request for a cluster is generated by a tenant, management system 160 may identify the tenant associated with the request and determine one or more of computing systems 120-128 that are available to that tenant; [0013] management system 160 may maintain information about tiers of tenants, where child tenants (or subtenants) may exist within each tenant (as tenant class) of a computing environment 100. For example, a tenant may comprise a corporation, and a subtenant or child tenant may comprise a division in the corporation (such as a legal or advertising department). The resources allocated to parent tenant may be based on a quality of service selected by the parent tenant, based on the different data processing operations or software applications required by the parent tenant, based on pricing tiers determined by the parent tenant, or based on other similar factors).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Kelkar, Bass, and Jana with Baxter because Baxter’s teaching of giving serving different resources, operations, and software to tenants based on their individual agreements and situational needs would have provided the existing system with the advantage and capability to verify if a tenant is able to utilize a capability within the system’s hardware accelerators, ultimately allowing for better resource utilization (see Baxter, [0003] a management system may identify a request to deploy a cluster in the computing environment, wherein the computing environment comprises multiple computing systems. The management system may further identify a tenant associated with the request and identify one or more of the computing systems available to the tenant. The method further includes selecting at least one computing system of the one or more systems to support the request and deploying one or more virtual nodes as part of the cluster in the at least one computing system).
Regarding claim 13, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Baxter further teaches wherein each of the one or more tenants are to pay a different price for sharing different subsets of the one or more available operations and/or capabilities of the hardware accelerator device ([0013] The resources allocated to parent tenant may be based on a quality of service selected by the parent tenant, based on the different data processing operations or software applications required by the parent tenant, based on pricing tiers determined by the parent tenant, or based on other similar factors; Examiner notes: different tenants have different requirements for resources leading to different costs).
Regarding claim 14, Kelkar, Bass, and Jana teach the apparatus of claim 1,
Baxter further teaches wherein the one or more tenants are capable of migration between hardware accelerator devices of different generations ([0018] if additional clusters are requested from tenants associated with a better quality of service, the original cluster may be migrated to another set of one or more computing systems to provide the other tenant with the required quality of service).
Regarding claim 15, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Baxter further teaches wherein the logic circuitry is to control access to the one or more available operations and/or capabilities to support varying levels of system resource availability and/or quality of service for each of the one or more tenants ([0018] management system 160 may further consider a quality of service associated with the tenant. As an example, each of the tenants may be associated with a minimum quality of service or minimum amount of physical resources but may be allocated additional resources or enhanced processing resources when the resources are available in computing environment 100).
Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kelkar et al. US 20230153159 A1 in view of Bass et al. US 20130152099 A1 in view of Jana et al. US 20170236128 A1, hereinafter “Jana” in further view of Gewirtz et al. US 8051227 B1.
Regarding claim 24, Kelkar, Bass, and Jana teach the apparatus of claim 1.
Kelkar, Bass, and Jana do not explicitly teach wherein a work queue of the one or more work queues has a memory mapped input/output address mapped to a tenant of the one or more tenants, wherein the memory mapped input/output address is not mapped to other tenants.
However, Gewirtz teaches wherein a work queue of the one or more work queues has a memory mapped input/output address mapped to a tenant of the one or more tenants, wherein the memory mapped input/output address is not mapped to other tenants (Fig 1 Memory Mapped Registers; Fig 3; FIG. 3, at block 301, a command (e.g., a memory access command, such as a read command or a write command) is received from an agent via a predetermined memory mapped register (e.g., data access register). The agent may be one of the software processes, each being executed by one of multiple processor cores of a network processor of a network element. At block 302, a queue is identified based on the predetermined memory mapped register, where the queue has been allocated in a memory, Col 7 27-35; Examiner notes: the predetermined memory mapped register represents queue interactions for a specific agent).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Gewirtz’ programming of queues with the system of Kelkar, Bass, and Jana. A person of ordinary skill in the art would have been motivated to make this combination to provide the existing system with the advantage of selectively providing software agents access to specific queues (see Gewirtz Col 1 60-64, As a result, the pointer is obtained and updated atomically through hardware so that the software process represented by the first agent is not required to obtain an exclusive access control of the first queue from the Operating System).
Conclusion
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/H.L./
Examiner, Art Unit 2195
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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