Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pg. 6-11, filed 05/27/2025, with respect to the 101 rejection of claims 1-20 have been fully considered and are persuasive. The 101 rejection of claims 1-20 has been withdrawn.
Applicant's arguments filed 05/27/2025, with respect to the 103 rejection of claims 1-20, have been fully considered but they are not persuasive.
Regarding Applicant’s arguments on pg. 13-14: “Ning does not relate to sparing, as would be recognized by a person having ordinary skill in the art at the time of the invention.” The present application defines sparing in the specification in para. 4 as follows: “Sparing operations copy the contents of memory to another location or another format,” before going on to list non-limiting examples. The BRI of the claims in light of the specification requires sparing circuitry to be circuitry that performs sparing operations, as defined in the para. 4 of the present application’s specification. Ning clearly does teach sparing circuitry as shown in fig. 2, operation S24->Y: “store the address information pointed to by the read command into a memory bit of a preset memory space.”
Regarding Applicant’s arguments on pg. 16-17, Applicant alleges that the memory device disclosed by Ning is not a memory controller. The BRI of a memory controller in light of the present applications specification is a device that controls memory. Of which Ning clearly does teach in para. 98: “The execution unit 43 controls the address information stored in preset memory space 42.”
Regarding Applicant’s arguments on pg. 17, Applicant alleges that “execution unit 43 does not include sparing circuitry [execution unit 43, fig. 4] to store a last sparing address as a memory address for a memory [spare memory cell 44, fig 4].” Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. As shown above and in the non-final office action, the execution unit 43 is sparing circuitry and does store a last sparing address as a memory address for a memory (fig. 2, operation S24->Y).
Regarding Applicant’s arguments on pg. 17, Applicant alleges that “Ning does not disclose use of different Error Correction Code formats and therefore cannot teach ‘determine an Error Correction Code format for the processor memory address.’” However, Ning does disclose this limitation (see fig. 2). Based on a comparison of the address pointed to by the read command and the stored address (S21), error correction either is performed (error correction code format 1) or is not performed (error correction code format 2). If the addresses are identical (S21->Y->S23), a read operation is performed and no error correction is performed. Otherwise, the process continues until step S24: determine whether an error occurs. As shown in claim 5, lines 8-11 of Ning, “Determining whether an error occurs in the data to be read out comprises: decoding the first ECC.” Applicant lists a number of nonlimiting ECC formats as examples, but the Examiner maintains that the BRI of an Error Correction Code format, in light of the specification, merely using an error correction code in some way.
Regarding Applicant’s arguments on pg. 21, Applicant alleges that “the logical addresses of data are not processor memory addresses and they are received from the host and not any circuitry in the memory controller (and specifically the sparing circuitry that is absent from both Higgins and Ning).” It is well known to those of ordinary skill in the art that a logical address generally refers to an address generated by the CPU when a program is running, and is therefore a processor memory address. There is no definition in the specification to support Applicant’s argument that a logical address is not a processor memory address. In response to applicant's argument that Higgins does not disclose receiving the processor memory address from the sparing circuitry, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, using Higgins’ address conversion system allows for benefits such as conserving storage capacity (Higgins, para. 3, lines 2-3).
Claims 8 and 14 correspond to claim 1, and their rejections will be maintained for reasons similar to those presented above. Applicant claims that each of claims 2-7, 9-13, and 15-20 is patentable over Ning in view of Higgins based on the patentability of independent claims 1, 8, and 14. However, as shown above, the rejection of claims 1, 8, and 14 will be maintained, rendering this argument moot.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 8, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ning (US Publication No. 2021/0313002 A1) in view of Higgins (US Publication No. 2018/0373590 A1).
Regarding claim 1, Ning discloses a memory controller comprising: a sparing circuitry [execution unit 43, fig. 4] to store a last sparing address as a memory address for a memory [spare memory cell 44, fig. 4].
to compare the processor memory address with the last sparing address to determine an Error Correction Code format for the processor memory address; [Determine whether the address information pointed to by the read command (processor memory address) is identical to the address information stored in the preset memory space (last sparing address). Depending on the result of this comparison, error detection may or may not be performed (steps S21, S23, S32; fig. 2). Determining whether an error occurs in the data to be read out comprises: decoding the first ECC (claim 5, lines 8-11).]
However, Ning does not explicitly disclose converting a system address for a processor memory transaction to a processor memory address or reverse address decode circuitry to receive the processor memory address from the sparing circuitry and to convert the processor memory address to a second system address for error logging.
In the analogous art of error correction, Higgins teaches converting a system address for a processor memory transaction to a processor memory address or reverse address decode circuitry to receive the processor memory address from the sparing circuitry and to convert the processor memory address to a second system address for error logging. [The memory controller 118 may convert between logical addresses of data (processor memory address) used by the host 100 and physical addresses of the memory 116 (system address) during data programming and reading (para. 25, lines 1-4).]
It would be obvious to one of ordinary skill in the art, having the teachings of Ning and Higgins before them before the effective filing date of the claimed invention, to integrate the address conversion taught by Higgins into the memory controller disclosed by Ning, to allow for benefits such as conserving storage capacity (Higgins, para. 3, lines 2-3).
Claims 8 and 14 correspond to claim 1, and are rejected accordingly.
Claims 2-7, 9-13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ning in view of Higgins and Das (US Publication No. 2016/0232063 A1).
Regarding claim 2, the combination of Ning and Higgins teaches the memory controller of claim 1. However, the combination of Ning and Higgins does not explicitly teach wherein the Error Correction Code format is Adaptive Double Device Data Correction (ADDDC) or Single Device Data Correction (SDDC).
In the analogous art of error correction, Das teaches wherein the Error Correction Code format is Adaptive Double Device Data Correction (ADDDC) [System 102 can implement ADDDC (adaptive double device data correction) to manage hard errors or hard failures (para. 48, lines 1-3)]
or Single Device Data Correction (SDDC) [Techniques are known for SDDC (single device data correction) to address hard failure. (para. 5, lines 7-9)].
It would be obvious to one of ordinary skill in the art, having the teachings of Ning, Higgins, and Das before them before the effective filing date of the claimed invention, to incorporate the error correction formats taught by Das into the memory controller disclosed by the combination of Ning and Higgins, to allow for benefits such as improving service rates by a factor of 10x for large configurations (Das, para. 54, lines 9-10).
Regarding claim 3, the combination of Ning and Higgins teaches the memory controller of claim 1. Ning further discloses wherein the sparing circuitry uses memory addresses in increasing order [address information pointed to by the read command is sequentially stored into the plurality of memory bits of the preset memory space 10 (para. 47, lines 1-4)]
However, the combination of Ning and Higgins does not explicitly teach wherein the Error Correction Code format is Adaptive Double Device Data Correction (ADDDC).
In the analogous art of error correction, Das teaches wherein the Error Correction Code format is Adaptive Double Device Data Correction (ADDDC) [System 102 can implement ADDDC (adaptive double device data correction) to manage hard errors or hard failures (para. 48, lines 1-3)].
It would be obvious to one of ordinary skill in the art, having the teachings of Ning, Higgins, and Das before them before the effective filing date of the claimed invention, to incorporate the error correction format taught by Das into the memory controller disclosed by the combination of Ning and Higgins, to allow for benefits such as improving service rates by a factor of 10x for large configurations (Das, para. 54, lines 9-10).
Regarding claim 4, the combination of Ning, Higgins, and Das teaches the memory controller of claim 3. However, the combination of Ning and Higgins does not explicitly teach wherein sparing circuitry performs rank based ADDDC sparing.
Das teaches wherein sparing circuitry performs rank based ADDDC sparing. [ADDDC can further improve service rates by a significant margin by providing the ability to survive the additional hard failure in a lockstep pair. The lockstep partners refer to the pair of ranks 128 that are working in lockstep (para. 51, lines 7-11)].
It would be obvious to one of ordinary skill in the art, having the teachings of Ning, Higgins, and Das before them before the effective filing date of the claimed invention, to incorporate the error correction format taught by Das into the memory controller disclosed by the combination of Ning and Higgins, to allow for benefits such as improving service rates by a factor of 10x for large configurations (Das, para. 54, lines 9-10).
Regarding claim 5, the combination of Ning, Higgins, and Das teaches the memory controller of claim 3. However, the combination of Ning and Higgins does not explicitly teach wherein sparing circuitry performs bank based ADDDC sparing.
Das teaches wherein sparing circuitry performs bank based ADDDC sparing. [ADDDC can further improve service rates by a significant margin by providing the ability to survive the additional hard failure in a lockstep pair. The lockstep partners refer to the pair of banks 124 that are working in lockstep (para. 51, lines 7-11)].
It would be obvious to one of ordinary skill in the art, having the teachings of Ning, Higgins, and Das before them before the effective filing date of the claimed invention, to incorporate the error correction format taught by Das into the memory controller disclosed by the combination of Ning and Higgins, to allow for benefits such as improving service rates by a factor of 10x for large configurations (Das, para. 54, lines 9-10).
Regarding claim 6, the combination of Ning, Higgins, and Das teaches the memory controller of claim 5. Ning further discloses wherein the memory is a Dynamic Random Access Memory [The preset memory space 42 may be a structure having memory function known to those skilled in the art, such as a dynamic random access memory (DRAM) (para. 92, lines 8-12)].
Regarding claim 7, the combination of Ning, Higgins, and Das teaches the memory controller of claim 6. However, the combination of Ning and Higgins does not explicitly teach wherein the memory address includes a row address, a column address and a bank address.
Das teaches wherein the memory address includes a row address, a column address and a bank address. [It will be understood that memory 120 can have an architecture with addressable regions of column, row, and bank (para. 60, lines 1-4)].
It would be obvious to one of ordinary skill in the art, having the teachings of Ning, Higgins, and Das before them before the effective filing date of the claimed invention, to incorporate the error correction format and corresponding memory architecture taught by Das into the memory controller disclosed by the combination of Ning and Higgins, to allow for benefits such as improving service rates by a factor of 10x for large configurations (Das, para. 54, lines 9-10).
Claims 9-13 correspond to claims 2-6 (respectively) and are rejected accordingly.
Claims 15-19 correspond to claims 2-6 (respectively) and are rejected accordingly.
Regarding claim 20, the combination of the combination of Ning and Higgins teaches the system of claim 14. However, the combination of Ning and Higgins does not explicitly teach further comprising one or more of: a display communicatively coupled to the processor; or a battery coupled to the processor.
In the analogous art of error correction, Das teaches a display communicatively coupled to the processor; or a battery coupled to the processor. [display interface 1232 communicatively coupled to the processor 1210 (fig. 12)]
It would be obvious to one of ordinary skill in the art, having the teachings of Ning, Higgins, and Das before them before the effective filing date of the claimed invention, to incorporate the display taught by Das into the system disclosed by the combination of Ning and Higgins, to allow for benefits such as providing a visual display for a user to interact with the computing device (Das, para. 117, lines 3-4).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/14/2025