CTNF 17/552,239 CTNF 91398 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/02/2025 has been entered. Response to Amendment The office action is responding to the arguments filed on 06/29/2026. Claims 1-5, 8-22 and 24-26 are pending. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-5, 10, 12-13, 15, 17-19, 21-22 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20180143903 A1) in view of Gupta et al. (US 20190102311 A1) hereinafter Wu and Gupta . Regarding claim 1, Wu teaches An apparatus comprising: an interface circuitry, coupled to the interface, (See Fig 1, paragraph [0025], illustrates interface 140 is coupled with memory controller) wherein the discontinue access to the memory address region comprises a data flush or scrub of data of the memory address region from the one or more cache devices to a memory device. ( See Fig 1, paragraph [0023], illustrates a request from an application for the processor 112 which specifies address range for cache flushing to CM engine 148) Wu teaches cache coherence and snooping. However, Wu does not explicitly teach to receive an indication that when the one or more processors are to discontinue access to a memory address region associated with one or more cache devices and based on the indication that the one or more processors are to discontinue access to the memory address region, the circuitry is to cease transmission of snoop requests associated with the memory address region On the other hand, Gupta which also relates to cache coherence and snooping teaches to receive an indication that when the one or more processors are to discontinue access to a memory address region associated with one or more cache devices and (See Fig 4, paragraph [0108], illustrates host processor 445 or accelerator 410 uses bias table lookup as an indication to access memory regions where bias state bit may be used to allow access to memory regions. In other words, bias state bit indicates if it’s allowed to access or not allowed to access to memory regions ) based on the indication that the one or more processors are to discontinue access to the memory address region, the circuitry is to cease transmission of snoop requests associated with the memory address region , (See Fig 5A and 5B, paragraph [0104], illustrates based on indication in snoop-invalidate message coherence controller 530 may return data to a requesting processor core, followed immediately by a snoop-invalidate message . In other words, coherence controller sends message to invalidate or cease snoop requests associated with memory region ) Both Wu and Gupta relate to cache coherence and snooping. Wu teaches cache coherence with flushing commands in an address region. On the other hand, Gupta also teaches cache coherence and snooping and bias state bit indicates if it’s allowed to access or not allowed to access to memory regions and coherence controller sends message to invalidate or cease snoop requests associated with memory region . Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu with Gupta to specify cache coherence and snooping and bias state bit indicates if it’s allowed to access or not allowed to access to memory regions and coherence controller sends message to invalidate or cease snoop requests associated with memory region providing methods which may be used to enable bias-based coherency for device attached memory as mentioned in paragraph [0052]. Regarding claim 2, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, comprising a second circuitry, wherein the second circuitry is to issue one or more snoop requests associated with access to the memory address region until data associated with the memory address region is flushed or scrubbed from the one or more cache devices to the memory device On the other hand, Wu which also relates to cache coherence and flushing teaches The apparatus of claim 1, until data associated with the memory address region is flushed or scrubbed from the one or more cache devices to the memory device. (“If the physical address PA matches a stored physical address in the snoop filter 380, at step 440 a cache flush command specifying the physical address PA is issued to the one or more corresponding clusters identified by the snoop filter 380. The loop index PA increments at step 450 by an offset (which is the size of a cache line) to the next physical address. The method 400 repeats the steps 440 and 450 until the end of the physical address range is reached at step 460. In one embodiment, the CM engine 148 may notify the processor or the application which initiated the cache flushing request to indicate that the generation of cache flushing commands is completed at step 470”) (paragraph [0033] line 1-6) (i.e. Fig 4 at step 440-460 illustrate 440 a cache flush command specifying the physical address PA is issued to the one or more corresponding clusters identified by the snoop filter 380 and CM engine 148 (Fig 3) repeats the steps 440 and 450 until the end of the physical address range is reached at step 460. In other words, CM engine continues flushing command on the address region in loop until it’s completed) comprising a second circuitry, wherein the second circuitry is to issue one or more snoop requests associated with access to the memory address region (“FIG. 1 also shows that each processor 112 may have access to multiple levels of caches”) (paragraph [0022] line 1) (“applications that run on the processors 112 typically use virtual addresses to reference data locations. In one embodiment, a request from an application that specifies a virtual address range for cache flushing is first translated to a physical address range”) (paragraph [0023] line 2-4) (i.e. each processor 112 may have access to multiple levels of caches and application running on the processors 112 typically use virtual addresses to reference data locations which is translated to physical address for cache flushing. In other words, processor may issue virtual addresses for cache flushing) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 1 is equally applicable to claim 2. Regarding claim 3, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, comprising a first processor of the one or more processors wherein the first processor comprises one or more of a core, accelerator, graphics processing unit (GPU), central processing unit (CPU), microprocessor, NDP, infrastructure processor unit (IPU), data processing unit (DPU), or Compute Express Link (CXL) controller. On the other hand, Wu which also relates to cache coherence and flushing teaches The apparatus of claim 1, comprising a first processor of the one or more processors wherein the first processor comprises one or more of a core, accelerator, graphics processing unit (GPU), central processing unit (CPU), microprocessor, NDP, infrastructure processor unit (IPU), data processing unit (DPU), or Compute Express Link (CXL) controller. (“the “multi-processor computing system” as described herein is a “multi-core processor system.” In one embodiment, each processor may contain one or more cores. In an alternative embodiment, each processor may be equivalent to a core. The processors described herein may contain a combination of central processing units (CPUs), a graphics processing units (GPUs), digital signal processors (DSPs), multimedia processors, and any processors that have access to the system memory”) (paragraph [0017] line 1-5) (i.e. Fig 1 illustrates a multi-processor computing system 100 where each processor may contain one or more cores and the processors described herein may contain a combination of central processing units (CPUs), a graphics processing units (GPUs), digital signal processors (DSPs), multimedia processors, and any processors that have access to the system memory) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 1 is equally applicable to claim 3. Regarding claim 4, Wu in view of Gupta teaches cache coherence and snooping in claim 3. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 3, wherein the first processor is to access and process data associated with the memory address region. On the other hand, Wu which also relates to cache coherence and flushing teaches The apparatus of claim 3, wherein the first processor is to access and process data associated with the memory address region. (“FIG. 1 also shows that each processor 112 may have access to multiple levels of caches”) (paragraph [0022] line 1) (“applications that run on the processors 112 typically use virtual addresses to reference data locations. In one embodiment, a request from an application that specifies a virtual address range for cache flushing is first translated to a physical address range”) (paragraph [0023] line 2-4) (i.e. each processor 112 may have access to multiple levels of caches and application running on the processors 112 typically use virtual addresses to reference data locations which is translated to physical address for cache flushing) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 1 is equally applicable to claim 4. Regarding claim 5, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, wherein the second circuitry to indicate snoop requests are to be sent to the one or more cache devices based on at least one of the one or more processors accessing data managed by the one or more cache devices. On the other hand, Wu which also relates to cache coherence and flushing teaches The apparatus of claim 1, wherein the second circuitry to indicate snoop requests are to be sent to the one or more cache devices based on at least one of the one or more processors accessing data managed by the one or more cache devices. (“the processor can snoop other processors' local caches to determine whether those processors have the most up-to-date data”) (paragraph [0028] line 7-8) (“the processor 112 can snoop other processors' local caches to determine whether those processors have the most up-to-date data and can request the CCI 140 to look up the snoop filter 380 to determine whether any other caches in the computing system 300 have that requested cache line.”) (paragraph [0029] line 6-7) (i.e. Fig 1 illustrates processor 112 can request the CCI (Cache coherent interconnect) 140 to look up the snoop filter 380 (Fig 3) to determine whether any other caches in the computing system 300 have that requested cache line. In other words, processor can request CCI if other caches in system 300 have cache line for coherency) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 1 is equally applicable to claim 5. Regarding claim 10, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, further comprising a server, wherein the server comprises the first processor, the first circuitry, the second circuitry, the one or more processors, and the memory device that is to store data associated with the memory address region. On the other hand, Wu which also relates to cache coherence and flushing teaches The apparatus of claim 1, further comprising a server, wherein the server comprises the first processor, the first circuitry, the second circuitry, the one or more processors, and the memory device that is to store data associated with the memory address region. (“the computing system 100 may be a computer, an appliance, a server, or a part of a cloud computing system”) (paragraph [0021] line 2-3) (“FIG. 1 illustrates an example architecture of a multi-processor computing system 100 according to one embodiment. The computing system 100 includes one or more clusters 110, and each cluster 110 further includes one or more processors 112. Each cluster 110 has access to a system memory 130”) (paragraph [0020] line 1-3) (i.e. Fig 1 illustrates computing system 100 which maybe a server includes one or more clusters 110, and each cluster 110 further includes one or more processors 112 and a system memory 130. In other words, computing system may include one or more clusters and each cluster may further include one or more processors and a system memory) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 1 is equally applicable to claim 10. Regarding claim 12, Wu teaches At least one non-transitory A computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: (“receiving a request from a processor by a cache maintenance hardware engine to flush the cache contents to a memory; generating, by the cache maintenance hardware engine, commands to flush the cache contents to thereby remove workload of generating the commands from the processors; and issuing the commands to the clusters, with each command specifying a physical address that identifies a cache line to be flushed”) (paragraph [0006] line 2-7) (i.e. a cache maintenance hardware engine receives commands from the processors and issuing the commands to the clusters to flush a cache line) cause data associated with a memory address region to be flushed from one or more cache devices and configure a processor to access data associated with the memory address region from a memory device without issuance of at least one snoop request based on the data having been flushed from the one or more cache devices. (“FIG. 3 illustrates an example architecture of a multi-processor computing system 300 according to another embodiment”) (paragraph [0029] line 1-2) (“In one embodiment, the CM engine 148 may use the snoop filter 380 to filter its cache flushing commands”) (paragraph [0031] line 1-2) (the method 600 is performed by the CM engine 148 of FIG. 3. At step 610, the CM engine 148 receives a request for whole system flush at time T. In response, at step 620, the CM engine 148 may make a copy of all snoop filter entries that are in the snoop filter 380 at or before time T. Alternatively, the snoop filter 380 may stop updating at time T until the completion of the command generation, and the CM engine 148 may access the snoop filter 380 while it is generating cache flushing commands. The CM engine 148 at step 630 loops through the snoop filter entries to generate cache flushing commands specifying physical addresses that are in the snoop filter 380 at or before time T) (paragraph [0037] line 2-7) (i.e. Fig 3 illustrates Computing system 300 has CM Engine 248 and snoop filter 390. Fig 6 at step 610 illustrates CM (Cache maintenance) engine 148 receives request for whole system flush at time T and in response CM engine may access the snoop filter 380 (Fig 3) to generate cache flushing commands specifying physical addresses that are in the snoop filter before time T and the snoop filter 380 may stop updating at time T until the completion of the flush command. In other words, CM Engine causes snoop filter to update after generating flush command and snoop filter stops updating or coherency when CM Engine generates flush command) (“It is determined at step 430 whether the physical address PA matches a stored physical address in the snoop filter 380; a match indicates that the data entry having the physical address PA is in a cache.”) (paragraph [0032] line 5-7) (i.e. Fig 4 step 430 illustrates when a physical address matches in snoop filter 380 (Fig 3) indicating a data entry in cache) and based on a read or write to the memory address region, permit transmission of snoop requests associated with the memory address region. (“a computing system may use a mechanism for tracking which data entries are cached, in which cluster or clusters a data entry is cached, and the state of each cache data entry. An example of such a mechanism is called snooping. For multi-processor systems with shared memory, snooping-based hardware cache coherence is widely adopted. If a processor's local cache access results in a miss, the processor can snoop other processors' local caches to determine whether those processors have the most up-to-date data”) (paragraph [0032] line 5-7) (i.e. a computing system may use a mechanism called snooping for tracking which data entries are cached for a certain address and the state of each cache data entry and if a processor's local cache access results in a miss the processor can snoop other processors local caches to determine whether those processors have the most up-to-date data. In other words, a computing system can use snooping mechanism for a processor to make sure the data entry or access of read or write for certain address in shared memory for other processors are up to date or coherent) Wu teaches cache coherence and snooping. However, Wu does not explicitly teach based on data having been flushed from one or more cache devices, cause ceasing of transmission of snoop requests associated with a memory address region and configure a processor to access the data associated with the memory address region from a memory device and after ceasing of transmission of snoop requests associated with the memory address region and configuration of the processor to access data associated with the memory address region from the memory device On the other hand, Gupta which also relates to cache coherence and snooping teaches and configure a processor to access the data associated with the memory address region from a memory device and after ceasing of transmission of snoop requests associated with the memory address region and configuration of the processor to access data associated with the memory address region from the memory device (See Fig 4, paragraph [0108], illustrates host processor 445 or accelerator 410 uses bias table lookup as an indication to access memory regions where bias state bit may be used to allow access to memory regions. In other words, bias state bit indicates if it’s allowed to access or not allowed to access to memory regions ) based on data having been flushed from one or more cache devices, cause ceasing of transmission of snoop requests associated with a memory address region , (See Fig 5A and 5B, paragraph [0104] and [0107], illustrates based on indication in snoop-invalidate message coherence controller 530 may return data to a requesting processor core, followed immediately by a snoop-invalidate message . In other words, coherence controller sends message to invalidate or cease snoop requests associated with memory region when flush operation maybe required ) Both Wu and Gupta relate to cache coherence and snooping. Wu teaches cache coherence with flushing commands in an address region. On the other hand, Gupta also teaches cache coherence and snooping and bias state bit indicates if it’s allowed to access or not allowed to access to memory regions and coherence controller sends message to invalidate or cease snoop requests associated with memory region . Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu with Gupta to specify cache coherence and snooping and bias state bit indicates if it’s allowed to access or not allowed to access to memory regions and coherence controller sends message to invalidate or cease snoop requests associated with memory region when flush operation maybe required providing methods which may be used to enable bias-based coherency for device attached memory as mentioned in paragraph [0052]. Regarding claim 13, Wu in view of Gupta teaches cache coherence and snooping in claim 12. However, Wu – Gupta combination does not explicitly teach The computer-readable medium of claim 12, wherein the one or more cache devices comprise two or more cache devices and wherein the processor is to access data associated with the memory address region from the memory device without issuance of at least one snoop request based on the data having been flushed from the two or more cache devices On the other hand, Wu which also relates to cache coherence and snooping teaches The computer-readable medium of claim 12, wherein the one or more cache devices comprise two or more cache devices and wherein the processor is to access data associated with the memory address region from the memory device without issuance of at least one snoop request based on the data having been flushed from the two or more cache devices. (“the processor can snoop other processors' local caches to determine whether those processors have the most up-to-date data”) (paragraph [0028] line 7-8) (“the processor 112 can snoop other processors' local caches to determine whether those processors have the most up-to-date data and can request the CCI 140 to look up the snoop filter 380 to determine whether any other caches in the computing system 300 have that requested cache line.”) (paragraph [0029] line 6-7) (i.e. Fig 1 illustrates processor 112 can request the CCI (Cache coherent interconnect) 140 to look up the snoop filter 380 (Fig 3) to determine whether any other caches in the computing system 300 have that requested cache line. In other words, processor can request CCI if other caches in system 300 have cache line for coherency) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 12 is equally applicable to claim 13. Regarding claim 15, Wu in view of Gupta teaches cache coherence and snooping in claim 12. However, Wu – Gupta combination does not explicitly teach The computer-readable medium of claim 12, wherein the processor comprises one or more of a core, accelerator, graphics processing unit (GPU), central processing unit (CPU), microprocessor, NDP, infrastructure processor unit (IPU), data processing unit (DPU) On the other hand, Wu which also relates to cache coherence and snooping teaches The computer-readable medium of claim 12, wherein the processor comprises one or more of a core, accelerator, graphics processing unit (GPU), central processing unit (CPU), microprocessor, NDP, infrastructure processor unit (IPU), data processing unit (DPU). (“the “multi-processor computing system” as described herein is a “multi-core processor system.” In one embodiment, each processor may contain one or more cores. In an alternative embodiment, each processor may be equivalent to a core. The processors described herein may contain a combination of central processing units (CPUs), a graphics processing units (GPUs), digital signal processors (DSPs), multimedia processors, and any processors that have access to the system memory”) (paragraph [0017] line 1-5) (i.e. Fig 1 illustrates a multi-processor computing system 100 where each processor may contain one or more cores and the processors described herein may contain a combination of central processing units (CPUs), a graphics processing units (GPUs), digital signal processors (DSPs), multimedia processors, and any processors that have access to the system memory) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 12 is equally applicable to claim 15. Regarding claim 17, Wu in view of Gupta teaches cache coherence and snooping in claim 12. However, Wu – Gupta combination does not explicitly teach The computer-readable medium of claim 12, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: based on a second processor accessing the data associated with the memory address region, permitting issuance of a snoop request associated with the memory address region On the other hand, Wu which also relates to cache coherence and snooping teaches The computer-readable medium of claim 12, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: based on a second processor accessing the data associated with the memory address region, permitting issuance of a snoop request associated with the memory address region. (“the processor can snoop other processors' local caches to determine whether those processors have the most up-to-date data”) (paragraph [0028] line 7-8) (“the processor 112 can snoop other processors' local caches to determine whether those processors have the most up-to-date data and can request the CCI 140 to look up the snoop filter 380 to determine whether any other caches in the computing system 300 have that requested cache line.”) (paragraph [0029] line 6-7) (i.e. Fig 1 illustrates processor 112 can request the CCI (Cache coherent interconnect) 140 to look up the snoop filter 380 (Fig 3) to determine whether any other caches in the computing system 300 have that requested cache line. In other words, processor can request CCI if other caches in system 300 have cache line for coherency) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 12 is equally applicable to claim 15. Regarding claim 18, Wu teaches A method comprising: causing data associated with a memory address region to be flushed from one or more cache devices and configuring a processor to access data associated with the memory address region from a memory device without issuance of at least one snoop request based on the data having been flushed from the one or more cache devices. (“FIG. 3 illustrates an example architecture of a multi-processor computing system 300 according to another embodiment”) (paragraph [0029] line 1-2) (“In one embodiment, the CM engine 148 may use the snoop filter 380 to filter its cache flushing commands”) (paragraph [0031] line 1-2) (the method 600 is performed by the CM engine 148 of FIG. 3. At step 610, the CM engine 148 receives a request for whole system flush at time T. In response, at step 620, the CM engine 148 may make a copy of all snoop filter entries that are in the snoop filter 380 at or before time T. Alternatively, the snoop filter 380 may stop updating at time T until the completion of the command generation, and the CM engine 148 may access the snoop filter 380 while it is generating cache flushing commands. The CM engine 148 at step 630 loops through the snoop filter entries to generate cache flushing commands specifying physical addresses that are in the snoop filter 380 at or before time T) (paragraph [0037] line 2-7) (i.e. Fig 3 illustrates Computing system 300 has CM Engine 248 and snoop filter 390. Fig 6 at step 610 illustrates CM (Cache maintenance) engine 148 receives request for whole system flush at time T and in response CM engine may access the snoop filter 380 (Fig 3) to generate cache flushing commands specifying physical addresses that are in the snoop filter before time T and the snoop filter 380 may stop updating at time T until the completion of the flush command. In other words, CM Engine causes snoop filter to update after generating flush command and snoop filter stops updating or coherency when CM Engine generates flush command) (“It is determined at step 430 whether the physical address PA matches a stored physical address in the snoop filter 380; a match indicates that the data entry having the physical address PA is in a cache.”) (paragraph [0032] line 5-7) (i.e. Fig 4 step 430 illustrates when a physical address matches in snoop filter 380 (Fig 3) indicating a data entry in cache) and based on a read or write to the memory address region, permitting transmission of snoop requests associated with the memory address region. (“a computing system may use a mechanism for tracking which data entries are cached, in which cluster or clusters a data entry is cached, and the state of each cache data entry. An example of such a mechanism is called snooping. For multi-processor systems with shared memory, snooping-based hardware cache coherence is widely adopted. If a processor's local cache access results in a miss, the processor can snoop other processors' local caches to determine whether those processors have the most up-to-date data”) (paragraph [0032] line 5-7) (i.e. a computing system may use a mechanism called snooping for tracking which data entries are cached for a certain address and the state of each cache data entry and if a processor's local cache access results in a miss the processor can snoop other processors local caches to determine whether those processors have the most up-to-date data. In other words, a computing system can use snooping mechanism for a processor to make sure the data entry or access of read or write for certain address in shared memory for other processors are up to date or coherent) Wu teaches cache coherence and snooping. However, Wu does not explicitly teach based on data having been flushed from one or more cache devices, cause ceasing of transmission of snoop requests associated with a memory address region and configuring a processor to access the data associated with the memory address region from a memory device and after ceasing of transmission of snoop requests associated with the memory address region and configuration of the processor to access data associated with the memory address region from the memory device On the other hand, Gupta which also relates to cache coherence and snooping teaches and configuring a processor to access the data associated with the memory address region from a memory device and after ceasing of transmission of snoop requests associated with the memory address region and configuration of the processor to access data associated with the memory address region from the memory device (See Fig 4, paragraph [0108], illustrates host processor 445 or accelerator 410 uses bias table lookup as an indication to access memory regions where bias state bit may be used to allow access to memory regions. In other words, bias state bit indicates if it’s allowed to access or not allowed to access to memory regions ) based on data having been flushed from one or more cache devices, cause ceasing of transmission of snoop requests associated with a memory address region (See Fig 5A and 5B, paragraph [0104] and [0107], illustrates based on indication in snoop-invalidate message coherence controller 530 may return data to a requesting processor core, followed immediately by a snoop-invalidate message . In other words, coherence controller sends message to invalidate or cease snoop requests associated with memory region when flush operation maybe required ) Both Wu and Gupta relate to cache coherence and snooping. Wu teaches cache coherence with flushing commands in an address region. On the other hand, Gupta also teaches cache coherence and snooping and bias state bit indicates if it’s allowed to access or not allowed to access to memory regions and coherence controller sends message to invalidate or cease snoop requests associated with memory region . Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu with Gupta to specify cache coherence and snooping and bias state bit indicates if it’s allowed to access or not allowed to access to memory regions and coherence controller sends message to invalidate or cease snoop requests associated with memory region when flush operation maybe required providing methods which may be used to enable bias-based coherency for device attached memory as mentioned in paragraph [0052]. Regarding claim 19, Wu in view of Gupta teaches cache coherence and snooping in claim 18. However, Wu – Gupta combination does not explicitly teach The method of claim 18, wherein the processor comprises one or more of a core, accelerator, graphics processing Lenit (GPU), central processing unit (CPU), microprocessor, NDP, infrastructure processor unit (IPU), data processing unit (DPU) On the other hand, Wu which also relates to cache coherence and snooping teaches The method of claim 18, wherein the processor comprises one or more of a core, accelerator, graphics processing Lenit (GPU), central processing unit (CPU), microprocessor, NDP, infrastructure processor unit (IPU), data processing unit (DPU). (“the “multi-processor computing system” as described herein is a “multi-core processor system.” In one embodiment, each processor may contain one or more cores. In an alternative embodiment, each processor may be equivalent to a core. The processors described herein may contain a combination of central processing units (CPUs), a graphics processing units (GPUs), digital signal processors (DSPs), multimedia processors, and any processors that have access to the system memory”) (paragraph [0017] line 1-5) (i.e. Fig 1 illustrates a multi-processor computing system 100 where each processor may contain one or more cores and the processors described herein may contain a combination of central processing units (CPUs), a graphics processing units (GPUs), digital signal processors (DSPs), multimedia processors, and any processors that have access to the system memory) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 18 is equally applicable to claim 19. Regarding claim 21, Wu in view of Gupta teaches cache coherence and snooping in claim 18. However, Wu – Gupta combination does not explicitly teach The method of claim 18, comprising: based on a second processor accessing the data associated with the memory address region, permitting issuance of a snoop request associated with the memory address region On the other hand, Wu which also relates to cache coherence and snooping teaches The method of claim 18, comprising: based on a second processor accessing the data associated with the memory address region, permitting issuance of a snoop request associated with the memory address region. (“the processor can snoop other processors' local caches to determine whether those processors have the most up-to-date data”) (paragraph [0028] line 7-8) (“the processor 112 can snoop other processors' local caches to determine whether those processors have the most up-to-date data and can request the CCI 140 to look up the snoop filter 380 to determine whether any other caches in the computing system 300 have that requested cache line.”) (paragraph [0029] line 6-7) (i.e. Fig 1 illustrates processor 112 can request the CCI (Cache coherent interconnect) 140 to look up the snoop filter 380 (Fig 3) to determine whether any other caches in the computing system 300 have that requested cache line. In other words, processor can request CCI if other caches in system 300 have cache line for coherency) The same motivation that was utilized for combining Wu and Gupta as set forth in claim 18 is equally applicable to claim 21 . 07-21-aia AIA Claim (s) 22 and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Gupta and further in view of Arimilli et al. (US 20030009631 A1) hereinafter Arimilli . Regarding claim 22, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, wherein the circuitry is to resume snoop requests associated with the memory address region based on a read or write to the memory address region . On the other hand, Arimilli which also relates to cache coherence and snooping teaches The apparatus of claim 1, wherein the circuitry is to resume snoop requests associated with the memory address region based on a read or write to the memory address region . (See Fig 12, paragraph [0119], illustrates after all flush operations are complete at 330, system memory read operations is initiated where memory controller 71 considers read or write operations) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 1 above. In addition, Wu, Gupta and Arimilli are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Arimilli also teaches cache coherence and snooping and after all flush operations are complete at 330, system memory read operations is initiated where memory controller 71 considers read or write operations. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Arimilli to specify cache coherence and snooping and after all flush operations are complete at 330, system memory read operations is initiated where memory controller 71 considers read or write operations providing a method of operation that improves memory access time for exclusive access operations through memory directory management as mentioned in paragraph [0012]. Regarding claim 25, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, wherein the circuitry is to: monitor flushing of data associated with the memory address region by the one or more cache devices and cease transmission of snoop requests associated with the memory address region based on a number of the one or more cache devices that have not flushed stored data associated with the memory address region being zero . On the other hand, Arimilli which also relates to cache coherence and snooping teaches The apparatus of claim 1, wherein the circuitry is to: monitor flushing of data associated with the memory address region by the one or more cache devices and (See Fig 10A and 10B, paragraph [0098], illustrates cache lines are tracked in LMD for access requests for flush commands by memory controller) cease transmission of snoop requests associated with the memory address region based on a number of the one or more cache devices that have not flushed stored data associated with the memory address region being zero . (See Fig 12, paragraph [0105], illustrates node controller 56 flush accepted combined responses to cease or null combined responses to all snoopers for the address regions of memory system) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 1 above. In addition, Wu, Gupta and Arimilli are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Arimilli also teaches cache coherence and snooping and cache lines are tracked in LMD for access requests for flush commands by memory controller and node controller 56 flush accepted combined responses to cease or null combined responses to all snoopers for the address regions of memory system. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Arimilli to specify cache coherence and snooping and cache lines are tracked in LMD for access requests for flush commands by memory controller and node controller 56 flush accepted combined responses to cease or null combined responses to all snoopers for the address regions of memory system providing a method of operation that improves memory access time for exclusive access operations through memory directory management as mentioned in paragraph [0012]. Regarding claim 26 Wu in view of Gupta teaches cache coherence and snooping in claim 18. However, Wu – Gupta combination does not explicitly teach The method of claim 18, wherein the ceasing transmission of snoop requests associated with a memory address region is based on all of the one or more cache devices having flushed stored data associated with the memory address region to the memory device . On the other hand, Arimilli which also relates to cache coherence and snooping teaches The method of claim 18, wherein the ceasing transmission of snoop requests associated with a memory address region is based on all of the one or more cache devices having flushed stored data associated with the memory address region to the memory device (See Fig 2B and 3, paragraph [0093], illustrates Flush query is snooped by the local node controller 56 and transmitted by node controller 56 either to each remote node 52 specified in the Flush query or to all remote nodes 52 of the memory system) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 1 above. In addition, Wu, Gupta and Arimilli are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Arimilli also teaches cache coherence and snooping and Flush query is snooped by the local node controller 56 and transmitted by node controller 56 either to each remote node 52 specified in the Flush query or to all remote nodes 52 of the memory system. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Arimilli to specify cache coherence and snooping and Flush query is snooped by the local node controller 56 and transmitted by node controller 56 either to each remote node 52 specified in the Flush query or to all remote nodes 52 of the memory system providing a method of operation that improves memory access time for exclusive access operations through memory directory management as mentioned in paragraph [0012] . 07-21-aia AIA Claim (s) 24 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Gupta and further in view of Mullender et al. (US 20180357108 A1) hereinafter Mullender . Regarding claim 24, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, wherein the circuitry is to: after the indication to discontinue access to the memory address region, based on and subsequent access to the memory region by a processor of the one or more processors, permit issuance of a snoop requests associated with the memory address region. On the other hand, Mullender which also relates to cache coherence teaches The apparatus of claim 1, wherein the circuitry is to: after the indication to discontinue access to the memory address region, based on and subsequent access to the memory region by a processor of the one or more processors, permit issuance of a snoop requests associated with the memory address region (See Fig 4, paragraph [0054], illustrates under certain conditions computing system 400 can enable cache coherency by default and disable cache coherency or vice versa and cache coherency may include snooping) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 1 above. In addition, Wu, Gupta and Mullender are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Mullender also teaches cache coherence and snooping and under certain conditions computing system 400 can enable cache coherency by default and disable cache coherency or vice versa and cache coherency may include snooping. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Mullender to specify cache coherence and snooping and under certain conditions computing system 400 can enable cache coherency by default and disable cache coherency or vice versa and cache coherency may include snooping providing resource group access to a particular peripheral device and denies access to a different peripheral device as mentioned in paragraph [0010] . 07-21-aia AIA Claim (s) 11, 14, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Gupta and further in view of Robinson et al. (US 20190266091 A1) hereinafter Robinson . Regarding claim 11, Wu in view of Gupta teaches cache coherence and snooping in claim 10. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 10, further comprising a data center, wherein the data center comprises the server and a second server wherein the second server is communicatively coupled to the server using a network interface device, the second server is to transmit data to be stored in the memory address region. On the other hand, Robinson which also relates to cache coherence and flushing teaches The apparatus of claim 10, further comprising a data center, wherein the data center comprises the server and a second server wherein the second server is communicatively coupled to the server using a network interface device, the second server is to transmit data to be stored in the memory address region. (“The master devices 152, 154, 156 couple to the slave devices 160, 162, 164 via a bus, communication fabric or network-on-chip (NoC) 170”) (paragraph [0087] line 5-6) (i.e. Fig 1 illustrates master devices 152, 154, 156 couple to the slave devices 160, 162, 164 via a communication fabric or network-on-chip (NoC) 170. In other words, devices which are considered as severs or processors are coupled with each other via a network interface of chip) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 10 above. In addition, Wu, Gupta and Robinson are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Robinson also teaches cache coherence and snooping and devices which are considered as severs or processors are coupled with each other via a network interface of chip. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Robinson to specify cache coherence and snooping and devices which are considered as severs or processors are coupled with each other via a network interface of chip providing better resolution in data conflicts and multiple snoop requests as mentioned in paragraph [0002]. Regarding claim 14, Wu in view of Gupta teaches cache coherence and snooping in claim 12. However, Wu – Gupta combination does not explicitly teach The computer-readable medium of claim 12, wherein the cause data associated with a memory address region from one or more cache devices comprises a writeback of the data associated with the memory address region to a memory device. On the other hand, Robinson which also relates to cache coherence and flushing teaches The computer-readable medium of claim 12, wherein the cause data associated with a memory address region from one or more cache devices comprises a writeback of the data associated with the memory address region to a memory device. (“The coherency manager 322 can also monitor outgoing coherent transactions on the Address Write (AW) interface (for example writeback and evict transactions), and incoming responses on the write response (B) channel (for example responses to the writeback and evict transactions) to be able to update cache line status and to drive a write acknowledgement signal (‘WACK’) 514”) (paragraph [0109] line 11-14) (i.e. Fig 4 illustrates coherency manager 322 monitors outgoing coherent transactions on the Address Write (AW) interface (for example writeback and evict transactions) incoming responses on the write response (B) channel (for example responses to the writeback and evict transactions) to be able to update cache line status. In other words, coherency manager updates cache line by write back after monitoring eviction or flushing) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 12 above. In addition, Wu, Gupta and Robinson are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Robinson also teaches cache coherence and flushing and coherency manager updating cache line by write back after monitoring eviction or flushing. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Robinson to specify cache coherence and flushing and coherency manager updating cache line by write back after monitoring eviction or flushing providing ability to allocate plurality of zones providing better resolution in data conflicts and multiple snoop requests as mentioned in paragraph [0002]. Regarding claim 16, Wu in view of Gupta teaches cache coherence and snooping in claim 12. However, Wu – Gupta combination does not explicitly teach The computer-readable medium of claim 12, wherein the memory comprises one or more of: at least one register, at least one cache device, at least one volatile memory device, at least one non-volatile memory device, or at least one persistent memory device. On the other hand, Robinson which also relates to cache coherence and flushing teaches The computer-readable medium of claim 12, wherein the memory comprises one or more of: at least one register, at least one cache device, at least one volatile memory device, at least one non-volatile memory device, or at least one persistent memory device. (“a computer-readable storage medium include a random-access memory (RAM), read-only memory (ROM), an optical disc, flash memory, hard disk memory, and other memory devices”) (paragraph [0272] line 9-11) (“The reverse translation module 550 suitably comprises a register array”) (paragraph [0150] line 2-3) (“A computing system such as computing system 100 comprises a first processor 102, a first cache memory 104 and a main memory 114”) (paragraph [0069] line 1-2) (i.e. Fig 1, 5 and 6A illustrate computing system 100 comprises cache memory 104, register array 550 and different types memory including flash, volatile memories etc) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 12 above. In addition, Wu, Gupta and Robinson are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Robinson also teaches cache coherence and flushing and computing system comprising cache memory, register array and different types memory including flash, volatile memories. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Robinson to specify cache coherence and flushing and computing system comprising cache memory, register array and different types memory including flash, volatile memories providing better resolution in data conflicts and multiple snoop requests as mentioned in paragraph [0002]. Regarding claim 20, Wu in view of Gupta teaches cache coherence and snooping in claim 18. However, Wu – Gupta combination does not explicitly teach The method of claim 18, wherein the flush of data associated with the memory address region from the one or more cache devices comprises a writeback of the data associated with the memory address region to a memory device. On the other hand, Robinson which also relates to cache coherence and flushing teaches The method of claim 18, wherein the flush of data associated with the memory address region from the one or more cache devices comprises a writeback of the data associated with the memory address region to a memory device. (“The coherency manager 322 can also monitor outgoing coherent transactions on the Address Write (AW) interface (for example writeback and evict transactions), and incoming responses on the write response (B) channel (for example responses to the writeback and evict transactions) to be able to update cache line status and to drive a write acknowledgement signal (‘WACK’) 514”) (paragraph [0109] line 11-14) (i.e. Fig 4 illustrates coherency manager 322 monitors outgoing coherent transactions on the Address Write (AW) interface (for example writeback and evict transactions) incoming responses on the write response (B) channel (for example responses to the writeback and evict transactions) to be able to update cache line status. In other words, coherency manager updates cache line by write back after monitoring eviction or flushing) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 12 above. In addition, Wu, Gupta and Robinson are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Robinson also teaches cache coherence and flushing and coherency manager updating cache line by write back after monitoring eviction or flushing. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Robinson to specify cache coherence and flushing and coherency manager updating cache line by write back after monitoring eviction or flushing providing ability to allocate plurality of zones providing better resolution in data conflicts and multiple snoop requests as mentioned in paragraph [0002] . 07-21-aia AIA Claim (s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Gupta and further in view of Pal et al. (US 20210200678 A1) hereinafter Pal . Regarding claim 8, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, wherein the first circuitry is part of a cache and home agent (CHA) and part of a memory controller. On the other hand, Pal which also relates to cache coherence and flushing teaches The apparatus of claim 1, wherein the first circuitry is part of a cache and home agent (CHA) and part of a memory controller. (“the cache-coherent fabric 200 is divided into primary and secondary paths comprising two caching agents CA (primary CA (PCA) 210.P and secondary CA (SCA) 210.S) and associated memory controllers MC (primary MC (PMC) 220.P and secondary MC (SMC) 220.S)”) (paragraph [0020] line 3-5) (i.e. Fig 1 illustrates cache-coherent fabric 200 have two caching agents CAs and two memory controllers MCs handling caching activities) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 12 above. In addition, Wu, Gupta and Pal are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Pal also teaches cache coherence and flushing and cache-coherent fabric having two caching agents CAs and two memory controllers MCs handling caching activities. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Pal to specify cache coherence and flushing and cache-coherent fabric having two caching agents CAs and two memory controllers MCs handling caching activities providing redundant cache-coherent fabric memory fabric as mentioned in paragraph [0001]. Regarding claim 9, Wu in view of Gupta teaches cache coherence and snooping in claim 1. However, Wu – Gupta combination does not explicitly teach The apparatus of claim 1, wherein the memory address region comprises sub-regions which are capable of being managed separately or together or accesses to the memory address region is monitored to initiate operations that trigger discontinuation of one or more snoop probes. On the other hand, Pal which also relates to cache coherence and flushing teaches The apparatus of claim 1, wherein the memory address region comprises sub-regions which are capable of being managed separately or together or accesses to the memory address region is monitored to initiate operations that trigger discontinuation of one or more snoop probes. (“The memory 700 has an address space divided into one or more safety memory address regions 710, 730, and one or more non-safety memory address regions 720, 740. The safety memory address regions 710, 730 may be allocated to safety-related applications, such as ASIL-compliant applications. This demarcation can be established by the Basic Input/Output System (BIOS) when setting up the memory addresses on system boot. The redundant access manager 120 is configured to redundantly distribute the access request only if the access request is for memory access within a safety memory address region 710,730”) (paragraph [0055] line 1-6) (i.e. Fig 7 illustrates memory 700 has an address space divided into one or more safety memory address regions 710, 730, and one or more non-safety memory address regions 720, 740. Each of these address regions are configured to redundantly distribute the access request. In other words, memory space 700 are divided into regions and they are capable of independently managed) It would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to combine Wu with Gupta for the reasons set forth in claim 12 above. In addition, Wu, Gupta and Pal are considered analogous arts, because they all relate to cache coherence and snooping. Wu - Gupta combination teaches cache coherence with flushing commands in an address region. On the other hand, Pal also teaches cache coherence and flushing and memory space being divided into regions and they are capable of independently managed. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine Wu - Gupta combination with Pal to specify cache coherence and flushing and memory space being divided into regions and they are capable of independently managed providing redundant cache-coherent fabric memory fabric as mentioned in paragraph [0001]. Response to Arguments 07-37 Applicant’s arguments filed on 06/29/2026 have been fully considered but they are not persuasive. Applicant’s first argument is claim 1 mapping by primary reference Wu or Arimilli in page 2 of the response: The Final Office Action relies on Arimilli, rather than Wu, to teach "the circuitry is to stop a snoop request from being sent to the one or more cache devices." (Final Office Action, page 4.) Arimilli teaches, at [0104] and [0105], a memory controller receives a flush command to invalidate a cache line and provides a snoop response (Null snoop response) indicating that the memory controller is accepting coherency management responsibility for the flush command. Arimilli teaches, at [0106], that cache hierarchies that do not hold a valid copy of the target cache line provide a Null snoop response. Arimilli's Null snoop response does not cause the memory controller to cease transmission of snoop requests. Arimilli's snoop response is not a snoop request. Arimilli is silent on ceasing transmission of snoop requests. Claim 1 requires that a data flush of a memory address region causes cease of transmission of snoop requests associated with the memory address region. At least for these reasons, Wu and Arimilli fail to teach or suggest at least the cited portion of claim 1. Withdrawal of the rejection of claim 1 is requested for at least this reason In summary, applicant argued that references Wu or Arimilli do not teach amended limitation ceasing or stopping snooping requests in the address region based on data flush in the memory region. The amendment necessitates adding secondary reference Gupta in this regard. For further clarification examiner cites portion from Gupta. Also, for applicant’s understanding examiner would like to explain the teachings of Gupta and examiner’s interpretation in more detail here. See Fig 4, paragraph [0108], Gupta teaches host processor 445 or accelerator 410 uses bias table lookup as an indication to access memory regions where bias state bit may be used to allow access to memory regions. In other words, bias state bit indicates if it’s allowed to access or not allowed to access to memory regions . Also See Fig 5A and 5B, paragraph [0104] and [0107], Gupta teaches based on indication in snoop-invalidate message coherence controller 530 may return data to a requesting processor core, followed immediately by a snoop-invalidate message . In other words, coherence controller sends message to invalidate or cease snoop requests associated with memory region when flush operation maybe required . The cited portions clearly teach when flush operation is required controller sends message to invalidate or cease snoop requests associated with memory region. Thus, the rejection of amended claims 1 is maintained. Same argument applies for claim 12 and 18. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBIR K CHOWDHURY whose telephone number is (703)756-1207. The examiner can normally be reached Monday-Friday 8:30 - 5:00 CST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.K.C./Examiner, Art Unit 2132 /HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132 Application/Control Number: 17/552,239 Page 2 Art Unit: 2132 Application/Control Number: 17/552,239 Page 3 Art Unit: 2132 Application/Control Number: 17/552,239 Page 4 Art Unit: 2132 Application/Control Number: 17/552,239 Page 5 Art Unit: 2132 Application/Control Number: 17/552,239 Page 6 Art Unit: 2132 Application/Control Number: 17/552,239 Page 7 Art Unit: 2132 Application/Control Number: 17/552,239 Page 8 Art Unit: 2132 Application/Control Number: 17/552,239 Page 9 Art Unit: 2132 Application/Control Number: 17/552,239 Page 10 Art Unit: 2132 Application/Control Number: 17/552,239 Page 11 Art Unit: 2132 Application/Control Number: 17/552,239 Page 12 Art Unit: 2132 Application/Control Number: 17/552,239 Page 13 Art Unit: 2132 Application/Control Number: 17/552,239 Page 14 Art Unit: 2132 Application/Control Number: 17/552,239 Page 15 Art Unit: 2132 Application/Control Number: 17/552,239 Page 16 Art Unit: 2132 Application/Control Number: 17/552,239 Page 17 Art Unit: 2132 Application/Control Number: 17/552,239 Page 18 Art Unit: 2132 Application/Control Number: 17/552,239 Page 19 Art Unit: 2132 Application/Control Number: 17/552,239 Page 20 Art Unit: 2132 Application/Control Number: 17/552,239 Page 21 Art Unit: 2132 Application/Control Number: 17/552,239 Page 22 Art Unit: 2132 Application/Control Number: 17/552,239 Page 23 Art Unit: 2132 Application/Control Number: 17/552,239 Page 24 Art Unit: 2132 Application/Control Number: 17/552,239 Page 25 Art Unit: 2132 Application/Control Number: 17/552,239 Page 26 Art Unit: 2132 Application/Control Number: 17/552,239 Page 27 Art Unit: 2132 Application/Control Number: 17/552,239 Page 28 Art Unit: 2132 Application/Control Number: 17/552,239 Page 29 Art Unit: 2132 Application/Control Number: 17/552,239 Page 30 Art Unit: 2132 Application/Control Number: 17/552,239 Page 31 Art Unit: 2132 Application/Control Number: 17/552,239 Page 32 Art Unit: 2132 Application/Control Number: 17/552,239 Page 33 Art Unit: 2132 Application/Control Number: 17/552,239 Page 34 Art Unit: 2132 Application/Control Number: 17/552,239 Page 35 Art Unit: 2132 Application/Control Number: 17/552,239 Page 36 Art Unit: 2132 Application/Control Number: 17/552,239 Page 37 Art Unit: 2132 Application/Control Number: 17/552,239 Page 38 Art Unit: 2132 Application/Control Number: 17/552,239 Page 39 Art Unit: 2132 Application/Control Number: 17/552,239 Page 40 Art Unit: 2132
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