Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This Office action is in response to the application filed on December 15, 2021.
Specification
The title is objected to for failure to be sufficiently descriptive.
The specification has not been checked to the extent necessary to determine the
presence of all possible minor errors. The applicant's cooperation is requested in correcting any errors of which the applicant may become aware in the specification.
Claim Objections
Claims 1 and 12 are objected to because of the following informalities:
Claim 1
In line 36, “the H-bridge” should be –a first--
Claim 12
In line 31, “the H-bridge” should be –an H-bridge--
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 8 and 21 is rejected under 35 U.S.C. 112(a), first paragraph, as failing to
comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification fails to provide an enabling description for “wherein the delay locked loop comprises 25 delay lines and the delay locked loop adjusts the duty cycle of the first phase clock signal and the second phase clock signal from 20% to 50% with a 2% step size” as recited in Claims 8 and 21. The specification discloses on page 17, lines 29-31:
To perform a duty-cycle from 20% to 50% with a 2% step size, the delay line of the DLL 332comprises 25 delay units, with the output of each respective delay unit representing a Phase nth.
This disclosure recites that in order to achieve a duty cycle from 20% to 50% with a 2% step size, a single delay line of the DLL comprising 25 delay units is required. It does not recite the claimed “25 delay lines.” Moreover, it does not recite the claimed duty-cycle adjustment for two clock signals. Lastly, it does not recite the claimed duty-cycle adjustment performed by the DLL. The examiner assumes that these definitions are distinct from the original content in the specification, and are therefore, new.
Double Patenting (Same Invention)
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-5, 12-20, and 22-30 are rejected under 35 U.S.C. 101 as claiming
the same invention as that of claims of prior U.S. Patent No.:
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11665483 [17877851]
This is a statutory double patenting rejection.
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1. A microchip…comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during the positive half-period of the main clock signal and low during the negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein the phases of the first phase clock signal and the second phase clock signal are centre aligned; a pulse width modulation (PWM) signal generator subsystem comprising: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double the frequency of the main clock signal, wherein the delay locked loop controls the rising edge of the first phase clock signal and the second phase clock signal to be synchronous with the rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts the frequency and the duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal, wherein the first phase output signal and the second phase output signal are configured to drive the first circuit to generate an AC drive signal to drive the resonant circuit; a first phase output signal terminal which outputs the first phase output signal to the first circuit; a second phase output signal terminal which outputs the second phase output signal to the first circuit.
2. The microchip of claim 1, wherein the oscillator generates the main clock signal at a frequency of 50 kHz to 105 MHz.
3. The microchip of claim 1, wherein the microchip further comprises: a frequency divider which is connected to the oscillator to receive the main clock signal from the oscillator, the frequency divider dividing the main clock signal by a predetermined divisor amount and outputting a frequency reference signal to the delay locked loop.
4. The microchip of claim 1, wherein the delay locked loop comprises a plurality of delay lines connected end to end, wherein a total delay of the plurality of delay lines is equal to a period of the main clock signal.
5. The microchip of claim 4, wherein the delay locked loop adjusts the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by varying a delay of each of the plurality of delay lines in the delay locked loop.
11653152 [17/877848]
1. A microchip…comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; a pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive an H-bridge circuit to generate an AC drive signal to drive the resonant circuit; a first phase output signal terminal which outputs the first phase output signal to the H-bridge circuit; a second phase output signal terminal which outputs the second phase output signal to the H-bridge circuit;…
2. The microchip of claim 1, wherein the oscillator generates the main clock signal at a frequency of 50 kHz to 105 MHz.
3. The microchip of claim 1, wherein the microchip further comprises: a frequency divider which is connected to the oscillator to receive the main clock signal from the oscillator, the frequency divider dividing the main clock signal by a predetermined divisor amount and outputting a frequency reference signal to the delay locked loop.
4. The microchip of claim 1, wherein the delay locked loop comprises a plurality of delay lines connected end to end, wherein a total delay of the plurality of delay lines is equal to a period of the main clock signal.
5. The microchip of claim 4, wherein the delay locked loop adjusts the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by varying a delay of
11665483 [17877851]
1. … a microchip…comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; a pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive the H-bridge circuit to generate the AC drive signal to drive the resonant circuit; a first phase output signal terminal which outputs the first phase output signal to the H-bridge circuit; a second phase output signal terminal which outputs the second phase output signal to the H-bridge circuit;…
2. The apparatus of claim 1, wherein the oscillator generates the main clock signal at a frequency of 50 kHz to 105 MHz.
3. The apparatus of claim 1, wherein the microchip further comprises: a frequency divider which is connected to the oscillator to receive the main clock signal from the oscillator, the frequency divider dividing the main clock signal by a predetermined divisor amount and outputting a frequency reference signal to the delay locked loop.
4. The apparatus of claim 1, wherein the delay locked loop comprises a plurality of delay lines connected end to end, wherein a total delay of the plurality of delay lines is equal to a period of the main clock signal.
5. The apparatus of claim 4, wherein the delay locked loop adjusts the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by varying a delay of
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12. A system for transmitting ultrasonic waves, the system comprising: a resonant circuit, wherein the resonant circuit is at least one of an LC tank, an antenna and a piezoelectric transducer; a microchip connected to the resonant circuit, wherein the microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; a pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive the H-bridge circuit to generate the AC drive signal to drive the resonant circuit;a first power supply terminal; a second power supply terminal; the H-bridge circuit which incorporates a first switch, a second switch, a third switch and a fourth switch, wherein: the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal is connected electrically between the first switch and the third switch, the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal, and a second output terminal is connected electrically between the second switch and the fourth switch; a first phase terminal which receives a first phase output signal from the pulse width modulation (PWM) signal
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each of the plurality of delay lines in the delay locked loop.
6. The microchip of claim 1, wherein the feedback input terminal receives a feedback signal which is indicative of a parameter of operation of the H-bridge circuit or AC drive signal when the H-bridge circuit is driving the resonant circuit with the AC drive signal.
7. The microchip of claim 1, wherein the feedback input terminal receives a feedback signal from the H-bridge circuit in a form of a voltage which indicative of an rms current of an AC drive signal which is driving the resonant circuit.
8. The microchip of claim 1, wherein the ADC subsystem comprises a plurality of further ADC input terminals which receive feedback signals which are indicative of at least one of a voltage of a battery connected to the microchip or the voltage of a battery charger connected to the microchip.
9. The microchip of claim 1, wherein the microchip further comprises: a temperature sensor which is embedded within the microchip, wherein the temperature sensor generates a temperature signal which is indicative of a temperature of the microchip, and wherein the temperature signal is received by a further ADC input terminal of the ADC subsystem and the temperature signal is sampled by the ADC subsystem.
10. The microchip of claim 1, wherein the ADC subsystem samples signals received at the plurality of ADC input terminals sequentially with each signal being sampled by the ADC subsystem a respective predetermined number of times.
11. The microchip of claim 1, wherein the microchip further comprises: a battery charging subsystem which controls charging of an external battery which is connected to the microchip.
12. The microchip of claim 1, wherein the DAC subsystem comprises: a further
digital to analogue converter (DAC) which converts a further digital control signal generated by the digital processor subsystem into a further analogue voltage control signal to control the voltage regulator circuit.
13. A microchip…comprising: an oscillator an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; a pulse width modulation (PWM) signal generator
11665483 [17877851]
each of the plurality of delay lines in the delay locked loop.6. The apparatus of claim 1, wherein the feedback input terminal receives a feedback signal from the H-bridge circuit in a form of a voltage which is indicative of an rms current of the AC drive signal which is driving the resonant circuit.
7. The apparatus of claim 1, wherein the ADC subsystem comprises a plurality of further ADC input terminals which receive feedback signals which are indicative of at least one of a voltage of a battery connected to the apparatus or the voltage of a battery charger connected to the apparatus.
8. The apparatus of claim 1, wherein the microchip further comprises: a temperature sensor which is embedded within the microchip, wherein the temperature sensor generates a temperature signal which is indicative of a temperature of the microchip, and wherein the temperature signal is received by a further ADC input terminal of the ADC subsystem and the temperature signal is sampled by the ADC subsystem.
9. The apparatus of claim 1, wherein the ADC subsystem samples signals received at the plurality of ADC input terminals sequentially with each signal being sampled by the ADC subsystem a respective predetermined number of times.
10. The apparatus of claim 1, wherein the microchip further comprises: a battery charging subsystem which controls charging of an external battery which is connected to the microchip.
11. The apparatus of claim 1, wherein the DAC subsystem comprises: a further digital to analogue converter (DAC) which converts a further digital control signal generated by the digital processor subsystem into a further analogue voltage control signal to control the voltage regulator circuit.
12. An apparatus for transmitting ultrasonic waves, the apparatus comprising: a resonant circuit, wherein the resonant circuit is at least one of an LC tank, an antenna and a piezoelectric transducer; a microchip connected to the resonant circuit, and wherein the microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and
the second phase clock signal are centre
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generator; a second phase terminal which receives a second phase output signal from the PWM signal generator; a digital state machine which generates timing signals based on the first phase output signal and the second phase output signal and outputs the timing signals to switches of the H-bridge circuit to control the switches to turn on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit the ultrasonic waves.
13. The microchip of claim 12, wherein the H-bridge circuit outputs a power of 22 W to 50 W to the resonant circuit which is connected to the first output terminal and the second output terminal.
14. The microchip of claim 12, wherein the oscillator generates the main clock signal at a frequency of 50 kHz to 105 MHz. (See Claim 2 in the patents)
15. A system for transmitting ultrasonic waves, the system comprising: a resonant circuit, wherein the resonant circuit is at least one of an LC tank, an antenna and a piezoelectric transducer; a first microchip connected to the resonant circuit, wherein the first microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: a first power supply terminal; a second power supply terminal; an H-bridge circuit which incorporates a first switch, a second switch, a third switch and a fourth switch, wherein: the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal is connected electrically between the first switch and the third switch, the first output terminal being connected to a first terminal of the resonant circuit, the second switch and the
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subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive an H-bridge circuit to generate an AC drive signal to drive the resonant circuit; a first power supply terminal; a second power supply terminal; the H-bridge circuit which incorporates a first switch, a second switch, a third switch and a fourth switch, wherein: the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal is connected electrically between the first switch and the third switch, the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal, and a second output terminal is connected electrically between the second switch and the fourth switch; a first phase terminal which receives a first phase output signal from the pulse width modulation (PWM) signal generator; a second phase terminal which receives a second phase output signal
11665483 [17877851]
aligned; a pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive an H-bridge circuit to generate an AC drive signal to drive the resonant circuit; a first power supply terminal; a second power supply terminal; the H-bridge circuit which incorporates a first switch, a second switch, a third switch and a fourth switch, wherein: the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal is connected electrically between the first switch and the third switch, the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal, and a second output terminal is connected electrically between the second switch and the fourth switch; a first phase terminal which receives a first phase
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fourth switch are connected in series between the first power supply terminal and the second power supply terminal, and a second output terminal is connected electrically between the second switch and the fourth switch, the second output terminal being connected to a second terminal of the resonant circuit; a first phase terminal which receives a first phase output signal from a pulse width modulation (PWM) signal generator subsystem; a second phase terminal which receives a second phase output signal from the PWM signal generator subsystem; a digital state machine which generates timing signals based on the first phase output signal and the second phase output signal and outputs the timing signals to switches of the H-bridge circuit to control the switches to turn on and off in a sequence such that the H- bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit the ultrasonic waves; and a second microchip connected
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from the pulse width modulation (PWM) signal generator; a digital state machine which generates timing signals based on the first phase output signal and the second phase output signal and outputs the timing signals to switches of the H-bridge circuit to control the switches to turn on and off in a sequence such that the H-bridge circuit outputs an AC drive signal for driving the resonant circuit, wherein the sequence comprises a free-float period in which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on in order to dissipate energy stored by the resonant circuit; a current sensor which incorporates: a first current sense resistor which is connected in series between the first switch and the first power supply terminal; a first voltage sensor which measures a voltage drop across the first current sense resistor and provides a first voltage output which is indicative of a current flowing through the first current sense resistor; a second current sense resistor which is connected in series between the second switch and the first power supply terminal; a second voltage sensor which measures a voltage drop across the second current sensor resistor and provides a second voltage output which is indicative of a current flowing through the second current sense resistor; and a current sensor output terminal which provides an rms output voltage relative to ground which is equivalent to the first voltage output and the second voltage output, wherein the rms output voltage is indicative of an rms current flowing through the first switch or the second switch and the current flowing through the resonant circuit which is connected between the first output terminal and the second output terminal.
14. The microchip of claim 13, wherein the H-bridge circuit is configured to output a power of 22 W to 50 W to the resonant circuit which is connected to the first output terminal and the second output terminal.
15. The microchip of claim 13, wherein the microchip further comprises: a temperature sensor which is embedded within the microchip, wherein the temperatures sensor measures the temperature of the microchip and disables at least part of the microchip in the event that the temperature sensor senses that the microchip is at a temperature which is in excess of a predetermined threshold.
11665483 [17877851]
output signal from the pulse width modulation (PWM) signal generator; a second phase terminal which receives a second phase output signal from the pulse width modulation (PWM) signal generator; a digital state machine which generates timing signals based on the first phase output signal and the second phase output signal and outputs the timing signals to switches of the H-bridge circuit to control the switches to turn on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit the ultrasonic waves, wherein the sequence comprises a free-float period in which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on in order to dissipate energy stored by the resonant circuit; a current sensor which incorporates: a first current sense resistor which is connected in series between the first switch and the first power supply terminal; a first voltage sensor which measures a voltage drop across the first current sense resistor and provides a first voltage output which is indicative of a current flowing through the first current sense resistor; a second current sense resistor which is connected in series between the second switch and the first power supply terminal; a second voltage sensor which measures a voltage drop across the second current sensor resistor and provides a second voltage output which is indicative of a current flowing through the second current sense resistor; and a current sensor output terminal which provides an rms output voltage relative to ground which is equivalent to the first voltage output and the second voltage output, wherein the rms output voltage is indicative of an rms current flowing through the first switch or the second switch and the current flowing through the resonant circuit which is connected between the first
output terminal and the second output terminal.
13. The apparatus of claim 12, wherein the H-bridge circuit is configured to output a power of 22 W to 50 W to the resonant circuit which is connected to the first output terminal and the second output terminal.
14. The apparatus of claim 12, wherein the microchip further comprises: a temperature sensor which is embedded within the microchip, wherein the temperatures sensor measures the temperature of the microchip and disables at least part of the microchip in the event that the temperature sensor senses that the microchip is at a temperature which is in excess of a predetermined threshold.
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to the first microchip to control the H-bridge circuit to generate the AC drive signal, wherein the second microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; the pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, wherein the PWM signal generator subsystem comprises: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive the H-bridge circuit to generate an AC drive signal to drive the resonant circuit; a first phase output signal terminal which outputs the first phase output signal to the H-bridge circuit; and a second phase output signal terminal which outputs the second phase output signal to the H-bridge circuit.
16. The system of claim 15, wherein the H-bridge circuit outputs a power of 22 W to 50 W to the resonant circuit which is connected to the first output terminal and the second output terminal.
17. The system of claim 15, wherein the oscillator generates the main clock signal at a frequency of 50 kHz to 105 MHz.
18. The system of claim 15, wherein, during a setup phase of operation of the system, the second microchip: measures a length of time taken for the current flowing through the resonant circuit to fall to zero when the first switch and the second switch are turned off and
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16. An apparatus for driving a resonant circuit, wherein the resonant circuit is an LC tank, an antenna or a piezoelectric transducer, the apparatus comprising: a first microchip, wherein the first microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: a first power supply terminal; a second power supply terminal; an H-bridge circuit which incorporates a first switch, a second switch, a third switch and a fourth switch, wherein: the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal is connected electrically between the first switch and the third switch, the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal, and a second output terminal is connected electrically between the second switch and the fourth switch; a first phase terminal which receives a first phase output signal from a pulse width modulation (PWM) signal generator subsystem; a second phase terminal which receives a second phase output signal from the PWM signal generator subsystem; a digital state machine which generates timing signals based on the first phase output signal and the second phase output signal and outputs the timing signals to switches of the H-bridge circuit to control the switches to turn on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit the ultrasonic waves, wherein the sequence comprises a free-float period in which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on in order to dissipate energy stored by the resonant circuit; a current sensor which incorporates: a first current sense resistor which is connected in series between the first switch and the first power supply terminal; a first voltage sensor which measures a voltage drop across the first current sense resistor and provides a first voltage output which is indicative of a current flowing through the first current sense resistor; a second current sense resistor which is connected in series between the second switch and the first power supply terminal; a second voltage sensor which measures the voltage drop across the second current sensor resistor and provides a second voltage output which is indicative of the current flowing through the second current sense resistor; and a current sensor output terminal which provides an rms output voltage relative to ground which is equivalent to the first voltage output and the second voltage
11665483 [17877851]
15. An apparatus for transmitting ultrasonic waves, the apparatus comprising: a resonant circuit, wherein the resonant circuit is at least one of an LC tank, an antenna and a piezoelectric transducer; a first microchip connected to the resonant circuit, wherein the first microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: a first power supply terminal; a second power supply terminal; an H-bridge circuit which incorporates a first switch, a second switch, a third switch and a fourth switch, wherein: the first switch and the third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output terminal is connected electrically between the first switch and the third switch, the first output terminal being connected to a first terminal of the resonant circuit, the second switch and the fourth switch are connected in series between the first power supply terminal and the second power supply terminal, and a second output terminal is connected electrically between the second switch and the fourth switch, the second output terminal being connected to a second terminal of the resonant circuit; a first phase terminal which receives a first phase output signal from a pulse width modulation (PWM) signal generator subsystem; a second phase terminal which receives a second phase output signal from the PWM signal generator subsystem; a digital state machine which generates timing signals based on the first phase output signal and the second phase output signal and outputs the timing signals to switches of the H-bridge circuit to control the switches to turn on and off in a sequence such that the H-bridge circuit outputs an AC drive signal to the resonant circuit to drive the resonant circuit to generate and transmit the ultrasonic waves, wherein the sequence comprises a free-float period in which the first switch and the second switch are turned off and the third switch and the fourth switch are turned on in order to dissipate energy stored by the resonant circuit; a current sensor which incorporates: a first current
sense resistor which is connected in series between the first switch and the first power supply terminal; a first voltage sensor which measures a voltage drop across the first current sense resistor and provides a first voltage output which is indicative of a current flowing through the first current sense resistor; a second current sense resistor which is connected in series between the second switch and the first power supply terminal; a second voltage sensor which measures the voltage drop across the second current sensor resistor and provides a second voltage output which is indicative of the current flowing
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the third switch and the fourth switch are turned on; and sets the length of time of the free-float period to be equal to a measured length of time. (See Claims 19 and 18 in Patents)
19. The microchip of claim 12, wherein the delay locked loop comprises a plurality of delay lines connected end to end, wherein a total delay of the plurality of delay lines is equal to a period of the main clock signal. (See Claim 4 in Patents)
20. The microchip of claim 19, wherein the delay locked loop adjusts the duty cycle of the first phase clock signal and the second phase clock signal in response to the driver control signal by varying a delay of each of the plurality of delay lines in the delay locked loop.
22. (new) A system for transmitting ultrasonic waves, the system comprising: a resonant circuit; a circuit connected to the resonant circuit, wherein the circuit generates an AC drive signal to drive the resonant circuit to generate and transmit ultrasonic waves; a microchip connected to the circuit to control the circuit to generate the AC drive signal, the microchip comprising: an oscillator which generates: a main clock signal, a first phase clock signal, and a second phase clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; a pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, the PWM signal generator subsystem comprising: a delay locked loop which generates a double frequency clock signal being double a frequency of the main clock signal, the delay locked loop controls a rising edge of the first phase clock signal and a rising edge of the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal to drive the circuit to generate an AC drive signal to drive the resonant circuit to generate and transmit the ultrasonic waves; a first output which outputs the first phase output signal to the circuit; and a second output which outputs the second phase output signal to the circuit.
23. The system of claim 22 further comprising a feedback input terminal which receives a feedback signal from an H-bridge circuit.
24. The system of claim 22 further comprising an analogue to digital converter
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output, wherein the rms output voltage is indicative of an rms current flowing through the first switch or the second switch and the current flowing through the resonant circuit which is connected between the first output terminal and the second output terminal; and a second microchip connected to the first microchip to control the H-bridge circuit to generate the AC drive signal, wherein the second microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; the pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, wherein the PWM signal generator subsystem comprises: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first phase clock signal and the second phase clock signal in response to a driver control signal to produce a first phase output signal and a second phase output signal of the two phase centre aligned PWM signal, wherein the first phase output signal and the second phase output signal of the two phase centre aligned PWM signal are configured to drive the H-bridge circuit to generate an AC drive signal to drive the resonant circuit; a first phase output signal
11665483 [17877851]
through the second current sense resistor; and a current sensor output terminal which provides an rms output voltage relative to ground which is equivalent to the first voltage output and the second voltage output, wherein the rms output voltage is indicative of an rms current flowing through the first switch or the second switch and the current flowing through the resonant circuit which is connected between the first output terminal and the second output terminal; and a second microchip connected to the first microchip to control the H-bridge circuit to generate the AC drive signal, wherein the second microchip is a single unit which comprises a plurality of interconnected embedded components and subsystems comprising: an oscillator which generates: a main clock signal, a first phase clock signal which is high for a first time during a positive half-period of the main clock signal and low during a negative half-period of the main clock signal, and a second phase clock signal which is high for a second time during the negative half-period of the main clock signal and low during the positive half-period of the main clock signal, wherein phases of the first phase clock signal and the second phase clock signal are centre aligned; the pulse width modulation (PWM) signal generator subsystem which generates a two phase centre aligned PWM signal, wherein the PWM signal generator subsystem comprises: a delay locked loop which generates a double frequency clock signal using the first phase clock signal and the second phase clock signal, the double frequency clock signal being double a frequency of the main clock signal, wherein the delay locked loop controls a rising edge of the first phase clock signal and the second phase clock signal to be synchronous with a rising edge of the double frequency clock signal, and wherein the delay locked loop adjusts a frequency and a duty cycle of the first
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(ADC) subsystem comprising: a plurality of ADC input terminals which receive a plurality of respective analogue signals, wherein one ADC input terminal of the plurality of ADC input terminals is connected to a feedback input terminal such that the ADC subsystem receives the feedback signal from a H-bridge circuit, and wherein the ADC subsystem samples analogue signals received at the plurality of ADC input terminals at a sampling frequency which is proportional to the frequency of the main clock signal and the ADC subsystem generates ADC digital signals using the sampled analogue signals.
25. The system of claim 24 further comprising a digital processor subsystem which receives the ADC digital signals from the ADC subsystem and processes the ADC digital signals to generate a driver control signal, wherein the digital processor subsystem communicates the driver control signal to the PWM signal generator subsystem to control the PWM signal generator subsystem.
26. The system of claim 22 further comprising a digital to analogue converter (DAC) subsystem comprising: a digital to analogue converter (DAC) which converts a digital control signal generated by the digital processor subsystem into an analogue voltage control signal to control a voltage regulator circuit which generates a voltage for modulation by an H-bridge circuit; and a DAC output terminal which outputs the analogue voltage control signal to control the voltage regulator circuit to generate a predetermined voltage for modulation by the H-bridge circuit to drive a resonant circuit in response to feedback signals which are indicative of an operation of the resonant circuit.
27. A system for transmitting ultrasonic waves, the system comprising: a resonant circuit; a microchip connected to the resonant circuit, the microchip comprising: a first power supply terminal; a second power supply terminal; an H-bridge circuit which incorporates a plurality of switches, wherein: a first switch and a third switch are connected in series between the first power supply terminal and the second power supply terminal; a first output is connected electrically between the first switch and the third switch, a second switch and a fourth switch are connected in series between the first power supply terminal and the second power supply terminal, and a second output is connected electrically between the second switch and the fourth switch; a first phase terminal which receives a first phase output signal from a pulse width modulation (PWM) signal generator subsystem; a second phase terminal which receives a second phase output signal from the PWM signal generator subsystem; a digital state 1653152 [17/877848]
terminal which outputs the first phase output signal to the H-bridge circuit; a second phase output signal terminal which outputs the second phase output signal to the H-bridge circuit; a feedback input termi