DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Arguments
Applicant's arguments regarding the 35 U.S.C. 112a rejections of claims 1-9 have been fully considered and the 35 U.S.C. 112a rejections are withdrawn.
Applicant's arguments regarding the 35 U.S.C. 112b rejections of claims 6-9 have been fully considered and the 35 U.S.C. 112b rejections are withdrawn. However, new 35 U.S.C. 112b rejections of claims 1-20 are made.
Applicant's arguments regarding the non-statutory double patenting rejections of claims 1-20 have been fully considered and some of the non-statutory double patenting rejections are withdrawn.
Applicant's arguments regarding the 35 U.S.C. 103 rejections of claims 1-20 have been fully considered but they are either unpersuasive or are moot in light of the references being applied in the current rejection.
Regarding the 35 U.S.C. 103 rejection, the applicant argues the following in the remarks:
The applied art fails to teach wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command.
The applied art fails to teach wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
Examiner has thoroughly considered Applicant' s arguments, but respectfully finds them unpersuasive for at least the following reasons:
As to point (a), the examiner respectfully disagrees. Tamai recites in Col. 76 lines 42-65 “When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1…as shown in FIG. 60(a-3), the reassignment part 75 registers the present time as the process start time for the I/O request to be processed following the I/O request SSR 1 (step S254); Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75”. After the memory system aborts execution of the command, the memory controller registers a start time of a next I/O request to be processed.
As to point (b), the examiner finds this point moot in light of the references being applied in the current rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1, 10, and 17 (line numbers refer to claim 1):
Lines 13-17 recite “wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system” but it is unclear what “after the memory system aborts” means (Does the memory controller perform one of more operations not associated with the command before the command is resent or after?).
Claims 2-9, 11-16, and 18-20 are dependent claims of claims 1, 10, and 17 and fail to resolve the deficiencies of claim 1, 10, and 17, so they are rejected for the same reasons.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 6-9 and 15-16 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
As per claims 6 and 15 (line numbers refer to claim 6):
Lines 1-3 recite “wherein the memory controller is further configured to resend, after at least a predetermined period of time following the abort signal, the command to the memory system” which is already recited in claim 1.
Claims 7-9 and 16 are dependent claims of claims 6 and 15, respectfully, and fail to resolve the deficiencies of claims 6 and 15, so they are rejected for the same reasons.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11243804 in view of Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), in view of Tamai et al. (US 6799283 B1 hereinafter Tamai), and further in view of Carlson et al. (US 6535935 B1 hereinafter Carlson).
Although the claims at issue are not identical, they are not patentably distinct from each
other.
Regarding claim 1 of the instant application, the following table compares claim 1 with
claim 14 of U.S. Patent No. 11243804. The differences are bolded.
Instant Application
U.S. Patent No. 11243804
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and
a memory controller connectable to a memory system external to the processor;
wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
14. A system, comprising: a processor having: a register configured to store a parameter specifying a time duration; a plurality of execution units configured to execute instructions; and a memory controller; a memory system having multiple components that have different latencies for memory access; and a memory bus coupled between the memory system and the memory controller;
wherein when the processor executes an instruction to load an item, the memory controller sends a command to the memory system to load an item from a memory address;
wherein in response to a determination that the memory system fails to provide, as a response to the command, the item from the memory address to the processor within the time duration, the processor is configured to abort execution of the instruction, and the memory controller is configured to send, over the memory bus, a signal to abort the command; wherein in response to the signal to abort the command, the memory system is configured to change hosting of the memory address in a first component in the multiple components to hosting of the memory address in a second component in the multiple components, wherein the second component has a memory access latency shorter than the first component; and wherein based on the signal to abort the command, the memory system is configured to identify a desired latency for the item, select the second component based on the desired latency, and remap the memory address to the second component.
Although the claims at issue are not identical, they are not patentably distinct from each
other. The U.S. Patent No. 11243804 does not explicitly claim a memory controller connectable to a memory system external to the processor; execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system; wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Euler teaches a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined claims of U.S. Patent No. 11243804 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of U.S. Patent No. 11243804 and Euler fail to teach execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system; wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Kim teaches execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of U.S. Patent No. 11243804 and Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
The claims of U.S. Patent No. 11243804, Euler, and Kim fail to teach wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Tamai teaches wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command (Figs. 32, 55, 58, 59; Col. 76 lines 42-65 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1…as shown in FIG. 60(a-3), the reassignment part 75 registers the present time as the process start time for the I/O request to be processed following the I/O request SSR 1 (step S254); Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of U.S. Patent No. 11243804, Kim, and Euler with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
The claims of U.S. Patent No. 11243804, Kim, Euler, and Tamai fail to teach wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Carlson teaches wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-i; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of U.S. Patent No. 11243804, Euler, Kim, and Tamai with the teachings of Carlson to recover from the abort (see Carlson Col. 6 lines 1-6 After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12124322 (Application No. 17/518,170) in view of Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), in view of Tamai et al. (US 6799283 B1 hereinafter Tamai), and further in view of Carlson et al. (US 6535935 B1 hereinafter Carlson).
Although the claims at issue are not identical, they are not patentably distinct from each
other.
Regarding claim 1 of the instant application, the following table compares claim 1 with
claim 2 of US Patent No. 12124322. The differences are bolded.
Instant Application
US Patent No. 12124322
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register,
sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
1. An apparatus, comprising: a memory array; and
a controller coupled with the memory array and configured to cause the apparatus to:
receive, from a host system, a command to perform an access operation on the memory array; initiate a media management operation that is different than a write operation and is different than a read operation; transmit, to the host system and based at least in part on an elapsed time after receiving the command satisfying a threshold, an indication that the access operation is delayed due to the media management operation; and receive, from the host system based at least in part on the indication, a second command to perform one or more operations associated with the memory array or the media management operation.
2. The apparatus of claim 1, wherein the second command is to abort the access operation, and wherein, to perform the one or more operations, the controller is configured to cause the apparatus to: abort the access operation based at least in part on receiving the second command.
Although the claims at issue are not identical, they are not patentably distinct from each
other. US Patent No. 12124322 does not explicitly claim a processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer, which can be a register, is within a processing unit 112.); a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); the memory controller is configured to send a command to the memory system (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent No. 12124322 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of US Patent No. 12124322 and Euler fail to teach wherein during execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Kim teaches wherein during execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent No. 12124322 and Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
The claims of US Patent No. 12124322, Euler, and Kim fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command (Figs. 32, 55, 58, 59; Col. 76 lines 42-65 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1…as shown in FIG. 60(a-3), the reassignment part 75 registers the present time as the process start time for the I/O request to be processed following the I/O request SSR 1 (step S254); Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent No. 12124322, Euler, and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
The claims of US Patent No. 12124322, Euler, Kim, and Tamai fail to teach wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Carlson teaches wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-i; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of U.S. Patent No. 12124322, Euler, Kim, and Tamai with the teachings of Carlson to recover from the abort (see Carlson Col. 6 lines 1-6 After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent 12468455 in view of Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), in view of Tamai et al. (US 6799283 B1 hereinafter Tamai), and further in view of Carlson et al. (US 6535935 B1 hereinafter Carlson).
Although the claims at issue are not identical, they are not patentably distinct from each
other.
Regarding claim 1 of the instant application, the following table compares claim 1 with
claim 11 of US Patent 12468455. The differences are bolded.
Instant Application
US Patent 12468455
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor;
wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
7. An apparatus, comprising:
an access controller communicatively coupled to a first memory, the access controller further comprising a second memory, wherein the access controller is configured to regulate access of the first memory based on: a number of memory operations performed on the first memory over a particular period of time; and an amount of time taken for performance of one or more memory operations on the first memory; wherein the second memory configured to store data corresponding to one or more host access transactions, and wherein the second memory further comprises: a first flag indicative whether a read access to data corresponding to a respective host access transaction is granted; a second flag indicative whether a write access to data corresponding to the respective host access transaction is granted; a third flag indicative whether a host access to data corresponding to the respective host access transaction is temporarily prevented on a respective location; and a fourth flag indicative whether the host access to the data corresponding to the respective host access transaction is permanently prevented on a respective location.
10. The apparatus of claim 7, wherein the access controller is configured to receive a plurality of memory commands respectively corresponding to a plurality of memory operations that correspond to a host access transaction.
11. The apparatus of claim 10, wherein the access controller further comprises a timer that indicates whether a first particular period of time has passed since a respective memory command of the plurality of commands is received, wherein: the access controller is configured to abort the host access transaction in response to performance of a memory operation corresponding to the respective memory command not being completed within the particular period of time.
Although the claims at issue are not identical, they are not patentably distinct from each
other. US Patent 12468455 does not explicitly claim a processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer, which can be a register, is within a processing unit 112.); a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); the memory controller is configured to send a command to the memory system (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 12468455 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of US Patent 12468455 and Euler fail to teach wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Kim teaches wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 12468455 and Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
The claims of US Patent 12468455, Euler, and Kim fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system, wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command (Figs. 32, 55, 58. 59; Col. 76 lines 42-65 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1…as shown in FIG. 60(a-3), the reassignment part 75 registers the present time as the process start time for the I/O request to be processed following the I/O request SSR 1 (step S254); Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 12468455, Euler, and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
The claims of US Patent 12468455, Euler, Kim, and Tamai fail to teach wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Carlson teaches wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-i; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of U.S. Patent No. 12468455, Euler, Kim, and Tamai with the teachings of Carlson to recover from the abort (see Carlson Col. 6 lines 1-6 After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), in view of Tamai et al. (US 6799283 B1 hereinafter Tamai), and further in view of Carlson et al. (US 6535935 B1 hereinafter Carlson).
Euler, Kim, and Tamai were cited in a prior office action.
As per claim 1, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer, which can be a register, is within a processing unit 112.);
a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and
a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage; As shown in Fig. 2, the journal controller is within the processing unit 112.);
the memory controller is configured to send a command to the memory system (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system);
a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage).
Euler fails to teach wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Kim teaches wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
Euler and Kim fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal; wherein the memory controller is configured to perform one or more operations that are not associated with the command after the memory system aborts execution of the command (Figs. 32, 55, 58, 59; Col. 76 lines 42-65 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1…as shown in FIG. 60(a-3), the reassignment part 75 registers the present time as the process start time for the I/O request to be processed following the I/O request SSR 1 (step S254); Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time T.sub.D Of the I/O request SSR, and, when the delay time T.sub.D exceeds the limit time T.sub.L, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Euler, Kim, and Tamai fail to teach wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system.
However, Carlson teaches wherein the memory controller is configured to, after a predetermined period following the abort signal, resend the command to the memory system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-I; Col. 7 lines 46-47 Thereafter, at time t5 in FIG. 3A, the host bus adapter 27i sends a terminate signal; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, and Tamai with the teachings of Carlson to recover from the abort (see Carlson Col. 6 lines 1-6 After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted.).
As per claim 10, Euler teaches a memory system, comprising: a plurality of memory components having different latencies in data retrieval (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage; Diskette drives and hard-disk drives have different latencies in data retrieval. Diskette drives read and write in the range of kilobytes per second and hard disk drives read and write in the range of megabytes per second.); and
a controller coupled to the plurality of memory components and configured to (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage):
wherein the processor has a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer which can be a register is within a processing unit 112.), and a determination that the memory system fails to respond within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
Euler fails to teach a controller coupled to the plurality of memory components and configured to: receive a command from a processor to load a data item from a memory address; execute the command, and wherein the processor is configured to send a signal to the memory system in response to a determination that the memory system fails to respond to the command within the time duration identified by the register; receive, during execution of the command, the signal; abort, in response to the signal, the execution of the command; perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and after a predetermined period following the signal, resend the command to the memory system.
However, Kim teaches a controller coupled to the plurality of memory components and configured to: receive a command from a processor to load a data item from a memory address; execute the command ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
Euler and Kim fail to teach wherein the processor is configured to send a signal to the memory system in response to a determination that the memory system fails to respond to the command within the time duration identified by the register; receive, during execution of the command, the signal; abort, in response to the signal, the execution of the command; perform one or more operations that are not associated with the command after the memory system aborts execution of the command; and after a predetermined period following the signal, resend the command to the memory system.
However, Tamai teaches wherein the processor is configured to send a signal to the memory system in response to a determination that the memory system fails to respond to the command within the time duration identified by the register; receive, during execution of the command, the signal; and abort, in response to the signal, the execution of the command; perform one or more operations that are not associated with the command after the memory system aborts execution of the command (Fig. 32, 55, 58, 59; Col. 76 lines 42-65 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1…as shown in FIG. 60(a-3), the reassignment part 75 registers the present time as the process start time for the I/O request to be processed following the I/O request SSR 1 (step S254); Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1;).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time T.sub.D Of the I/O request SSR, and, when the delay time T.sub.D exceeds the limit time T.sub.L, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Euler, Kim, and Tamai fail to teach after a predetermined period following the signal, resend the command to the memory system.
However, Carlson teaches after a predetermined period following the signal, resend the command to the memory system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-i; Col. 7 lines 46-47 Thereafter, at time t5 in FIG. 3A, the host bus adapter 27i sends a terminate signal; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, and Tamai with the teachings of Carlson to recover from the abort (see Carlson Col. 6 lines 1-6 After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted.).
As per claim 17, Euler teaches a system, comprising: a processor having: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer which can be a register is within a processing unit 112.); and
a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and
a memory sub-system having: a plurality of memory components having different latencies in data retrieval (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Diskette drives and hard-disk drives have different latencies in data retrieval. Diskette drives read and write in the range of kilobytes per second and hard disk drives read and write in the range of megabytes per second.); and
a controller coupled to the plurality of memory components (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage);
the processor is configured to send a command to the memory sub-system (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage; The journal controller is within the processor (processing unit 112).);
a determination that the memory sub-system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
Euler fails to teach wherein during execution of an instruction in the processor to load a data item from a memory address, the processor is configured to send a command to the memory sub-system; wherein in response to a determination that the memory sub-system fails to respond to the command within the time duration identified by the register, the processor is configured to send a signal to the memory sub-system; and wherein the controller is configured to, in response to the signal, abort execution of the command; wherein the controller is configured to perform one or more operations that are not associated with the command after the memory sub-system aborts execution of the command; and wherein the controller is configured to, after a predetermined period following the signal, resend the command to the memory sub-system.
However, Kim teaches wherein during execution of an instruction in the processor to load a data item from a memory address, the processor is configured to send a command to the memory sub-system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
Euler and Kim fail to teach wherein in response to a determination that the memory sub-system fails to respond to the command within the time duration identified by the register, the processor is configured to send a signal to the memory sub-system; and wherein the controller is configured to, in response to the signal, abort execution of the command; wherein the controller is configured to perform one or more operations that are not associated with the command after the memory sub-system aborts execution of the command; and wherein the controller is configured to, after a predetermined period following the signal, resend the command to the memory sub-system.
However, Tamai teaches wherein in response to a determination that the memory sub-system fails to respond to the command within the time duration identified by the register, the processor is configured to send a signal to the memory sub-system; and wherein the controller is configured to, in response to the signal, abort execution of the command; wherein the controller is configured to perform one or more operations that are not associated with the command after the memory sub-system aborts execution of the command (Fig. 32, 55, 58, 59; Col. 76 lines 42-65 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1…as shown in FIG. 60(a-3), the reassignment part 75 registers the present time as the process start time for the I/O request to be processed following the I/O request SSR 1 (step S254); Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time T.sub.D Of the I/O request SSR, and, when the delay time T.sub.D exceeds the limit time T.sub.L, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Euler, Kim, and Tamai fail to teach wherein the controller is configured to, after a predetermined period following the signal, resend the command to the memory sub-system.
However, Carlson teaches wherein the controller is configured to, after a predetermined period following the signal, resend the command to the memory sub-system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-i; Col. 7 lines 46-47 Thereafter, at time t5 in FIG. 3A, the host bus adapter 27i sends a terminate signal; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, and Tamai with the teachings of Carlson to recover from the abort (see Carlson Col. 6 lines 1-6 After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted.).
Claims 2-6, 9, 11-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, and Carlson, as applied to claims 1, 10, and 17 above, in view of Tanaka et al. (US 5355475 A hereinafter Tanaka).
Tanaka was cited in a previous office action.
As per claim 2, Euler, Kim, Tamai, and Carlson teach the processor of claim 1. Kim teaches wherein the command is configured to request the memory system to retrieve the data item from a memory address ([0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation.).
Additionally, Tamai teaches the memory system is further configured to, in response to the abort signal: identify a latency for retrieval of the data item (Figs. 32, 58; Col. 76 lines 42-48 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b").
Euler, Kim, Tamai, and Carlson fail to teach remap the memory address to store the data item for retrieval according to the latency identified in response to the abort signal.
However, Tanaka teaches remap the memory address to store the data item for retrieval according to the latency identified in response to the abort signal (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, and Carlson with the teachings of Tanaka to efficiently utilize storage (see Tanaka Col. 24 lines 16-17 efficiently utilizing storage units, and improving the file access capability).
As per claim 3, Euler, Kim, Tamai, Carlson, and Tanaka teach the processor of claim 2. Euler teaches wherein the memory system is configured to have a plurality of memory components having different latencies for data retrieval (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Diskette drives and hard-disk drives have different latencies in data retrieval.).
Additionally, Tamai teaches the time duration identified by the register is shorter than a data retrieval latency of at least one of the plurality of memory components (Fig. 5a; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 36 lines 35-36 the controller 7 further includes a reservation table 73 and a second timer 74).
As per claim 4, Euler, Kim, Tamai, Carlson, and Tanaka teach the processor of claim 3. Kim teaches wherein the plurality of memory components include dynamic random access memory, non-volatile random access memory, or flash memory, or any combination thereof ([0102] The first type memory 121 may include a high speed volatile memory (e.g., a dynamic random access memory (DRAM) device); [0102] the second type memory 122 may include at least one of a FLASH memory).
As per claim 5, Euler, Kim, Tamai, Carlson, and Tanaka teach the processor of claim 2. Tanaka teaches wherein prior to the abort signal, the memory address is mapped to a first memory component in the memory system to store the data item; and the abort signal is configured to identify the latency in combination with the command to cause the memory system to identify a second memory component in the memory system to store the data item for the memory address (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 21 lines 7-9 a file relocation is requested according to a used time zone with the program name being as a parameter when starting or terminating the program; Col. 7 lines 29-37 As a result, if the corrected actual execution time exceeds the expecting execution time set by the user, the relocation indicators are calculated for the respective files, where the indicators each include the difference between an expecting execution time and an actual execution time as an element of an execution capability bias factor thereof, in a manner similar to the foregoing step 1. The files are then relocated based on the relocation indicators.).
As per claim 6, Euler, Kim, Tamai, Carlson, and Tanaka teach the processor of claim 5. Carlson teaches wherein the memory controller is further configured to resend, after at least a predetermined period of time following the abort signal, the command to the memory system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-I; Col. 7 lines 46-47 Thereafter, at time t5 in FIG. 3A, the host bus adapter 27i sends a terminate signal; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4).
As per claim 9, Euler, Kim, Tamai, Carlson, and Tanaka teach the processor of claim 6. Carlson teaches wherein the memory controller is further configured to send, after sending the abort signal and before resending the command, a further command to retrieve data from an address different from the memory address (Col. 7 lines 20-23 In response to the MASTER INITIATED READ command at time t2, the data transfer section 23 increases the sliding segment of the data stream 13-1 thru 13-N in the RFIFO 24i; Col. 7 lines 46-48 Thereafter, at time t5 in FIG. 3A, the host bus adapter 27i sends a terminate signal to the data transfer section 23 of the controller 21; Col. 7 lines 57-60 After the terminate signal occurs at time t5, the PCI busses 25-1 thru 25-3 can be used to read data streams from other disks, and to write data streams to other disks. This occurs at time t6 in FIG. 3A; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4.).
As per claim 11, it is a memory system claim of claim 2, so it is rejected for the same reasons.
As per claim 12, it is a memory system claim of claim 3, so it is rejected for the same reasons.
As per claim 13, it is a memory system claim of claim 4, so it is rejected for the same reasons.
As per claim 14, Euler, Kim, Tamai, Carlson, and Tanaka teach the memory system of claim 11. Tamai teaches the controller is configured to identify the latency based on a time gap between the signal and the command (Figs. 32, 58; Col. 76 lines 42-48 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b").
Additionally, Tanaka teaches wherein prior to the signal, the memory address is mapped to a first memory component, among the plurality of memory components, in the memory system to store the data item; and identify a second memory component, among the plurality of memory components, to store the data item for the memory address (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 7 lines 29-37 As a result, if the corrected actual execution time exceeds the expecting execution time set by the user, the relocation indicators are calculated for the respective files, where the indicators each include the difference between an expecting execution time and an actual execution time as an element of an execution capability bias factor thereof, in a manner similar to the foregoing step 1. The files are then relocated based on the relocation indicators.).
As per claim 15, Euler, Kim, Tamai, Carlson, and Tanaka teach the memory system of claim 14. Carlson teaches wherein the processor is further configured to resend, after at least a predetermined period of time following the signal, the command to the memory system (Col. 5 lines 22-26 In response to the MASTER INITIATED READ command of step S6, the data transfer section 23 of the controller 21 performs S7. There, the data transfer section 23 writes a sliding segment of one data stream 13-1 thru 13-N into one RFIFO 24i; Col. 5 line 60-Col. 6 line 36 In step S9, the data transfer section 23 of the controller 21 sends a TERMINATE signal on the PCI bus 25-1 to the host bus adapter 27-i. This TERMINATE signal can be sent at any time during step S7. When step S9 is performed, the data transfer section 23 stops writing the sliding segment of data into the RFIFO 24i, and it stops sending a subsegment of the sliding segment from the RFIFO 24i to the host bus adapter 27-i. After the sending of the TERMINATE signal in step S8 and/or step S9, the PCI buses 25-1 thru 25-3 can be used for any purpose, such as writing other data streams to other disks. Then, at some later time, the WRITE-TO-DISK instruction which uses the particular RFIFO 24i to write the particular data stream 13-1 thru 13-N, can be restarted. To do that, the host bus adapter 27-i sends another MASTER INITIATED READ command which references the data stream 13-1 thru 13-N. This occurs in step S10 of FIG. 2B wherein the MASTER INITIATED READ command includes a PCI BUS READ ADDRESS 41. There, item 8 and item 2 are concatenated together along with a modified item 7, which is shown in FIG. 2B as item 7*. Item 2 is the reference to the one particular data stream 13-1 thru 13-N that was already partially stored in the one particular RFIFO 24i and was partially sent to the host bus adapter 27-i. Item 7* is an update of the phony starting address in the memory 11 of the data stream 13-1 thru 13-N. To generate the updated phony address in item 7*, the host bus adapter 27-i increases by one the phony starting address of item 7 each time it actually receives a byte of the subsegment of the data stream 13-1 thru 13-N that is sent in step S7. Thus, the phony address in item 7* is equivalent to a count of the number of bytes in the data stream 13-1 thru 13-N which have actually passed thru the buffer 26a and have been received by the host bus adapter 27-i. Next, in response to MASTER INITIATED READ command of step S10, the data transfer section 23 of the controller 21 performs step S7. There the data transfer section 23 of the controller 21 uses item 7* to determine the location in the RFIFO 24i of the data byte that was last received by the host bus adapter 27-i. After that determination is made, the data transfer section 23 of the controller 21 continues to write additional portions of the sliding segment of data stream 13-1 thru 13-N into the RFIFO 24i; and concurrently, it continues to send a subsegment of the sliding segment from the RFIFO 24i through the bridge 26-1 to the host bus adapter 27-i; Col. 7 lines 46-47 Thereafter, at time t5 in FIG. 3A, the host bus adapter 27i sends a terminate signal; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4; Col.3 lines 42-47 Component 20 is an I/O processor which is directed by the instruction processor 10 to execute multiple WRITE-TO-DISK instructions. Included within the I/O processor 20 are several other components 21, 22 . . . 27-M which are shown in FIG. 1. All of those components interact to execute each WRITE-TO-DISK instruction 12. Component 21 is a controller).
Additionally, Tanaka teaches the controller is configured to relocate the data item from the first memory component to the second memory component within the predetermined period of time (Col. 6 lines 8-19 In the present invention, an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy such that an estimated execution time for a job is limited within an expecting execution time; Col. 11 line 12 storage unit is connected with its control unit; Col. 2 lines 16-18 relocate files within a relocation allowable time so as to satisfy an execution time expected by a user).
As per claim 18, Euler, Kim, Tamai, and Carlson teach the system of claim 17. Euler teaches wherein the plurality of memory components includes a first memory component having a first data retrieval latency and a second memory component having a second data retrieval latency shorter than the first data retrieval latency (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Diskette drives and hard-disk drives have different latencies in data retrieval. Diskette drives read and write in the range of kilobytes per second and hard disk drives read and write in the range of megabytes per second.).
Euler, Kim, Tamai, and Carlson fail to teach the controller is configured to relocate the data item for the memory address from the first memory component to the second memory component.
However, Tanaka teaches the controller is configured to relocate the data item for the memory address from the first memory component to the second memory component (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 24, line 26 Access loads among storage units; Col. 4 lines 4042 a plurality of storage units having different access capabilities; Col. 5 lines 27-28 a storage unit having high speed access capability; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 10 lines 65-66 designation of a control unit).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, and Carlson with the teachings of Tanaka to efficiently utilize storage (see Tanaka Col. 24 lines 16-17 efficiently utilizing storage units, and improving the file access capability).
As per claim 19, Euler, Kim, Tamai, Carlson, and Tanaka teach the system of claim 18. Tamai teaches wherein the controller is further configured to: identify a desired data retrieval latency for the data item based on a time gap between the command and the signal (Figs. 32, 58; Col. 76 lines 42-48 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT;).
Additionally, Tanaka teaches select, based on the desired data retrieval latency for the data item, the second memory component, from the plurality of memory components to relocate the data item (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 7 lines 29-37 As a result, if the corrected actual execution time exceeds the expecting execution time set by the user, the relocation indicators are calculated for the respective files, where the indicators each include the difference between an expecting execution time and an actual execution time as an element of an execution capability bias factor thereof, in a manner similar to the foregoing step 1. The files are then relocated based on the relocation indicators.).
As per claim 20, Euler, Kim, Tamai, and Tanaka teach the system of claim 19. Kim teaches wherein the plurality of memory components include dynamic random access memory, non-volatile random access memory, or flash memory, or any combination thereof ([0102] The first type memory 121 may include a high speed volatile memory (e.g., a dynamic random access memory (DRAM) device); [0102] the second type memory 122 may include at least one of a FLASH memory).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, Carlson, and Tanaka, as applied to claim 6 above, in view of Oe et al. (US 20140297971 A1 hereinafter Oe).
Oe was cited in a previous office action.
As per claim 7, Euler, Kim, Tamai, Carlson, and Tanaka teach the processor of claim 6.
Euler, Kim, Tamai, Carlson, and Tanaka fail to teach wherein the predetermined period of time is configured to be longer than a time period for the memory system to remap the memory address from the first memory component to the second memory component.
However, Oe teaches wherein the predetermined period of time is configured to be longer than a time period for the memory system to remap the memory address from the first memory component to the second memory component (claim 5 wherein the moving moves, among movement areas having the rate continuously exceeding the second threshold for the predetermined number of times, data of a movement area in which number of inputs and outputs is expected to exceed the first threshold for a time longer than a time for moving data to the second storage device, to the second storage device.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Carlson, and Tanaka with the teachings of Oe to reduce latency (see Oe [0097] can appropriately select a neighborhood of a high load area and move data from the HDD 300 to the SSD 200, thereby being capable of accessing the HDD 300 at a high speed.).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, Carlson, and Tanaka, as applied to claim 6 above, in view of Choi (US 20200065240 A1) and further in view of Arashi et al. (US 20050249060 A1 hereinafter Arashi).
Choi and Arashi were cited in a previous office action.
As per claim 8, Euler, Kim, Tamai, Carlson, and Tanaka teach the processor of claim 6.
Euler, Kim, Tamai, Carlson, and Tanaka fail to teach wherein the memory controller is further configured to: free a resource associated with the command after sending the abort signal; and perform an operation using the resource between sending the abort signal and resending the command.
However, Choi teaches wherein the memory controller is further configured to: free a resource associated with the command after sending the abort signal ([0008] The controller may further: check whether the first transaction is committed or aborted, for the first write data stored in the first write buffer; perform a first write operation of storing the first write data stored in the first write buffer in the nonvolatile memory device by performing a first flush operation for the first write buffer, in the case where the first transaction is checked as being committed, and then releases the first write buffer in the volatile memory, and release the first write buffer in the volatile memory in the case where the first transaction is checked as being aborted.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Carlson, and Tanaka with the teachings of Choi to effectively manage transactions (see Choi [0027] effectively manage transaction write data).
Euler, Kim, Tamai, Carlson, Tanaka, and Choi fail to teach perform an operation using the resource between sending the abort signal and resending the command.
However, Arashi teaches perform an operation using the resource between sending the abort signal and resending the command ([0008] the control unit performs seek action control from a retry address which precedes an address at which an error is detected by a predetermined amount when a readout error detection signal is inputted from the information readout unit at the time of reading out the information on the optical disk, and subsequently performs seek action control from an address which is different from the previous retry address and precedes the address at which the error is detected when the readout error detection signal for the same address is inputted; [0009] In this configuration, when a readout error detection signal is inputted at the time of seek action control, a control unit performs first retry seek action control for performing readout from an address which precedes an address (hereinafter called "an error initial detection address") at which a readout error is detected by a predetermined amount. An information readout unit sequentially reads out information from an address specified by this first retry seek action control to the error initial detection address. Then, when the error detection signal is again inputted at the error initial detection address at the time of this first retry seek action control, the control unit performs second retry seek action control for performing readout from an address which precedes the error initial detection address unlike the address specified by the first retry seek action control. Then, the control unit performs the above retry seek action control over predetermined times or until information on the error initial detection address can be read out.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Carlson, Tanaka, and Choi with the teachings of Arashi to reduce time needed to retry reading (see Arashi [0019] Also, according to the invention, by sequentially performing specification from an address near to the address at which an error is detected at the time of a retry seek action, the effect described above is obtained and also, time necessary to perform a retry reading action can be reduced.).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, Carlson, and Tanaka, as applied to claim 15 above, and further in view of Fugini et al. (US 9823968 B1 hereinafter Fugini).
Fugini was cited in a previous office action.
As per claim 16, Euler, Kim, Tamai, Carlson, and Tanaka teach the memory system of claim 15. Carlson teaches wherein the processor is further configured to send, after sending the signal and before resending the command, a further command to retrieve data from an address different from the memory address (Col. 7 lines 20-23 In response to the MASTER INITIATED READ command at time t2, the data transfer section 23 increases the sliding segment of the data stream 13-1 thru 13-N in the RFIFO 24i; Col. 7 lines 46-48 Thereafter, at time t5 in FIG. 3A, the host bus adapter 27i sends a terminate signal to the data transfer section 23 of the controller 21; Col. 7 lines 57-60 After the terminate signal occurs at time t5, the PCI busses 25-1 thru 25-3 can be used to read data streams from other disks, and to write data streams to other disks. This occurs at time t6 in FIG. 3A; Col. 7 line 62-Col. 8 line 2 Subsequently, at time t7 in FIG. 3B, the WRITE-TO-DISK instruction which was being executed at times t3-t4 is restarted. To do that, the host bus adapter 27i sends another MASTER INITIATED READ command with a PCI BUS READ ADDRESS in which item 2 equals R1. That causes the data transfer section 23 of the controller 21 to select the particular data stream 13-1 thru 13-N that was being transferred at times t3-t4; Col. 3 lines 44-45 Included within the I/O processor 20 are several other components 21).
Additionally, Tanaka teaches relocation of the data item from the first memory component to the second memory component (Col. 6 lines 8-19 In the present invention, an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy such that an estimated execution time for a job is limited within an expecting execution time; Col. 11 line 12 storage unit is connected with its control unit; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit).
Euler, Kim, Tamai, Carlson, and Tanaka fail to teach the controller is configured to execute the further command in parallel with relocation of the data item from the first memory component to the second memory component.
However, Fugini teaches the controller is configured to execute the further command in parallel with relocation of the data item from the first memory component to the second memory component (Col. 14 lines 37-40 The Write Data Multiplexer 56 facilitates data migration between the plurality of the Controller Blocks 54 and the Memory Unit 60 by coordinating parallel reading, writing and processing data in different controller blocks 54.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Carlson, and Tanaka with the teachings of Fugini to provide error protection (see Fugini Col. 10 lines 64-65 error protection is provided in the subject method).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSING CHUN LIN whose telephone number is (571)272-8522. The examiner can normally be reached Mon - Fri 9AM-5PM.
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/H.L./Examiner, Art Unit 2195
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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