DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Arguments
Applicant's arguments regarding the non-statutory double patenting rejections of claims 1-20 have been fully considered but are moot in light of the references being applied in the current rejection
Applicant's arguments regarding the 35 U.S.C. 103 rejections of claims 1-20 have been fully considered but are moot in light of the references being applied in the current rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claim 1:
Lines 11-12 recite “wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed” but this is not supported by the specification. As shown in Figure 3, after a command is aborted, the command is resent to be completed. See the description of Figure 3 in [0037-0038] “For example, the aborted command is a first command for retrieving data from a first memory address. At block 307, the processor 100 can optionally send a second command to the memory system to load a second item from a second memory address that is different from the first memory address. In this way, the processor can process other operations (e.g., the second command) instead of having to wait for the completion of the load operation on the low speed memory (e.g., the first command). At block 309, the processor 100 can resend the command to the memory system to load the item from the memory address after at least a predetermined period of time following the signal to abort the command”. Therefore, the specification does not support that the command is never executed.
Claims 2-9 are dependent claims of claim 1 and fail to resolve the deficiencies of claim 1, so they are rejected for the same reasons.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 6:
Lines 2-3 recite “resend, after at least a predetermined period of time following the abort signal, the command to the memory system”, but claim 1 recites that the command is never executed. Therefore, it is unclear why the command is resent to the memory system if the command is never executed.
Claims 7-9 are dependent claims of claim 6 and fail to resolve the deficiencies of claim 6, so they are rejected for the same reasons.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11199995 in view of Euler et al. (US 6052696 A hereinafter Euler) and in view of Tamai et al. (US 6799283 B1 hereinafter Tamai).
Although the claims at issue are not identical, they are not patentably distinct from each
other.
Regarding claim 1 of the instant application, the following table compares claim 1 with
claim 15 of U.S. Patent No. 11199995. The differences are bolded.
Instant Application
U.S. Patent No. 11199995
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
15. A memory system, comprising: one or more processors; and a non-transitory computer-readable medium including one or more sequences of instructions that, when executed by the one or more processors, causes: receiving, by the memory system coupled to a processor via a memory bus, a load command responsive to a load instruction from the processor, the load instruction identifying a logical memory address in a logical address space, a register storing a parameter specifying a time duration, the load command generated from combining the load instruction and the parameter in the register during translation from the logical memory address into a physical memory address in a physical address space to load an item from the physical memory address, the load command including the parameter specifying the time duration; determining, by the memory system, whether providing the item from the physical memory address to the processor takes within the time duration; and providing, by the memory system, a response to the processor within the time duration in response to a determination that providing the item from the physical memory address to the processor takes longer than the time duration.
Although the claims at issue are not identical, they are not patentably distinct from each
other. U.S. Patent No. 11199995 does not explicitly claim a processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and aborts execution of the command in response to the abort signal such that the command is never executed.
However, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer, which can be a register, is within a processing unit 112.);
a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and
a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage);
the memory controller is configured to send a command to the memory system (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage);
a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined claims of U.S. Patent No. 11199995 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of U.S. Patent No. 11199995 and Euler fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and aborts execution of the command in response to the abort signal such that the command is never executed.
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and aborts execution of the command in response to the abort signal such that the command is never executed (Figs. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined claims of U.S. Patent No. 11199995 and Euler with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11243804 in view of Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), and in view of Tamai et al. (US 6799283 B1 hereinafter Tamai).
Although the claims at issue are not identical, they are not patentably distinct from each
other.
Regarding claim 1 of the instant application, the following table compares claim 1 with
claim 14 of U.S. Patent No. 11243804. The differences are bolded.
Instant Application
U.S. Patent No. 11243804
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and
a memory controller connectable to a memory system external to the processor;
wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
14. A system, comprising: a processor having: a register configured to store a parameter specifying a time duration; a plurality of execution units configured to execute instructions; and a memory controller; a memory system having multiple components that have different latencies for memory access; and a memory bus coupled between the memory system and the memory controller;
wherein when the processor executes an instruction to load an item, the memory controller sends a command to the memory system to load an item from a memory address;
wherein in response to a determination that the memory system fails to provide, as a response to the command, the item from the memory address to the processor within the time duration, the processor is configured to abort execution of the instruction, and the memory controller is configured to send, over the memory bus, a signal to abort the command; wherein in response to the signal to abort the command, the memory system is configured to change hosting of the memory address in a first component in the multiple components to hosting of the memory address in a second component in the multiple components, wherein the second component has a memory access latency shorter than the first component; and wherein based on the signal to abort the command, the memory system is configured to identify a desired latency for the item, select the second component based on the desired latency, and remap the memory address to the second component.
Although the claims at issue are not identical, they are not patentably distinct from each
other. The U.S. Patent No. 11243804 does not explicitly claim a memory controller connectable to a memory system external to the processor; execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system; wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Euler teaches a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined claims of U.S. Patent No. 11243804 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of U.S. Patent No. 11243804 and Euler fail to teach execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system; wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Kim teaches execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of U.S. Patent No. 11243804 and Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
The claims of U.S. Patent No. 11243804, Euler, and Kim fail to teach wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Tamai teaches wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed (Figs. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of U.S. Patent No. 11243804, Kim, and Euler with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent 11687282 in view of Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), and in view of Tamai et al. (US 6799283 B1 hereinafter Tamai).
Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 1 of the instant application, the following table compares claim 1 with claim 4 of US Patent 11687282. The differences are bolded.
Instant Application
US Patent 11687282
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor;
wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
1. An apparatus, comprising: a host interface of a memory module operable on a memory bus to receive a load command from a central processing unit, the load command specifying a memory address and a requested time duration for responding to the load command; a plurality of memory devices having different latencies in accessing data stored in the memory devices; and a controller coupled to the host interface and the memory devices, wherein the controller is configured to, in response to the load command, at least: identify a memory device, among the plurality of memory devices, that currently stores an item at the memory address; and determine whether a latency of the memory device is sufficient to retrieve the item from the memory device as a response to the load command within the requested time duration.
4. The apparatus of claim 1, wherein the controller is configured to, in response to a determination that the latency of the memory device is insufficient to retrieve the item from the memory device within the requested time duration, provide the response to the load command within the requested time duration; and the response is configured to indicate that the item is not available within the time duration.
Although the claims at issue are not identical, they are not patentably distinct from each
other. The US Patent 11687282 does not explicitly claim a processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer which can be a register is within a processing unit 112.); a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 11687282 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of US Patent 11687282 and Euler fail to teach wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Kim teaches wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 11687282 and Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
The claims of US Patent 11687282, Kim, and Euler fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed (Figs. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined claims of US Patent 11687282, Euler, and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent No. 12124322 (Application No. 17/518,170) in view of Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), and in view of Tamai et al. (US 6799283 B1 hereinafter Tamai).
Although the claims at issue are not identical, they are not patentably distinct from each
other.
Regarding claim 1 of the instant application, the following table compares claim 1 with
claim 2 of US Patent No. 12124322. The differences are bolded.
Instant Application
US Patent No. 12124322
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register,
sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
1. An apparatus, comprising: a memory array; and
a controller coupled with the memory array and configured to cause the apparatus to:
receive, from a host system, a command to perform an access operation on the memory array; initiate a media management operation that is different than a write operation and is different than a read operation; transmit, to the host system and based at least in part on an elapsed time after receiving the command satisfying a threshold, an indication that the access operation is delayed due to the media management operation; and receive, from the host system based at least in part on the indication, a second command to perform one or more operations associated with the memory array or the media management operation.
2. The apparatus of claim 1, wherein the second command is to abort the access operation, and wherein, to perform the one or more operations, the controller is configured to cause the apparatus to: abort the access operation based at least in part on receiving the second command.
Although the claims at issue are not identical, they are not patentably distinct from each
other. US Patent No. 12124322 does not explicitly claim a processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer, which can be a register, is within a processing unit 112.); a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); the memory controller is configured to send a command to the memory system (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent No. 12124322 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of US Patent No. 12124322 and Euler fail to teach wherein during execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Kim teaches wherein during execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent No. 12124322 and Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
The claims of US Patent No. 12124322, Euler, and Kim fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed (Figs. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent No. 12124322, Euler, and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of US Patent 12468455 in view of Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), and in view of Tamai et al. (US 6799283 B1 hereinafter Tamai).
Although the claims at issue are not identical, they are not patentably distinct from each
other.
Regarding claim 1 of the instant application, the following table compares claim 1 with
claim 11 of US Patent 12468455. The differences are bolded.
Instant Application
US Patent 12468455
1. A processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor;
wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system;
wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
7. An apparatus, comprising:
an access controller communicatively coupled to a first memory, the access controller further comprising a second memory, wherein the access controller is configured to regulate access of the first memory based on: a number of memory operations performed on the first memory over a particular period of time; and an amount of time taken for performance of one or more memory operations on the first memory; wherein the second memory configured to store data corresponding to one or more host access transactions, and wherein the second memory further comprises: a first flag indicative whether a read access to data corresponding to a respective host access transaction is granted; a second flag indicative whether a write access to data corresponding to the respective host access transaction is granted; a third flag indicative whether a host access to data corresponding to the respective host access transaction is temporarily prevented on a respective location; and a fourth flag indicative whether the host access to the data corresponding to the respective host access transaction is permanently prevented on a respective location.
10. The apparatus of claim 7, wherein the access controller is configured to receive a plurality of memory commands respectively corresponding to a plurality of memory operations that correspond to a host access transaction.
11. The apparatus of claim 10, wherein the access controller further comprises a timer that indicates whether a first particular period of time has passed since a respective memory command of the plurality of commands is received, wherein: the access controller is configured to abort the host access transaction in response to performance of a memory operation corresponding to the respective memory command not being completed within the particular period of time.
Although the claims at issue are not identical, they are not patentably distinct from each
other. US Patent 12468455 does not explicitly claim a processor, comprising: a register operable to store a parameter representative of a time duration; a plurality of execution units; and a memory controller connectable to a memory system external to the processor; wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer, which can be a register, is within a processing unit 112.); a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); the memory controller is configured to send a command to the memory system (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage); a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 12468455 with the teachings of Euler to improve performance (see Euler Abstract A method and system of journal bundling that provides improved performance.).
The claims of US Patent 12468455 and Euler fail to teach wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory aborts execution of the command in response to the abort signal such that the command is never executed.
However, Kim teaches wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 12468455 and Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
The claims of US Patent 12468455, Euler, and Kim fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system, wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed (Figs. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the claims of US Patent 12468455, Euler, and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Similar claim mappings of the remaining claims would have been obvious to a person
having ordinary skill in the art but have been omitted for the sake of brevity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Euler et al. (US 6052696 A hereinafter Euler), in view of Kim et al. (US 20190303226 A1 hereinafter Kim), and further in view of Tamai et al. (US 6799283 B1 hereinafter Tamai).
Euler and Kim were cited in a prior office action.
As per claim 1, Euler teaches a processor, comprising: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer, which can be a register, is within a processing unit 112.);
a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and
a memory controller connectable to a memory system external to the processor (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage; As shown in Fig. 2, the journal controller is within the processing unit 112.);
the memory controller is configured to send a command to the memory system (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system);
a determination that the memory system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage).
Euler fails to teach wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system; wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Kim teaches wherein upon execution of a non-transitory computer-readable instruction in the processor to load a data item from the memory system, the memory controller is configured to send a command to the memory system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312; [0194] The processor 210 may include a memory controller 211 and a cache memory 212. The memory controller 211 may access the first to fourth memory modules 220 to 250 through main channels MCH and sub-channels SCH. The cache memory 212 may include a high-speed memory such as a static random access memory (SRAM); SRAM is a type of non-transitory computer-readable medium that can store instructions.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
Euler and Kim fail to teach wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed.
However, Tamai teaches wherein the memory controller, in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, sends an abort signal to the memory system; and wherein the memory system aborts execution of the command in response to the abort signal such that the command is never executed (Figs. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1; Col. 27 lines 27-40 Therefore, as shown in FIG. 5a, the disk array device of the present invention forcefully terminates reading from the disk drive 5D immediately after the time t1…As described above, the disk array device of the present invention terminates incomplete reading of the disk drive, allowing the disk drive to start another reading in short order without continuing unnecessary reading; Col. 6 lines 51-55 in the second aspect, also when reading of one disk drive takes too much time, this reading is terminated. Therefore, it is possible to provide the disk array device in which, if reading of one disk drive is delayed, this delay does not affect other reading.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time T.sub.D Of the I/O request SSR, and, when the delay time T.sub.D exceeds the limit time T.sub.L, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
As per claim 10, Euler teaches a memory system, comprising: a plurality of memory components having different latencies in data retrieval (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage; Diskette drives and hard-disk drives have different latencies in data retrieval. Diskette drives read and write in the range of kilobytes per second and hard disk drives read and write in the range of megabytes per second.); and
a controller coupled to the plurality of memory components and configured to (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage):
wherein the processor has a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer which can be a register is within a processing unit 112.), and a determination that the memory system fails to respond within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
Euler fails to teach a controller coupled to the plurality of memory components and configured to: receive a command from a processor to load a data item from a memory address; execute the command, and wherein the processor is configured to send a signal to the memory system in response to a determination that the memory system fails to respond to the command within the time duration identified by the register; receive, during execution of the command, the signal; and abort, in response to the signal, the execution of the command.
However, Kim teaches a controller coupled to the plurality of memory components and configured to: receive a command from a processor to load a data item from a memory address; execute the command ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
Euler and Kim fail to teach wherein the processor is configured to send a signal to the memory system in response to a determination that the memory system fails to respond to the command within the time duration identified by the register; receive, during execution of the command, the signal; and abort, in response to the signal, the execution of the command.
However, Tamai teaches wherein the processor is configured to send a signal to the memory system in response to a determination that the memory system fails to respond to the command within the time duration identified by the register; receive, during execution of the command, the signal; and abort, in response to the signal, the execution of the command (Fig. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1;).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time T.sub.D Of the I/O request SSR, and, when the delay time T.sub.D exceeds the limit time T.sub.L, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
As per claim 17, Euler teaches a system, comprising: a processor having: a register operable to store a parameter representative of a time duration (Fig. 2; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 5 lines 14-19 Referring to FIG. 2, there is depicted a block diagram of the principal components of processing unit 112 attached via network 160 to remote computer system 188. CPU (central processing unit) 226 is connected via system bus 234 to RAM (Random Access Memory) 258, diskette drive 122, hard-disk drive 123, tape drive 124, timer 225; As shown in Fig. 2, a timer which can be a register is within a processing unit 112.); and
a plurality of execution units (Col. 5 lines 23-24 Processing unit 112 includes central processing unit (CPU) 226; Col. 5 lines 42-45 Although processing unit 112 is shown to contain only a single CPU and a single system bus, the present invention applies equally to computer systems that have multiple CPUs); and
a memory sub-system having: a plurality of memory components having different latencies in data retrieval (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Diskette drives and hard-disk drives have different latencies in data retrieval. Diskette drives read and write in the range of kilobytes per second and hard disk drives read and write in the range of megabytes per second.); and
a controller coupled to the plurality of memory components (Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage);
the processor is configured to send a command to the memory sub-system (Fig. 2; Col. 3 lines 48-49 a journal controller for writing onto non-volatile storage or to a remote computer system; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage; The journal controller is within the processor (processing unit 112).);
a determination that the memory sub-system fails to respond to the command within the time duration identified by the register (Col. 9 lines 15-17 Control then continues to block 475 where journal controller 299 waits until either the timer timed out or a bundle write-operation completed; Col. 6 lines 7-9 Timer 225 can be a register, such as a clock register or a time register. Setting a timer places a value in the register; Col. 2 lines 44-45 starts a timer to expire at a predetermined maximum time-to-wait; Col. 3 lines 59-60 writes journal records in a bundle to non-volatile storage; Col. 5 lines 5-7 Remote computer system 188 can be implemented utilizing any suitable computer that contains non-volatile storage).
Euler fails to teach wherein during execution of an instruction in the processor to load a data item from a memory address, the processor is configured to send a command to the memory sub-system; wherein in response to a determination that the memory sub-system fails to respond to the command within the time duration identified by the register, the processor is configured to send a signal to the memory sub-system; and wherein the controller is configured to, in response to the signal, abort execution of the command.
However, Kim teaches wherein during execution of an instruction in the processor to load a data item from a memory address, the processor is configured to send a command to the memory sub-system ([0335] The memory controller 311 may receive an access command, which is based on the virtual addresses VA, from the processor 310. The memory controller 311 may convert the virtual addresses VA into actual addresses of the first to fourth memory modules 320 to 350. The memory controller 311 may access the first to fourth memory modules 320 to 350 through the main channels MCH, based on the actual addresses; [0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation; [0296] The processor 310 may include a memory controller 311; [0305] the processor 310 may map or fetch a specific storage space of the first to fourth memory modules 320 to 350 to the cache memory 312.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler with the teachings of Kim to improve performance (see Kim [0293] a memory system having improved performance by applying characteristics of the storage class memory and an operating method of the memory system are provided.).
Euler and Kim fail to teach wherein in response to a determination that the memory sub-system fails to respond to the command within the time duration identified by the register, the processor is configured to send a signal to the memory sub-system; and wherein the controller is configured to, in response to the signal, abort execution of the command.
However, Tamai teaches wherein in response to a determination that the memory sub-system fails to respond to the command within the time duration identified by the register, the processor is configured to send a signal to the memory sub-system; and wherein the controller is configured to, in response to the signal, abort execution of the command (Fig. 32, 55, 58; Col. 76 lines 42-56 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1…After step S252, the reassignment part 75 checks whether another I/O request SSR waits to be processed in the disk drive 62 which has terminated execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 34 lines 2-3 the controller 7 calculates a timeout value VTO1 to which a first timer 72 is to be set; Col. 34 lines 43-46 This time t0 is hereinafter referred to as a completion-expectation value t0. The controller 7 previously stores the completion-expectation value t0 for calculating the timeout value VTO1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler and Kim with the teachings of Tamai to avoid affecting processing of other commands (see Tamai Col. 81 lines 45-50 Therefore, the reassignment part 75 monitors the delay time T.sub.D Of the I/O request SSR, and, when the delay time T.sub.D exceeds the limit time T.sub.L, terminates execution of processing of the I/O request SSR. Thus, even if processing of one I/O request is delayed, such delay does not affect processing of the following I/O requests SSR.).
Claims 2-5, 11-14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, and Tamai, as applied to claims 1, 10, and 17 above, in view of Tanaka et al. (US 5355475 A hereinafter Tanaka).
Tanaka was cited in a previous office action.
As per claim 2, Euler, Kim, and Tamai teach the processor of claim 1. Kim teaches wherein the command is configured to request the memory system to retrieve the data item from a memory address ([0384] For example, the memory controller 311 may transmit a read command and a read address to the first memory module 320 to request a read operation.).
Additionally, Tamai teaches the memory system is further configured to, in response to the abort signal: identify a latency for retrieval of the data item (Figs. 32, 58; Col. 76 lines 42-48 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b").
Euler, Kim, and Tamai fail to teach remap the memory address to store the data item for retrieval according to the latency identified in response to the abort signal.
However, Tanaka teaches remap the memory address to store the data item for retrieval according to the latency identified in response to the abort signal (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, and Tamai with the teachings of Tanaka to efficiently utilize storage (see Tanaka Col. 24 lines 16-17 efficiently utilizing storage units, and improving the file access capability).
As per claim 3, Euler, Kim, Tamai, and Tanaka teach the processor of claim 2. Euler teaches wherein the memory system is configured to have a plurality of memory components having different latencies for data retrieval (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Diskette drives and hard-disk drives have different latencies in data retrieval.).
Additionally, Tamai teaches the time duration identified by the register is shorter than a data retrieval latency of at least one of the plurality of memory components (Fig. 5a; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT; Col. 36 lines 35-36 the controller 7 further includes a reservation table 73 and a second timer 74).
As per claim 4, Euler, Kim, Tamai, and Tanaka teach the processor of claim 3. Kim teaches wherein the plurality of memory components include dynamic random access memory, non-volatile random access memory, or flash memory, or any combination thereof ([0102] The first type memory 121 may include a high speed volatile memory (e.g., a dynamic random access memory (DRAM) device); [0102] the second type memory 122 may include at least one of a FLASH memory).
As per claim 5, Euler, Kim, Tamai, and Tanaka teach the processor of claim 2. Tanaka teaches wherein prior to the abort signal, the memory address is mapped to a first memory component in the memory system to store the data item; and the abort signal is configured to identify the latency in combination with the command to cause the memory system to identify a second memory component in the memory system to store the data item for the memory address (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 21 lines 7-9 a file relocation is requested according to a used time zone with the program name being as a parameter when starting or terminating the program; Col. 7 lines 29-37 As a result, if the corrected actual execution time exceeds the expecting execution time set by the user, the relocation indicators are calculated for the respective files, where the indicators each include the difference between an expecting execution time and an actual execution time as an element of an execution capability bias factor thereof, in a manner similar to the foregoing step 1. The files are then relocated based on the relocation indicators.).
As per claim 11, it is a memory system claim of claim 2, so it is rejected for the same reasons.
As per claim 12, it is a memory system claim of claim 3, so it is rejected for the same reasons.
As per claim 13, it is a memory system claim of claim 4, so it is rejected for the same reasons.
As per claim 14, Euler, Kim, Tamai, and Tanaka teach the memory system of claim 11. Tamai teaches the controller is configured to identify the latency based on a time gap between the signal and the command (Figs. 32, 58; Col. 76 lines 42-48 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b").
Additionally, Tanaka teaches wherein prior to the signal, the memory address is mapped to a first memory component, among the plurality of memory components, in the memory system to store the data item; and identify a second memory component, among the plurality of memory components, to store the data item for the memory address (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 7 lines 29-37 As a result, if the corrected actual execution time exceeds the expecting execution time set by the user, the relocation indicators are calculated for the respective files, where the indicators each include the difference between an expecting execution time and an actual execution time as an element of an execution capability bias factor thereof, in a manner similar to the foregoing step 1. The files are then relocated based on the relocation indicators.).
As per claim 18, Euler, Kim, and Tamai teach the system of claim 17. Euler teaches wherein the plurality of memory components includes a first memory component having a first data retrieval latency and a second memory component having a second data retrieval latency shorter than the first data retrieval latency (Col. 4 lines 46-51 Although diskette drive 122, hard-disk drive 123, and tape drive 124 are shown incorporated into system unit 112, they could be external to system unit 112, either connected directly, or on a local area network (LAN), on network 160, or attached to remote computer system 188; Diskette drives and hard-disk drives have different latencies in data retrieval. Diskette drives read and write in the range of kilobytes per second and hard disk drives read and write in the range of megabytes per second.)
Euler, Kim, and Tamai fail to teach the controller is configured to relocate the data item for the memory address from the first memory component to the second memory component.
However, Tanaka teaches the controller is configured to relocate the data item for the memory address from the first memory component to the second memory component (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 24, line 26 Access loads among storage units; Col. 4 lines 4042 a plurality of storage units having different access capabilities; Col. 5 lines 27-28 a storage unit having high speed access capability; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 10 lines 65-66 designation of a control unit).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, and Tamai with the teachings of Tanaka to efficiently utilize storage (see Tanaka Col. 24 lines 16-17 efficiently utilizing storage units, and improving the file access capability).
As per claim 19, Euler, Kim, Tamai, and Tanaka teach the system of claim 18. Tamai teaches wherein the controller is further configured to: identify a desired data retrieval latency for the data item based on a time gap between the command and the signal (Figs. 32, 58; Col. 76 lines 42-48 When determining in step S251 that TD1 >TL is satisfied for the ID "b", the reassignment part 75 instructs the disk interface control part 74 to terminate execution of the I/O request SSR 1 specified by the ID "b" (step S252). In response to this instruction, the disk interface 74 transmits a ABORT_TAG message, which is one of the SCSI messages, to terminate execution of the I/O request SSR 1; Col. 73 lines 46-48 The disk controller 71 includes a host interface 72, a read/write controller 73, a disk interface 74, and a reassignment part 75; Col. 81 lines 45-48 the reassignment part 75 monitors the delay time TD Of the I/O request SSR, and, when the delay time TD exceeds the limit time TL, terminates execution of processing of the I/O request SSR; Col. 49 lines 10-21 On the other hand, when TD >TL is satisfied in step S101, the reassignment part 8 instructs the SCSI interface 4 to terminate the processing of the second read request specified by the first list 82 to be processed (step S102). In step S102, in order to terminate the processing of the second read request, the assignment part 8 generates an ABORT_TAG message, one of the SCSI messages, and transmits the same to the SCSI interface 4. The SCSI interface 4 transmits the ABORT_TAG message to the disk drive 5 connected thereto. In response to the received ABORT_TAG message, the disk drive 5 terminates the second read request specified by the ID "b"; Col. 30 line 20 The controller 7 previously stores a limit time TLIMIT;).
Additionally, Tanaka teaches select, based on the desired data retrieval latency for the data item, the second memory component, from the plurality of memory components to relocate the data item (Col. 6 lines 8-17 an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit; Col. 7 lines 29-37 As a result, if the corrected actual execution time exceeds the expecting execution time set by the user, the relocation indicators are calculated for the respective files, where the indicators each include the difference between an expecting execution time and an actual execution time as an element of an execution capability bias factor thereof, in a manner similar to the foregoing step 1. The files are then relocated based on the relocation indicators.).
As per claim 20, Euler, Kim, Tamai, and Tanaka teach the system of claim 19. Kim teaches wherein the plurality of memory components include dynamic random access memory, non-volatile random access memory, or flash memory, or any combination thereof ([0102] The first type memory 121 may include a high speed volatile memory (e.g., a dynamic random access memory (DRAM) device); [0102] the second type memory 122 may include at least one of a FLASH memory).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, and Tanaka, as applied to claims 5 and 14 above, in view of Chen et al. (US 20100329052 A1 hereinafter Chen).
Chen was cited in a previous office action.
As per claim 6, Euler, Kim, Tamai, and Tanaka teach the processor of claim 5.
Euler, Kim, Tamai, and Tanaka fail to teach wherein the memory controller is further configured to resend, after at least a predetermined period of time following the abort signal, the command to the memory system.
However, Chen teaches wherein the memory controller is further configured to resend, after at least a predetermined period of time following the abort signal, the command to the memory system (Fig. 2; [0013] step 201: the controller 110 controls the decoder 120 and the driver P.sub.1 to activate the word line W.sub.1, and simultaneously to keep the word line W.sub.2 deactivated; [0014] step 202: the controller 110 read data D.sub.1 stored in the memory cell M.sub.11 through the corresponding bit line B.sub.1; [0015] step 203: the controller 110 turns off the decoder 120 and the driver P.sub.1 for a predetermined period T.sub.P for suspending the word line W.sub.1; [0016] step 204: after the predetermined period T.sub.P, the controller 110 turns on the driver P.sub.1 (the decoder 120 still remains turned-off) for writing a data D.sub.2, which is complementary to the data D.sub.1, into the memory cell M.sub.11 through the bit line B.sub.1; [0017] step 205: the controller 110 controls the decoder 120 and the driver P.sub.1 to activate the word line W.sub.1 again; [0018] step 206: the controller 110 reads a data D.sub.3 stored in the memory cell M.sub.11 through the bit line B.sub.1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, and Tanaka with the teachings of Chen to promote efficiency (see Chen [0027] In conclusion, the detecting device provided by the present invention can detect if an electrical coupling path exists between two adjacent word lines by means of suspending one of the word lines for a predetermined period and then writing a complementary data into the word line. In this way, the word lines having defects can be efficiently determined, providing a great convenience.).
As per claim 15, Euler, Kim, Tamai, and Tanaka teach the memory system of claim 14. Tanaka teaches the controller is configured to relocate the data item from the first memory component to the second memory component within the predetermined period of time (Col. 6 lines 8-19 In the present invention, an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy such that an estimated execution time for a job is limited within an expecting execution time; Col. 11 line 12 storage unit is connected with its control unit; Col. 2 lines 16-18 relocate files within a relocation allowable time so as to satisfy an execution time expected by a user).
Euler, Kim, Tamai, and Tanaka fail to teach wherein the processor is further configured to resend, after at least a predetermined period of time following the signal, the command to the memory system.
However, Chen teaches wherein the processor is further configured to resend, after at least a predetermined period of time following the signal, the command to the memory system (Fig. 2; [0013] step 201: the controller 110 controls the decoder 120 and the driver P.sub.1 to activate the word line W.sub.1, and simultaneously to keep the word line W.sub.2 deactivated; [0014] step 202: the controller 110 read data D.sub.1 stored in the memory cell M.sub.11 through the corresponding bit line B.sub.1; [0015] step 203: the controller 110 turns off the decoder 120 and the driver P.sub.1 for a predetermined period T.sub.P for suspending the word line W.sub.1; [0016] step 204: after the predetermined period T.sub.P, the controller 110 turns on the driver P.sub.1 (the decoder 120 still remains turned-off) for writing a data D.sub.2, which is complementary to the data D.sub.1, into the memory cell M.sub.11 through the bit line B.sub.1; [0017] step 205: the controller 110 controls the decoder 120 and the driver P.sub.1 to activate the word line W.sub.1 again; [0018] step 206: the controller 110 reads a data D.sub.3 stored in the memory cell M.sub.11 through the bit line B.sub.1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, and Tanaka with the teachings of Chen to promote efficiency (see Chen [0027] In conclusion, the detecting device provided by the present invention can detect if an electrical coupling path exists between two adjacent word lines by means of suspending one of the word lines for a predetermined period and then writing a complementary data into the word line. In this way, the word lines having defects can be efficiently determined, providing a great convenience.).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, Tanaka, and Chen, as applied to claim 6 above, in view of Oe et al. (US 20140297971 A1 hereinafter Oe).
Oe was cited in a previous office action.
As per claim 7, Euler, Kim, Tamai, Tanaka, and Chen teach the processor of claim 6.
Euler, Kim, Tamai, Tanaka, and Chen fail to teach wherein the predetermined period of time is configured to be longer than a time period for the memory system to remap the memory address from the first memory component to the second memory component.
However, Oe teaches wherein the predetermined period of time is configured to be longer than a time period for the memory system to remap the memory address from the first memory component to the second memory component (claim 5 wherein the moving moves, among movement areas having the rate continuously exceeding the second threshold for the predetermined number of times, data of a movement area in which number of inputs and outputs is expected to exceed the first threshold for a time longer than a time for moving data to the second storage device, to the second storage device.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Tanaka, and Chen with the teachings of Oe to reduce latency (see Oe [0097] can appropriately select a neighborhood of a high load area and move data from the HDD 300 to the SSD 200, thereby being capable of accessing the HDD 300 at a high speed.).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, Tanaka, and Chen, as applied to claim 6 above, in view of Choi (US 20200065240 A1) and further in view of Arashi et al. (US 20050249060 A1 hereinafter Arashi).
Choi and Arashi were cited in a previous office action.
As per claim 8, Euler, Kim, Tamai, Tanaka, and Chen teach the processor of claim 6.
Euler, Kim, Tamai, Tanaka, and Chen fail to teach wherein the memory controller is further configured to: free a resource associated with the command after sending the abort signal; and perform an operation using the resource between sending the abort signal and resending the command.
However, Choi teaches wherein the memory controller is further configured to: free a resource associated with the command after sending the abort signal ([0008] The controller may further: check whether the first transaction is committed or aborted, for the first write data stored in the first write buffer; perform a first write operation of storing the first write data stored in the first write buffer in the nonvolatile memory device by performing a first flush operation for the first write buffer, in the case where the first transaction is checked as being committed, and then releases the first write buffer in the volatile memory, and release the first write buffer in the volatile memory in the case where the first transaction is checked as being aborted.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Tanaka, and Chen with the teachings of Choi to effectively manage transactions (see Choi [0027] effectively manage transaction write data).
Euler, Kim, Tamai, Tanaka, Chen, and Choi fail to teach perform an operation using the resource between sending the abort signal and resending the command.
However, Arashi teaches perform an operation using the resource between sending the abort signal and resending the command ([0008] the control unit performs seek action control from a retry address which precedes an address at which an error is detected by a predetermined amount when a readout error detection signal is inputted from the information readout unit at the time of reading out the information on the optical disk, and subsequently performs seek action control from an address which is different from the previous retry address and precedes the address at which the error is detected when the readout error detection signal for the same address is inputted; [0009] In this configuration, when a readout error detection signal is inputted at the time of seek action control, a control unit performs first retry seek action control for performing readout from an address which precedes an address (hereinafter called "an error initial detection address") at which a readout error is detected by a predetermined amount. An information readout unit sequentially reads out information from an address specified by this first retry seek action control to the error initial detection address. Then, when the error detection signal is again inputted at the error initial detection address at the time of this first retry seek action control, the control unit performs second retry seek action control for performing readout from an address which precedes the error initial detection address unlike the address specified by the first retry seek action control. Then, the control unit performs the above retry seek action control over predetermined times or until information on the error initial detection address can be read out.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Tanaka, Chen, and Choi with the teachings of Arashi to reduce time needed to retry reading (see Arashi [0019] Also, according to the invention, by sequentially performing specification from an address near to the address at which an error is detected at the time of a retry seek action, the effect described above is obtained and also, time necessary to perform a retry reading action can be reduced.).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, Tanaka, and Chen, as applied to claim 6 above, in view of Arashi.
Arashi was cited in a previous office action.
As per claim 9, Euler, Kim, Tamai, Tanaka, and Chen teach the processor of claim 6.
Euler, Kim, Tamai, Tanaka, and Chen fail to teach wherein the memory controller is further configured to send, after sending the abort signal and before resending the command, a further command to retrieve data from an address different from the memory address.
However, Arashi teaches wherein the memory controller is further configured to send, after sending the abort signal and before resending the command, a further command to retrieve data from an address different from the memory address ([0008] the control unit performs seek action control from a retry address which precedes an address at which an error is detected by a predetermined amount when a readout error detection signal is inputted from the information readout unit at the time of reading out the information on the optical disk, and subsequently performs seek action control from an address which is different from the previous retry address and precedes the address at which the error is detected when the readout error detection signal for the same address is inputted; [0009] In this configuration, when a readout error detection signal is inputted at the time of seek action control, a control unit performs first retry seek action control for performing readout from an address which precedes an address (hereinafter called "an error initial detection address") at which a readout error is detected by a predetermined amount. An information readout unit sequentially reads out information from an address specified by this first retry seek action control to the error initial detection address. Then, when the error detection signal is again inputted at the error initial detection address at the time of this first retry seek action control, the control unit performs second retry seek action control for performing readout from an address which precedes the error initial detection address unlike the address specified by the first retry seek action control. Then, the control unit performs the above retry seek action control over predetermined times or until information on the error initial detection address can be read out.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Tanaka, and Chen with the teachings of Arashi to reduce time needed to retry reading (see Arashi [0019] Also, according to the invention, by sequentially performing specification from an address near to the address at which an error is detected at the time of a retry seek action, the effect described above is obtained and also, time necessary to perform a retry reading action can be reduced.).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Euler, Kim, Tamai, Tanaka, and Chen, as applied to claim 15 above, in view of Arashi and further in view of Fugini et al. (US 9823968 B1 hereinafter Fugini).
Fugini was cited in a previous office action.
As per claim 16, Euler, Kim, Tamai, Tanaka, and Chen teach the memory system of claim 15. Tanaka teaches relocation of the data item from the first memory component to the second memory component (Col. 6 lines 8-19 In the present invention, an expecting execution time set by a user and estimated access counts of respective files are stored for each job, and an actual execution time required to execute a job and access counts of respective files are monitored. If an actual execution time estimated only in consideration of accesses to files allocated in an objective storage unit exceeds the expecting execution time, the files are transferred to a faster storage unit. Stated another way, files are relocated in the storage hierarchy such that an estimated execution time for a job is limited within an expecting execution time; Col. 11 line 12 storage unit is connected with its control unit; Col. 20 lines 63-64 file is transferred from a slower storage unit to a faster storage unit).
Euler, Kim, Tamai, Tanaka, and Chen fail to teach wherein the processor is further configured to send, after sending the signal and before resending the command, a further command to retrieve data from an address different from the memory address; and the controller is configured to execute the further command in parallel with relocation of the data item from the first memory component to the second memory component.
However, Arashi teaches wherein the processor is further configured to send, after sending the signal and before resending the command, a further command to retrieve data from an address different from the memory address ([0008] the control unit performs seek action control from a retry address which precedes an address at which an error is detected by a predetermined amount when a readout error detection signal is inputted from the information readout unit at the time of reading out the information on the optical disk, and subsequently performs seek action control from an address which is different from the previous retry address and precedes the address at which the error is detected when the readout error detection signal for the same address is inputted; [0009] In this configuration, when a readout error detection signal is inputted at the time of seek action control, a control unit performs first retry seek action control for performing readout from an address which precedes an address (hereinafter called "an error initial detection address") at which a readout error is detected by a predetermined amount. An information readout unit sequentially reads out information from an address specified by this first retry seek action control to the error initial detection address).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Tanaka, and Chen with the teachings of Arashi to reduce time needed to retry reading (see Arashi [0019] Also, according to the invention, by sequentially performing specification from an address near to the address at which an error is detected at the time of a retry seek action, the effect described above is obtained and also, time necessary to perform a retry reading action can be reduced.).
Euler, Kim, Tamai, Tanaka, Chen, and Arashi fail to teach the controller is configured to execute the further command in parallel with relocation of the data item from the first memory component to the second memory component.
However, Fugini teaches the controller is configured to execute the further command in parallel with relocation of the data item from the first memory component to the second memory component (Col. 14 lines 37-40 The Write Data Multiplexer 56 facilitates data migration between the plurality of the Controller Blocks 54 and the Memory Unit 60 by coordinating parallel reading, writing and processing data in different controller blocks 54.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Euler, Kim, Tamai, Tanaka, Chen, and Arashi with the teachings of Fugini to provide error protection (see Fugini Col. 10 lines 64-65 error protection is provided in the subject method).
Conclusion
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/H.L./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195