DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The Amendment filed on 09/17/25, responding to the Requirement of Restriction mailed on 07/18/25, has been entered into the record. Claims 18-20 are cancelled and new claims 21-23 are added. Applicant’s election without traverse of Group I represented by claims 1-17 and 21-23 in the reply is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-17 and 21-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shin et al. (US2020/0219879, cited in IDS, Shin hereinafter).
As to claim 1, Shin discloses an integrated circuit structure (i.e., semiconductor device, Figs. 1 and 20) comprising:
a substrate (102/103/104/204);
a first device (200) above a first section of the substrate (102/204, II), the first device comprising
a first source region and a first drain region (250), and
a first body (212) extending laterally between the first source and first drain regions, the first body comprising silicon with crystalline orientation described by Miller index of (100) (see [0063]); and
a second device (100) above a second section of the substrate (I), the second device comprising
a second source region and a second drain region (150), and
a second body (112) extending laterally between the second source and second drain regions, the second body comprising silicon with crystalline orientation described by Miller index of (110) (see [0063]).
As to claim 2, Shin discloses the integrated circuit structure of claim 1, wherein:
the first section of the substrate (102/204), above which the first device is formed, comprises silicon with crystalline orientation described by Miller index of (100) (see [0063]).
As to claim 3, Shin discloses the integrated circuit structure of claim 1, wherein
a top portion of the second section of the substrate (104), above which the second device is formed, comprises silicon with crystalline orientation described by Miller index of (110) (see, [0063]); and
a bottom portion of the second section of the substrate (102), above which the second device is formed, comprises silicon with crystalline orientation described by Miller index of (100) (see, [0063]).
As to claim 4, Shin discloses the integrated circuit structure of claim 3, further comprising:
a layer comprising insulator material (103) between the top and bottom portions of the second section of the substrate (see Fig. 1).
As to claim 5, Shin discloses the integrated circuit structure of claim 3, further comprising:
a layer comprising oxygen (103, silicon oxide, [0022]) between the top and bottom portions of the second section of the substrate (see Fig. 1).
As to claim 7, Shin discloses the integrated circuit structure of claim 1, further comprising:
a first gate structure (235/270/272) at least in part wrapped around the first body, the first gate structure including (i) a first gate electrode (270) and (ii) first gate dielectric (272) between the first body and the first gate electrode; and
a second gate structure (135/170/172) at least in part wrapped around the second body, the second gate structure including (i) a second gate electrode (170) and (ii) second gate dielectric (172) between the second body and the second gate electrode.
As to claim 9, Shin discloses the integrated circuit structure of claim 7, further comprising:
a first spacer (235) between the first gate electrode and the first source region, and
a second spacer (235) between the first gate electrode and the first drain region,
wherein the first spacer is above and below a first tip region of the first body (i.e., edge portion of the 212 next to the first source region), and
wherein the second spacer is above and below a second tip region of the first body (i.e., edge portion of the 212 next to the first drain region). Examiner notes that the spacers 235 covers both sides of the first body.
As to claim 10, Shin discloses, the integrated circuit of claim 1, wherein the first device comprises one or more additional bodies (214 and 216) extending laterally between the first source and first drain regions, the one or more additional bodies comprising silicon with crystalline orientation described by Miller index of (100) (see [0063]).
As to claim 11, Shin discloses the integrated circuit of claim 10, wherein the first body and the one or more additional bodies are included in a vertical stack (210) including two or more nanowires, nanoribbons, or nanosheets (see [0037]).
As to claim 12, Shin discloses the integrated circuit of claim 1, wherein the second device comprises one or more additional bodies (114 and 116) extending laterally between the second source and second drain regions (150), the one or more additional bodies comprising silicon with crystalline orientation described by Miller index of (110) (see [0063]).
As to claim 13, Shin discloses an integrated circuit structure comprising:
a first source region and a first drain region (250);
a first body (212) comprising first semiconductor material and extending laterally between the first source and first drain regions;
a second source region and a second drain region (150); and
a second body (112) comprising second semiconductor material and extending laterally between the second source and second drain regions,
wherein a first crystalline orientation of the first semiconductor material (100) is different from a second crystalline orientation of the second semiconductor material (110, see [0063]).
As to claim 15, Shin discloses the integrated circuit structure of claim 13, further comprising:
a substrate (102/103/104/204) having (i) a first section (102/204), the first body above the first section, and (ii) a second section (102/103/104), the second body above the second section,
wherein the first section of the substrate comprises semiconductor material having the first crystalline orientation (i.e. orientation 100, see [0063]).
As to claim 16, Shin discloses the integrated circuit structure of claim 15, wherein:
a top portion of the second section of the substrate (104) comprises semiconductor material having the second crystalline orientation (i.e., orientation 110, see [0063]); and
a bottom portion of the second section of the substrate (102) comprises semiconductor material having the first crystalline orientation (i.e., orientation 100, see [0063]).
As to claim 17, Shin discloses the integrated circuit structure of claim 16, further comprising:
a layer comprising insulator material (i.e., silicon oxide 103) between the top and bottom portions of the second section of the substrate.
As to claim 21, Shin discloses an electronic device, comprising:
a chip package (i.e., a semiconductor device, CMOS), comprising one or more dies, at least one of the one or more dies comprising a substrate (102/103/104/204);
a first source region and a first drain region (250);
a first body (212) above a first section of the substrate (102/204) and extending laterally between the first source and first drain regions, the first body comprising silicon with crystalline orientation described by Miller index of (100) (see [0063]);
a second source region and a second drain region (150); and
a second body (112) above a second section of the substrate (102/103/104) different from the first section and extending laterally between the second source and second drain regions, the second body comprising silicon with crystalline orientation described by Miller index of (110) (see [0063]).
As to claim 22, Shin discloses the electronic device of claim 21, wherein:
the first section of the substrate (102/204), above which the first body is formed, comprises silicon with crystalline orientation described by Miller index of (100) (see [0063]).
As to claim 23, Shin discloses the electronic device of claim 22, wherein:
a top portion of the second section of the substrate (104), above which the second body is formed, comprises silicon with crystalline orientation described by Miller index of (110) (see [0063]); and
a bottom portion of the second section of the substrate (102), above which the second body is formed, comprises silicon with crystalline orientation described by Miller index of (100) (see [0063]).
Alternatively, as to claim 1, Shin discloses an integrated circuit structure (i.e., semiconductor device, Figs. 1 and 20) comprising:
a substrate (102/103/104/204);
a first device (100) above a first section of the substrate (102/103/104, I), the first device comprising
a first source region and a first drain region (150), and
a first body (112) extending laterally between the first source and first drain regions, the first body comprising silicon with crystalline orientation described by Miller index of (100) (see [0023]); and
a second device (200) above a second section of the substrate (102/204, II), the second device comprising
a second source region and a second drain region (250), and
a second body (212) extending laterally between the second source and second drain regions, the second body comprising silicon with crystalline orientation described by Miller index of (110) (see [0035]).
As to claim 6, Shin discloses the integrated circuit structure of claim 1, wherein the first device is a n- channel metal-oxide-semiconductor (NMOS) device, and the second device is a p-channel metal-oxide-semiconductor (PMOS) device (see [0019]).
Alternatively, as to claim 13, Shin discloses an integrated circuit structure comprising:
a first source region and a first drain region (150);
a first body (112) comprising first semiconductor material and extending laterally between the first source and first drain regions;
a second source region and a second drain region (250); and
a second body (212) comprising second semiconductor material and extending laterally between the second source and second drain regions,
wherein a first crystalline orientation of the first semiconductor material (110) is different from a second crystalline orientation of the second semiconductor material (100, see [0023] and [0035]).
As to claim 14, Shin discloses the integrated circuit structure of claim 13, wherein:
the first source region, the first drain region, and the first body form a n-channel metal- oxide-semiconductor (NMOS) device, and the first crystalline orientation is described by a Miller index of (100) (see [0019]); and
the second source region, the second drain region, and the second body form a p-channel metal-oxide-semiconductor (PMOS) device, and the second crystalline orientation is described by a Miller index of (110) (see [0019]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shin as applied to claim 7 above, and further in view of Chiang et al. (US 2022/0152632, cited in IDS and Chiang hereinafter).
Shin discloses the integrated circuit structure of claim 7, including formation of the first and second gate electrode (see [0084-0085]) in a side-by-side devices, however, it does not explicitly teach wherein the first gate electrode and the second gate electrode form a continuous gate electrode structure.
Chiang in a closely related art of CMOS semiconductor device teaches a first gate electrode and the second gate electrode form a continuous gate electrode structure (82, see [0047] and Fig. 16).
Since Shin and Chiang are in the same field of endeavor, a person having ordinary skill in the art at the time of invention would have recognized that forming a continuous gate structure with the first and second gate electrode could be applied the same way and would have yielded predictable results. The claim would have been obvious because the technique for improving a particular class of devices was part of the ordinary capabilities of a person of ordinary skill in the art, in view of the teaching of the technique for improvement in other situations. KSR Int'l Co. v. Teleflex Inc. 550 U.S. __, 82USPQ2d 1385 (Supreme Court 2007) (KSR).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eva Yan Montalvo whose telephone number is (571)270-3829. The examiner can normally be reached M-TH 9AM-7PM ET.
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/EVA Y MONTALVO/ Supervisory Patent Examiner, Art Unit 2818
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