DETAILED ACTION
This action is responsive to the following: The amended claims, request for reconsideration after on-final rejection, and arguments made by applicant filed on July 30 2025.
Claims 1-8 and 16-27 are pending. Claims 1 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed July 30th, 2025 has been entered. Claims 1-8 and 16-27 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 16-19, 21-25 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Nii (US 20060262628) in view Bhavnagarwala et al (US 6788566).
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Regarding Independent Claim 1, Nii teaches a memory circuit comprising:
a memory array circuit (Fig. 1: 1) that comprises a first column of memory cells (Fig. 1: MC, BL0, /BL0);
a column selection circuit (Fig 1: 4) coupled to the first column of the memory cells (Fig. 1: MC, BL0, /BL0) through a first bit line (Fig. 1: BL0, wherein the column selection circuit pulls a voltage of the first bit line toward a predefined voltage in response to a first write control signal during a first write operation to at least one of the memory cells in the first column;
a write enable circuit (Fig 59: 7) that generates a write enable signal (Fig. 59 : WE, WEN);
However, Nii fails to teach a first regenerative repeater circuit coupled to the first column of the memory cells through the first bit line, wherein the first regenerative repeater circuit pulls the voltage of the first bit line toward the predefined voltage in response to the write enable signal during the first write operation.
Bhavnagarwala teaches a regenerative repeater circuit (Fig. 2: 100) coupled to the first column of the memory cells (Fig 2: SRAM Cell) through the first bit line (Fig 2: BL), wherein the first regenerative repeater circuit pulls the voltage of the first bit line toward the predefined voltage in response to the write enable signal during the first write operation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a memory circuit with write enable circuitry and a regenerative repeater circuit that pulls the voltage of the bit line to a predefined value.
Regarding Claim 2, Nii and Bhavnagarwala teach the limitations of Claim 1.
Bhavnagarwala further teaches the first regenerative repeater circuit (Fig. 2: 100; drain of 118 connected to ground, which the BL discharges through) discharges the first bit line to a ground voltage during the first write operation (col 3 lines 10-18).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a regenerative repeater circuit that discharges the first bit line to ground.
Regarding Claim 3, Nii and Bhavnagarwala teach the limitations of Claim 1.
Bhavnagarwala further teaches the first regenerative repeater circuit (Fig. 2: 100) comprises a first inverter circuit (Fig. 2: 114, 116) coupled to the first bit line (Fig. 2: BL) and a first transistor (Fig. 2: 118) coupled to the first bit line and to an output of the first inverter circuit, and wherein the first inverter circuit turns the first transistor on to pull the voltage of the first bit line toward the predefined voltage in response to the column selection circuit pulling the voltage of the first bit line toward the predefined voltage during the first write operation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a regenerative repeater circuit consisting of an inverter coupled to a transistor and each coupled to a bit line such that the bit line going toward ground causes the first inverter to turn on the transistor and pull the bit line toward ground.
Regarding Claim 4, Nii and Bhavnagarwala teach the limitations of Claim 1.
Nii further teaches a circuit is coupled to the first column of the memory cells (Fig. 44: PCK) through a second bit line (Fig 44: /BL), and wherein the circuit pulls a voltage of the second bit line toward the predefined voltage (Fig. 44: VDD) during a write operation.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a circuit coupled to a second bit line that pulls the voltage of a second bit line to a predefined value during a write operation.
Regarding Claim 5, Nii and Bhavnagarwala teach the limitations of Claim 1.
Nii further teaches that the memory circuit further comprises:
word line decoder circuits (Fig 1: 3) coupled to the memory array circuit (Fig 1: 1), wherein the memory array circuit comprises rows of the memory cells, wherein the word line decoder circuits are coupled to the rows of the memory cells through word lines (Fig 1: WL0-WLn), and wherein the word line decoder circuits assert selected ones of the word lines to write bits to the memory cells in the rows coupled to the selected ones of the word lines.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii produce the memory circuit of claim 1 with a word line decoder that selects word lines to write the selected memory cells of the array.
Regarding Claim 6, Nii and Bhavnagarwala teach the limitations of Claim 1.
Nii further teaches a memory array circuit (Fig 1: 1) further comprises a second column of memory cells (Fig 1: MC, BLn, /BLn), wherein the column selection circuit is coupled to the second column of the memory cells through a second bit line (Fig 1: BLn), wherein the column selection circuit pulls a voltage of the second bit line toward the predefined voltage in response to a second write control signal during a second write operation (para 380) to at least one of the memory cells in the second column, and wherein the memory circuit further comprises:
a second write assist circuit (Fig 1: PCKn) coupled to the second column of the memory cells through the second bit line.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a memory circuit with a second column of memory cells and second regenerative repeater write assist circuit, which is used to pull the second bit line to a predefined value during a write operation.
Regarding Claim 7, Nii and Bhavnagarwala teach the limitations of Claim 1.
Nii teaches the column selection circuit (Fig 1: 4) is coupled to the first bit line (Fig. 1: BL0) next to a first edge of the memory array circuit, wherein the first regenerative repeater circuit (Fig 1: PCK0) is coupled to the first bit line (Fig 1: BL0) next to a second edge of the memory array circuit, and wherein the second edge of the memory array circuit is opposite to the first edge.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a memory circuit where the regenerate repeater circuit is on the opposite edge of the memory array from the column selection circuit.
Regarding Claim 8, Nii and Bhavnagarwala teach the limitations of Claim 1.
Nii teaches the first regenerative repeater circuit (Fig. 44: PCK) comprises first and second inverter circuits (Fig. 44: IV40, IV42) and first and second transistors (Fig. 44: PT80, PT82), wherein an input of the first inverter circuit is coupled to the first bit line, wherein an output of the first inverter circuit is coupled to an input of the first transistor, wherein an input of the second inverter circuit are coupled to the first column of the memory cells through a second bit line, and wherein an output of the second inverter circuit is coupled to an input of the second transistor.
However, Nii does not teach that the first transistor is coupled to the second bit line and the second transistor is coupled to the second bit line.
Bhavnagarwala teaches that a regenerative repeater circuit (Fig. 2: 100) a transistor (Fig. 2: 118) and an input of an inverter circuit (Fig. 2: 114, 116) are coupled to the bit line (Fig. 2: BL), wherein an output of the inverter (Fig. 2: 114, 116) circuit is coupled to an input of the transistor (Fig. 2: 118).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a memory circuit wherein the regenerative repeater circuit with contain inverters and transistors coupled together and to two bit lines in this way.
Regarding Independent Claim 16, Nii teaches method for writing data to a memory circuit, the method comprising:
driving a voltage of a first bit line toward a predefined voltage (Fig. 46: WRITE OPERATION, BL) with a column selection circuit (Fig. 1: 4) in response to a first write control signal (Fig. 8: CSL) during a first write operation to a column of memory cells in the memory circuit, wherein the column selection circuit is coupled to the column of the memory cells through the first bit line (Fig. 46: BL);
generating a write enable signal (Fig 59: WE, WEN) with a write enable circuit (Fig 59: 7);
However, Nii does not teach driving the voltage of the first bit line toward the predefined voltage with a first regenerative repeater circuit in response to the write enable signal during the first write operation, wherein the first regenerative repeater circuit is coupled to the column of the memory cells through the first bit line.
Bhavnagarwala teaches driving a voltage of a bit line toward the predefined voltage col (3 lines 13-18) with a regenerative repeater circuit (Fig. 2: 100) in response to the write enable signal (Fig. 2: Subarray Select) during the write operation, wherein the regenerative repeater circuit is coupled to the column of the memory cells (Fig. 2: 110) through the bit line (Fig. 2: BL).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a method of operating a memory circuit wherein the bit lines are charged to predefined values during a write operation in response to the column selection circuit. And wherein a regenerative repeater circuit provides write assist by pulling the bit line to a predefined value.
Regarding Claim 17, Nii and Bhavnagarwala teach the limitations of claim 16.
Bhavnagarwala further teaches driving the voltage of the first bit line toward the predefined voltage with the first regenerative repeater (Fig. 2: 100) circuit further comprises:
turning on a transistor (Fig. 2: 118) in the first regenerative repeater circuit using an inverter circuit (Fig. 2: 114, 116) to drive the voltage of the first bit line (Fig. 2: BL) toward the predefined voltage in response to the bit line dropping below a certain threshold voltage. (Col 3 lines 13-18).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to teach a write assist circuit where the regenerative repeater circuit turns on a transistor using an inverter to drive the voltage of a bit line to a predefined voltage in response to signals from the column select and write enable circuits.
Regarding Claim 18, Nii and Bhavnagarwala teach the limitations of claim 16.
Nii teaches driving a voltage of a second bit line (Fig. 1: /BL) toward the predefined voltage (Fig. 46: WRITE OPERATION, /BL) with the column selection circuit in response to a second write control signal during a second write operation (para 380) to the column of the memory cells (Fig. 1: MC, BL0, /BL0) in the memory circuit, wherein the column selection circuit is coupled to the column of the memory cells through the second bit line (Fig. 1: /BL0); and
Bhavnagarwala teaches driving a voltage of a bit line toward the predefined voltage col (3 lines 13-18) with a regenerative repeater circuit (Fig. 2: 100) in response to the write enable signal (Fig. 2: Subarray Select) during a write operation (col 3 lines 13-18), wherein the regenerative repeater circuit is coupled to the column of the memory cells (Fig. 2: 110) through the bit line (Fig. 2: BL).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a memory circuit where the second bit line is driven to a predefined voltage during a second write operation using a second regenerative repeater circuit.
Regarding Claim 19, Nii and Bhavnagarwala teach the limitations of claim 18.
Bhavnagarwala turning on a transistor (Fig. 2: 118) in the regenerative repeater circuit using an inverter circuit (Fig. 2: 114, 116) to drive the voltage of the bit line (Fig. 2: BL) toward the predefined voltage in response to the bit line dropping below a certain threshold voltage. (Col 3 lines 13-18).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a method where a transistor is turned on a second regenerative repeater circuit by an inverter in the same circuit in order to drive the second bit line to a predefined voltage.
Regarding Claim 21, Nii and Bhavnagarwala teach the limitations of claim 16.
Bhavnagarwala further teaches the first regenerative repeater circuit (Fig. 2: 100; drain of 118 connected to ground, which the BL discharges through) discharges the first bit line to a ground voltage during the first write operation (col 3 lines 10-18).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a memory circuit where the method of operation involves the regenerative repeater circuit discharging to ground.
Regarding Claim 22, Nii and Bhavnagarwala teach the limitations of claim 16.
Bhavnagarwala further teaches pulling a voltage of a bit line (Fig. 2: BL) toward the predefined voltage in response to the write enable (Fig. 2: Subarray Select) signal during a write operation (col 3 lines 10-18) to at least one of the memory cells (Fig. 2: 110) in the column using the regenerative repeater circuit (Fig 2: 100), wherein the first regenerative repeater circuit is coupled to the column of the memory cells through the bit line.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce a method of operating a memory circuit such that the first regenerative repeater circuit to a predefined value during a second write operation in response to a write enable signal.
Regarding Claim 23, Nii and Bhavnagarwala teach the limitations of claim 16.
Nii further teaches asserting word lines (Fig 46: WL, WRITE OPERATION) to write bits (Fig 46: ND1, ND2, WRITE OPERATION) to the memory cells in rows coupled to the word lines using word line decoder circuits (Fig 1: 3), wherein the word line decoder circuits are coupled to the rows through the word lines (Fig 1: WL0-WLn).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Bhavnagarwala to the teachings of Nii to produce the method of operating a memory circuit outline in claim 16 wherein the during a write operation word lines are asserted to write bits to memory cells using word lines coupled to a word line decoder.
Regarding Claim 24, Nii and Bhavnagarwala teach the limitations of claim 16.
Claim 24 is rejected for the same basis as claim 7.
Regarding Claim 25, Nii and Bhavnagarwala teach the limitations of claim 16.
Claim 25 is rejected for the same basis as Claim 8.
Regarding Claim 27, Nii and Bhavnagarwala teach the limitations of claim 1.
Claim 27 is rejected for the same basis as claim 19.
Claims 20 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Nii (US 20060262628) and Bhavnagarwala et al (US 6788566) in view of Rim et Al (US 20160042784).
Regarding Claim 20, Nii and Bhavnagarwala teach the limitations of claim 16.
However, Nii and Bhavnagarwala fail to teach a method wherein driving the voltage of the first bit line toward the predefined voltage with the column selection circuit further comprises:
driving the voltage of the first bit line toward the predefined voltage with a write driver circuit that receives a data input signal that indicates a bit value to write to at least one of the memory cells in the column of the memory cells during the first write operation, wherein the write driver circuit is coupled to the column selection circuit.
Rim teaches a write driver circuit (Fig. 2: 120) which drives one of the bit lines of a column of memory cells to a predefined value by receiving a data input signal (Fig. 2: data) to write at least one of the memory cells in the column of memory cells.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have applied the teachings of Rim to the teachings of Bhavnagarwala and Nii to produce a memory circuit with a write driver circuit coupled to the column selection circuit that drives the bit lines to a predefined value to write at least one of the cells during a write operation.
Regarding Claim 26, Nii and Bhavnagarwala teach the limitations of claim 1.
Claim 26 is rejected under the same basis as claim 20.
Response to Arguments
Applicant's arguments filed July 30th 2025 have been fully considered but they are not persuasive.
Applicant argues the obviousness rejection over the combination of Nii and Bhavnagarwala is improper because Nii’s “write assist circuit PCK0” is not the “first regenerative repeater,” as recited in claim 1. To support the argument, applicant asserts Nii’s PCK0 does not “pull[] the voltage of the first bit line toward the predefined voltage” as required by claim 1, because Nii’s write assist circuit PCK0 merely receives voltages from BL & /BL as inputs ot a NAND gate and does not affect the voltages on the bit line (Remarks 7). Applicant also asserts Nii’s “write assist circuit BPCK0” also does not pull the voltage of a bit line before BPCK0 does not receive the bit line voltage as inputs and therefore cannot affect the bit line voltage (Remarks 8, second full paragraph).
Applicant’s arguments are not persuasive because it does not respond to the rejection. The rejection of record does not rely upon Nii’s circuitry this way, but instead relies upon the teachings of Bhavnagarwala’s assist circuit 100 that uses two series connected pull-down transistors (Fig. 2: 118 and 120) that “pull” down the bitline (BL) to a “predefined voltage” (i.e., Vss). Furthermore, Bhavnagarwala’s circuit 100 in Figure 2 is substantially identical to the “regenerative repeater circuit” disclosed in the instant application Figure 2, insofar as presently claims as it has the functional inverter (Fig. 2: 114 and 116) that receives input from the bitline to create output feedback to transistor 118 to pull down the bit line through transistor 120, in the same way the application’s inverter 201 receives input from the bitline to create output feedback to transistor 203 to pull down the bitline through transistor 205.
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Applicant also argues the obviousness rejection over the combination of Nii and Bhavnagarwala is improper because Bhavnagarwala’s circuit 100 also cannot be the “first regenerative repeater,” required by claim 1. To support this argument, applicant asserts Bhavnagarwala’s circuit 100 also does not pull the bit line to a predefined voltage. According to applicant, the PFET 114 drives NFET 118 to assist in developing a signal on the bitline, and the feedback provided in the assist circuit is initiated by the bit line voltage, itself, as opposed to in response to the subarray select signal (or “write enable” as claimed) (Remarks 8-9).
Applicant’s argument is not persuasive. As indicated above, Bhavnagarwala’s circuit 100 uses transistors 118 and 120 to “pull” down the bitline, in the same way that instant application Figure 2 uses transistors 203 and 205 to “pull” down the bitline, to a “predefined voltage” (i.e., vss).
Applicant also argued the obviousness rejection over the combination of Nii and Bhavnagarwala is improper because Nii’s main control circuit 7 is not a “write enable circuit” that generals a “write enable signal” because it produces the “write instruction signal WEN” according to a “write enable signal WE” (i.e., it receives a “write enable signal” to generate a write instruction signal) (Remarks 8, first full paragraph).
Applicant’s argument is not persuasive. Nii teaches a control circuit that produces a signal WEN which enables write operations. Although Nii refers to WEN as a “write instruction signal” (Nii para. 0466), WEN is a signal used to enable the write operation of the device and therefore is a “write enable signal.” If anything, the difference between the claimed “write enable signal” and Nii’s WEN signal is a mere difference in words, and identity of terminology is not required. Cf. MPEP 2131 (quoting In re Bond, 910 F.2d 831 (Fed. Cir. 1990)).Fruthermore, Bhavnagarawala as well teaches a “subarray select” signal which functions identically to the write enable signal disclosed by applicant by activating a pull-down NFET with a source connected to a predefined voltage source, which provides a path to pull the bit line to this predefined voltage(i.e., Vss).
The rejections are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825