Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendment to claims 1 and 4 submitted on April 6, 2026 is acknowledged and has since been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 6, 8, 9, and 10 are rejected under 35 U.S.C. 103 as being obvious over Gardner (US 20210082901 A1) in further view of Rubin (US 20200126987 A1) and further evidenced by Xu (“Preparation and Properties of Hydrophobically modified Nano-SiO2 with Hexadeclytrimethoxysilane”, 2021).
Regarding Claim 1, Gardner teaches a method (see flowchart in Fig. 23) for forming a stacked semiconductor device (100), the method comprising:
forming a first semiconductor structure (107) on a first wafer (100a, shown Fig. 16);
forming a second semiconductor structure (107) on a second wafer (100b, shown Fig. 16);
positioning the first wafer with respect to the second wafer such that a top surface of the first semiconductor structure is directly facing a top surface of the second semiconductor structure (See Figs. 18-19 which show the second structure being flipped to bond with the first structure);
forming a bonding layer (122, see also [0058]) between the top surface of the first semiconductor structure and the top surface of the second semiconductor structure (shown Figs. 18-19), wherein respective wafer surfaces upon which the bonding layer is formed are pretreated with a prolonged water treatment comprising a duration of greater than 10 minutes (see [0040] describing first and second wafers being rinsed in DI water for 10 to 20 minutes), just before bonding, to convert the respective wafer surfaces to a more hydrophilic state (see [0040] which notes that the chemical oxide film aids in forming a strong covalent silicon bond once heated, wherein a chemical oxide formed on a silicon wafer is known to be naturally hydrophilic, see also Abstract of Xu which notes that common silicon and its native oxide are “extremely hydrophilic due to the presence of a large number of hydroxyl groups on its surface.”);
bonding the first wafer to the second wafer (shown Fig. 19) at a first temperature (initial adhesion occurring due to Van der Walls bonding at room temperature, see [0036]); and
annealing (see [0058]) at a second temperature to cure the bonding layer, wherein the second temperature is greater than the first temperature (see [0041]); and
exposing the channel layer (described in Gardner: Claim 20, see also S2317 in Fig. 23) of the first semiconductor device;
building a first transistor (see [0063] which describes the transistor being formed before or after the bonding step) from the exposed channel layer of the first semiconductor device;
bonding a third wafer (103c) to the first transistor (shown Fig. 22);
exposing the channel layer of the second semiconductor device (described in Gardner: Claim 20, see also S2317 in Fig. 23); and
building a second transistor from the exposed channel layer of the second semiconductor device (see [0063] which describes the transistor being formed before or after the bonding step).
The device of Gardner further teaches each of the first semiconductor structure and the second semiconductor structure being nanosheet transistors (see [0043] and Fig. 16 showing nanostructure stacks), but does not explicitly teach a first semiconductor structure having a channel layer of a first transistor type and a second semiconductor structure having a channel layer of a second transistor type different than the first transistor type.
Rubin teaches a method of forming a vertically stacked semiconductor device (see Fig. 18), wherein a lower layer comprises a first semiconductor structure (M1, a FinFET, see also [0037]) and an upper layer comprises a second semiconductor structure (M3, a nanosheet FET, see also [0049] and Fig. 18). As each FET structure is formed on a separate semiconductor wafer, modifying a channel type to be either a nanosheet GAA FET or FinFET as disclosed by Rubin would be obvious to one of ordinary skill in the art prior to the effective filing date as a matter of design choice (see also MPEP 2144.04 and In re Dailey, 357 F.2d 669, 149 USPQ 47).
More specifically, adopting the design choice of the device of Rubin in Fig. 18 would teach the first semiconductor structure having a channel layer of a first transistor type (FinFET) and the second semiconductor structure having a channel layer of a second transistor type (nanosheet FET) different than the first transistor type.
Regarding Claim 3, Gardner as modified by Rubin teaches the method of claim 1, wherein:
the first transistor type comprises one of a fin-type field effect transistor and a nanosheet transistor (as modified by Rubin, a FinFET); and
the second transistor type comprises an opposite one of a nanosheet transistor and a fin-type field effect transistor (as modified by Rubin, a nanosheet FET).
Regarding Claim 6, Gardner as modified by Rubin teaches the method of claim 1 further comprising:
forming a first insulator layer (120) between the first semiconductor structure and the bonding layer (shown Fig. 22); and
forming a second insulator layer (120) between the second semiconductor structure and the bonding layer (shown Fig. 22).
Regarding Claim 8, Gardner as modified by Rubin teaches the method of claim 6 further comprising pretreating a surface of the first insulator layer and a surface of the second insulator layer (see [0040] describing the first wafer and second wafer going through a pretreatment two-step clean sequence).
Regarding Claim 9, Gardner as modified by Rubin teaches the method of claim 8, wherein pretreating comprises one or more of a deionized (DI) water treatment, an argon or oxygen plasma treatment, and an ultraviolet (UV) cure (see Gardner: [0040]).
Regarding Claim 10, Gardner as modified by Rubin teaches the method of claim 1, wherein:
the first temperature comprises a temperature below 400 degrees Celsius (room temperature); and
the second temperature comprises a temperature above 400 degrees Celsius and below 1000 degrees Celsius (see [0038] describing the anneal being between 400° C and 600° C).
Claim(s) 4-5 are rejected under 35 U.S.C. 103 as being obvious over Gardner (US 20210082901 A1) in view of Rubin (US 20200126987 A1) and further in view of Wang (US 20200403097 A1).
Regarding Claim 4, Gardner as modified by Rubin teaches the method of claim 1, however Gardner and Rubin are silent regarding a crystalline orientation of the first semiconductor structure and the second semiconductor structure.
Wang teaches a method of bonding two wafers, wherein “a crystal orientation of each wafer may also be independently chosen by varying the starting wafer with the designated orientation, if desired” (see Wang: [0057]).
Transistor devices comprising monocrystalline silicon with crystalline orientations of either <110> or <100> are well known to those of ordinary skill in the art. In addition, there are a finite number of crystalline orientations that may be implemented when epitaxially growing monocrystalline semiconductor material layers (i.e., a silicon layer) to achieve the desired semiconductor channel effects. Thus, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a first semiconductor structure having a first crystalline orientation and a second semiconductor structure having a second crystalline orientation as a matter of design choice (see also MPEP 2144.04 and In re Dailey, 357 F.2d 669, 149 USPQ 47) as Wang suggests that the crystal orientations of these structures are chosen independently from each other.
Furthermore, the configuration of the above crystalline orientations may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Regarding Claim 5, Gardner as modified by Rubin and Wang teaches the method of claim 4, wherein the first transistor type comprises one of a fin-type field effect transistor and a nanosheet transistor, but is silent regarding specific crystalline orientations of the first semiconductor structure and second semiconductor structure.
Wang discloses that the crystal orientation of each wafer is independently chosen (see [0057]). Transistor devices comprising monocrystalline silicon with crystalline orientations of either <110> or <100> are well known to those of ordinary skill in the art. In addition, there are a finite number of crystalline orientations that may be implemented when epitaxially growing monocrystalline semiconductor material layers (i.e., a silicon layer) to achieve the desired semiconductor channel effects. Thus, it would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to try a variation of the stacked device of Wang to comprise a first semiconductor structure with semiconductor channels having <110> orientation and a second semiconductor structure with semiconductor channels having <100> orientation as suggested in [0057] of Wang as the crystal orientations of these structures are chosen independently from each other (see also MPEP 2144.05).
Furthermore, the configuration of the above crystalline orientations may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gardner (US 20210082901 A1 in view of Rubin (US 20200126987 A1) and in further view of Batey (Low-Temperature Deposition of High-Quality Silicon Dioxide by Plasma-Enhanced Chemical Vapor Deposition”, 1986).
Regarding Claim 7, Gardner as modified by Rubin teaches the method of claim 6, wherein the first insulator layer and the second insulator layer comprise an oxide (see [0040]). However, Gardner does not explicitly describe the dielectric layers being high density plasma (HDP) oxides.
Batey describes a method of depositing a plasma-enhanced high-quality silicon dioxide layer via slow deposition rate at relatively low temperatures (under 400 degrees Celsius), which results in a thin silicon dioxide film that is dense, pin-hole free, and has good electrical characteristics when compared to standard thermal oxides (see “CONCLUSIONS”).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a high-density plasma (HDP) oxide as the “low temperature” oxide layers described by Gardner as there are numerous advantages (see described above) of HDP oxides formed at low temperatures as applied to thin film transistor technology (see “CONCLUSIONS”).
Response to Arguments
Applicant's arguments filed April 6, 2026 have been fully considered but they are not persuasive.
Applicant argues that the cleaning steps of Gardner are not the same as “wherein respective wafer surfaces upon which the bonding layer is formed are pretreated with a prolonged water treatment comprising a duration of greater than 10 minutes, just before bonding, to convert the respective wafer surfaces to a more hydrophilic state” as Gardner contemplates the DI water treatment being followed by a NH4OH:H2O2:H2O clean prior to bonding. Examiner respectfully disagrees, and notes that one of ordinary skill in the art would broadly interpret the pretreatment steps of Gardner to include “a prolonged water treatment comprising a duration of greater than 10 minutes, just before bonding” (see also Gardner: [0040-0041] which cites a bonding step immediately after a cleaning step). Examiner notes that the instant application further contemplates additional or alternative pretreatment techniques being used in paragraph [0068]. Furthermore, Xu (“Preparation and Properties of Hydrophobically modified Nano-SiO2 with Hexadeclytrimethoxysilane”, 2021) describes a chemical oxide film (nano-SiO2) being formed on a silicon substrate as being naturally hydrophilic (see Xu: Abstract).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASEY PAUL BOATMAN whose telephone number is (703)756-4778. The examiner can normally be reached M-F 7:30 AM - 5:30 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights