Prosecution Insights
Last updated: April 19, 2026
Application No. 17/554,511

INTEGRATED ELECTRONICS ON THE ALUMINUM NITRIDE PLATFORM

Non-Final OA §103
Filed
Dec 17, 2021
Examiner
SHEKER, RHYS PONIENTE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cornell University
OA Round
5 (Non-Final)
85%
Grant Probability
Favorable
5-6
OA Rounds
3y 3m
To Grant
91%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
41 granted / 48 resolved
+17.4% vs TC avg
Moderate +6% lift
Without
With
+5.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
45 currently pending
Career history
93
Total Applications
across all art units

Statute-Specific Performance

§103
59.2%
+19.2% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
20.1%
-19.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 48 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to the Applicant’s Remarks filed on 02/03/2026. Currently, claims 1, 23-29, and 35-47 are pending in the application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/03/2026 has been entered. Response to Amendments Applicant' s arguments with respect to claim(s) 1, 23-29, and 35-47 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 26, and 47 are rejected under 35 U.S.C. 103 as being obvious over LIU et al. (Foreign Pub. No. CN 110474616 A (English translation attached)) in view of BADER et al. (“Gate-Recessed E-mode p-Channel HFET With High On-Current Based on GaN/AlN 2D Hole Gas”) and further in view of GIBB et al. (US Pub. No. 2019/0312027) Regarding independent claim 1, Liu teaches a semiconductor component (Fig. 5) comprising: one not intentionally doped AIN buffer layer (Fig. 5, 103, ¶ [0044]) epitaxially deposited (¶ [0047] teaches that Liu’s piezoelectric film is formed using MOCVD) on a substrate (Fig. 5, 105,); a structure, comprising: a structure (c) comprising: a first electrically conductive layer (Figs. 1 & 5, 104, ¶ [0051], the Examiner notes that 104 is unlabeled in Fig. 5 ) contacting only a first side of a first portion of the one not intentionally doped AIN buffer layer and sidewalls of an opening formed to extend through the substrate to the first side of the first portion of the one not intentionally doped AIN buffer layer (Fig. 5); and a second electrically conductive layer (Fig. 5, 107, ¶ [0051]) formed on only a second side of the first portion of the one not intentionally doped AIN buffer layer opposite to the first electrically conductive layer, wherein a thickness of the structure (c) is selected to obtain a predetermined center frequency of a filter (¶¶ [0006]-[0008] teaches that Liu’s device is an FBAR filter suitable for high frequency applications. It would be obvious to one of ordinary skill in the art that the thickness of Li’s FBAR filter corresponds to a center frequency). However, Li does not explicitly teach at least one other structure of: a structure (a) comprising: a second epi-layer of a second Group III nitride material epitaxially grown on a second portion of the one not intentionally doped AIN buffer layer; and comprising a 2D hole gas at a heterojunction between the one not intentionally doped AIN buffer layer and the second epi-layer of the second Group III nitride material, wherein a difference between a normal component of a polarization of the second epi-layer layer of the second Group III nitride material and the one not intentionally doped AIN buffer layer is negative; and, wherein there is an energy band offset between valence bands of the one not intentionally doped AIN buffer layer and the second Group III nitride material, wherein an energy bandgap of the second Group III nitride material being is smaller than an energy bandgap of AIN. However, Bader is a pertinent art that teaches a structure (a) comprising: a second epi-layer of a second Group III nitride material (Fig. 1b, 5 nm GaN channel, II. Experimental Results and Modeling) epitaxially grown on a not intentionally doped AIN buffer layer (II. Experimental Results and Modelling teaches GaN/AlN heterostructures obtained with Molecular Beam Epitaxy. There is no mention of the AlN in Fig. 1b being intentionally doped); and comprising a 2D hole gas (2DHG forms between AlN and GaN channel in Figure 1b) at a heterojunction between the one not intentionally doped AIN buffer layer and the second epi-layer of the second Group III nitride material, wherein a difference between a normal component of a polarization of the second epi-layer layer of the second Group III nitride material and the one not intentionally doped AIN buffer layer is negative (the polarization difference between AlN and GaN is negative); and, wherein there is an energy band offset between valence bands of the one not intentionally doped AIN buffer layer and the second Group III nitride material (see Ev at 2DHG in Fig. 1a), wherein an energy bandgap of the second Group III nitride material being is smaller than an energy bandgap of AIN (see Ev and Ec at 2DHG in Fig. 1a). a second epi-layer of a second Group III nitride material (Fig. 1b, 5 nm GaN channel, II. Experimental Results and Modeling) epitaxially grown on a second portion of the one not intentionally doped AIN buffer layer. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to integrate Liu’s FBAR filter with Bader’s HFET according to the teaching of Bader (Figs. 1A-1B) in order to use the high sheet conductance and wide bandgaps of Bader’s Gan/AlN structure in a monolithic device (Bader III. Conclusions and Benchmarks). However, Liu modified by Bader does not explicitly teach a second epi-layer of a second Group III nitride material epitaxially grown on a second portion of the one not intentionally doped AIN buffer layer. However, Gibb a second epi-layer of a second Group III nitride material epitaxially grown on a second portion of the not intentionally doped AIN buffer layer (Both Liu’s FBAR filter and Bader’s HFET require an epitaxial AlN layer. Gibb Fig. 15E, ¶¶ [0062]-[0067] teaches a filter and an active device on a single epitaxial AlN layer). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Bader’s device to be on a second portion of Liu’s epitaxial AlN layer according to the teaching of Gibb (Fig. 15E) in order to reduce integration cost (Gibb ¶ [0068])). Regarding claim 26, Liu modified by Bader modified by Gibb teaches the semiconductor component of claim 1, and Bader teaches that that the at least one other structure comprises: structure (a) (see Regarding independent claim 1). Regarding claim 47, Liu modified by Bader modified by Gibb teaches the semiconductor component of claim 1, and Liu teaches that the first electrically conductive layer Figs. 1 & 5, 104, ¶ [0051], the Examiner notes that 104 is unlabeled in Fig. 5 ) and the second electrically conductive layer (Fig. 5, 107, ¶ [0051]) are not metallic transition metal nitride layers (¶ [0012] teaches that Liu’s top and bottom electrodes are not transition metal nitride layers). Claims 27-28 are rejected under 35 U.S.C. 103 as being obvious over LIU et al. (Foreign Pub. No. CN 110474616 A (English translation attached)) in view of BADER et al. (“Gate-Recessed E-mode p-Channel HFET With High On-Current Based on GaN/AlN 2D Hole Gas”) and further in view of GIBB et al. (US Pub. No. 2019/0312027) and further in view of HICKMAN et al. (A. Hickman et al., "High Breakdown Voltage in RF AlN/GaN/AlN Quantum Well HEMTs," in IEEE Electron Device Letters, vol. 40, no. 8, pp. 1293-1296, Aug. 2019). Regarding claim 27, Liu modified Bader modified by Gibb teaches the semiconductor component of claim 1. However, Liu modified by Bader modified by Gibb does not explicitly teach that the at least one other structure comprises one structure, structure (b). However, Hickman is a pertinent art that teaches a second epi-layer of a second Group III nitride material (Fig. 1a, 30 nm GaN channel) epitaxially grown on the one not intentionally doped AIN buffer layer (II. Device Fabrication teaches AlN/GaN/AlN epitaxial structures grown by plasma-assisted molecular beam epitaxy (MBE) on semi insulating 6H silicon carbide substrates. There is no mention of the AlN buffer layer in Figure 1 being intentionally doped); and comprising a 2D hole gas (2DHG forms between AlN buffer and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the one not intentionally doped AIN buffer layer and the second epi-layer of the second Group III nitride material, wherein a difference between a normal component of a polarization of the second epi-layer of the second Group III nitride material and the one not intentionally doped AIN buffer layer is negative (the polarization difference between AlN and GaN is negative); wherein there is an energy band offset (see Ev at 2DHG in Fig. 1b) between valence bands of the not intentionally doped AIN buffer layer and the second epi-layer of the Group III nitride material and wherein an energy bandgap of the second epi-layer of the Group III nitride material being is smaller than an energy bandgap of AlN (see Ev and Ec at 2DHG in Fig. 1b) and the structure (b) further comprising a third Group III-N barrier layer deposited over a portion of the second epi-layer of the second Group III nitride material (Fig. 1A, 4 nm AlN barrier), wherein a thickness of the third Group III-N barrier layer and a composition and a thickness of a third Group III-N material are selected to form a two dimensional electron gas (2DEG) (Fig. 1A, 2DEG forms between 4 nm AlN barrier and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the second epi-layer of the second Group III nitride material and the third Group III-N barrier layer. Therefore, it would have been obvious to modify Liu modified by Bader modified by Gibb’s semiconductor component according to the teaching of Hickman (Figs. 1a-1b) in order to use an AlN/GaN/AlN quantum well HEMT as a platform for a high-power RF transistor (Hickman Abstract). Further, Hickman also teaches that Hickman’s AlN platform offers the possibility of integrating Bader’s p-Channel FET towards a nitride CMOS (Hickman I. Introduction) and Bader also notes the opportunity for monolithic integration with other AlN/Gan/AlN devices (Bader III. Conclusions and Benchmarking). Regarding claim 28, Liu modified by Bader modified by Gibb teaches the semiconductor component of claim 1, and Liu modified by Bader modified by Gibb teaches structure (a). However, Liu modified by Bader modified by Gibb does not explicitly teach that the at least one other structure comprises: structure (b). However, Hickman is a pertinent art that teaches a second epi-layer of a second Group III nitride material (Fig. 1a, 30 nm GaN channel) epitaxially grown on the one not intentionally doped AIN buffer layer (II. Device Fabrication teaches AlN/GaN/AlN epitaxial structures grown by plasma-assisted molecular beam epitaxy (MBE) on semi insulating 6H silicon carbide substrates. There is no mention of the AlN buffer layer in Figure 1 being intentionally doped); and comprising a 2D hole gas (2DHG forms between AlN buffer and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the one not intentionally doped AIN buffer layer and the second epi-layer of the second Group III nitride material, wherein a difference between a normal component of a polarization of the second epi-layer of the second Group III nitride material and the one not intentionally doped AIN buffer layer is negative (the polarization difference between AlN and GaN is negative); wherein there is an energy band offset (see Ev at 2DHG in Fig. 1b) between valence bands of the not intentionally doped AIN buffer layer and the second epi-layer of the Group III nitride material and wherein an energy bandgap of the second epi-layer of the Group III nitride material being is smaller than an energy bandgap of AlN (see Ev and Ec at 2DHG in Fig. 1b) and the structure (b) further comprising a third Group III-N barrier layer deposited over a portion of the second epi-layer of the second Group III nitride material (Fig. 1A, 4 nm AlN barrier), wherein a thickness of the third Group III-N barrier layer and a composition and a thickness of a third Group III-N material are selected to form a two dimensional electron gas (2DEG) (Fig. 1A, 2DEG forms between 4 nm AlN barrier and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the second epi-layer of the second Group III nitride material and the third Group III-N barrier layer. Therefore, it would have been obvious to modify Liu modified by Bader modified by Gibb’s semiconductor component according to the teaching of Hickman (Figs. 1a-1b) in order to use an AlN/GaN/AlN quantum well HEMT as a platform for a high-power RF transistor (Hickman Abstract). Further, Hickman also teaches that Hickman’s AlN platform offers the possibility of integrating Bader’s p-Channel FET towards a nitride CMOS (Hickman I. Introduction) and Bader also notes the opportunity for monolithic integration with other AlN/Gan/AlN devices (Bader III. Conclusions and Benchmarking). Claim 29 is rejected under 35 U.S.C. 103 as being obvious over LIU et al. (Foreign Pub. No. CN 110474616 A (English translation attached)) in view of BADER et al. (“Gate-Recessed E-mode p-Channel HFET With High On-Current Based on GaN/AlN 2D Hole Gas”) and further in view of GIBB et al. (US Pub. No. 2019/0312027) and further in view of GOKHALE et al. (US Pub. No. 2021/0091746 A1). Regarding claim 29, Liu modified by Bader modified by Gibb teaches the semiconductor component of claim 1. However, Liu modified by Bader modified by Gibb does not explicitly tech that the first electrically conductive layer is an epi-deposited layer, the second electrically conductive layer is an epi-deposited layer, or both the first electrically conductive layer and the second electrically conductive layer are epi-deposited layers. However, Gokhale is a pertinent art that teaches the first electrically conductive layer (Fig. 9A, 902, ¶ [0088]) is an epi-deposited layer (¶ [0041] teaches that Gokhale’s transition metal nitride (TMN) layers are epitaxially grown), the second electrically conductive layer (Fig. 9A, 905, ¶ [0088]) is an epi-deposited layer, or both the first electrically conductive layer and the second electrically conductive layer are epi-deposited layers. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify at least the bottom electrode of Liu’s FBAR filter to be an epitaxially grown TMN layer according to the teaching of Gokhale (Fig. 9A) in order to improve acoustic performance and reduce system loss (Gokhale ¶ [0041]). Claims 23-25, 35-39 and 41 are rejected under 35 U.S.C. 103 as being obvious over LIU et al. (Foreign Pub. No. CN 110474616 A (English translation attached)) in view of BADER et al. (“Gate-Recessed E-mode p-Channel HFET With High On-Current Based on GaN/AlN 2D Hole Gas”) and further in view of GIBB et al. (US Pub. No. 2019/0312027) and further in view of YAN (Li Yan, W. Hong, Guang Hua, Jixin Chen, K. Wu and Tie Jun Cui, "Simulation and experiment on SIW slot array antennas," in IEEE Microwave and Wireless Components Letters, vol. 14, no. 9, pp. 446-448, Sept. 2004) and further in view of LI'17 (Y. Li, L. -A. Yang, H. Zou, H. -S. Zhang, X. -H. Ma and Y. Hao, "Substrate Integrated Waveguide Structural Transmission Line and Filter on Silicon Carbide Substrate," in IEEE Electron Device Letters, vol. 38, no. 9, pp. 1290-1293, Sept. 2017) and further in view of LI'19 (Yang Li, Xiao-Hua Ma, Lin-An Yang, Jin-Ping Ao, Yue Hao; Terahertz monolithic integrated waveguide transmission lines based on wide bandgap semiconductor materials. J. Appl. Phys. 21 April 2019). Regarding claim 23, Liu modified by Bader modified by Gibb teaches the semiconductor component of claim 1. However, Liu modified by Bader modified by Gibb does not explicitly teach an additional structure comprising: a third electrically conductive layer disposed on a portion of the first side of the substrate a fourth electrically conductive layer disposed on a portion of a second side of the substrate, at a location opposite to the third electrically conductive and a first plurality of metalized vias extending from the third electrically conductive layer at the first side of the substrate, through the substrate, and to the fourth electrically conductive layer at the second side of the substrate. However, Yan is a pertinent art that teaches a third electrically conductive layer (top surface of Yan Fig. 2, see II. Design Procedure, equivalent to element 210 in Fig.11) disposed on a portion of the first side of the substrate (the top surface of Yan’s substrate integrated waveguide would correspond to the top surface of Liu modified by Bader modified by Gibb’s substrate); a fourth electrically conductive layer substrate (bottom surface of Yan Fig. 2, see II. Design Procedure, equivalent to element 220 in Fig.11 of the Specification of the instant application) disposed on a portion of a second side of the substrate (the bottom surface of Yan’s substrate integrated waveguide would correspond to the bottom surface of Liu modified by Bader modified by Gibb’s substrate), at a location opposite to the third electrically conductive and a first plurality of metalized vias (vias in between top and bottom surface of Yan Fig. 2, see II. Design Procedure, equivalent to elements 240 in Fig.11 of the Specification of the instant application) extending from the third electrically conductive layer at the first side of the substrate , through the substrate, and to the fourth electrically conductive layer at the second side of the substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor component of Liu modified by Bader modified by Gibb by adding the SIW of Yan in order to directly integrate a small size, low loss waveguide for microwave and millimeter wave frequencies (Yan IV. Conclusion). Further, Monolithic Integrated Circuits using SIWs and III-nitride devices based on SiC substrates (see Introduction of Li’17) and Monolithic Integrated Circuits using GaN/SiC heterostructures and SIWs (see Introduction of Li’19) are known in the art. Regarding claim 24, Liu modified by Bader modified by Gibb modified by Yan teaches the semiconductor component of claim 23, and Yan teaches a first group of the first plurality of metalized vias (see left column of Vias in Yan Fig.2a, see II. Design Procedure, equivalent to left column of elements 240 in Fig.11 of the Specification of the instant application) is disposed along a first line and a second group of the first plurality of metalized vias (see right column of Vias in Yan Fig.2a, see II. Design Procedure, equivalent to right column of elements 240 in Fig.11 of Specification) is disposed along a second line laterally spaced apart from the first line. Regarding claim 25, Liu modified by Bader modified by Gibb modified by Yan teaches the semiconductor component of claim 24. However, Liu modified by Bader modified by Gibb modified by Yan does not explicitly teach a second plurality of metalized vias , extending from the third electrically conductive layer at the first side of the substrate, through the substrate, and to the fourth electrically conductive layer, the second plurality of metalized vias being disposed between the first group and the second group of the first plurality of metalized vias. However, Li’17 is a pertinent art that teaches a second plurality of metalized vias (middle portion of Vias in Figs. 1b & 4 of Li’17 between the top two rows of Vias, see II. Design and Fabrication, equivalent to elements 330, 350, and 360 in Fig.12 of the Specification of the instant application), extending from the third electrically conductive layer at the first side of the substrate (Li’ 17, II. Design and Fabrication teaches forming an Au layer on the bottom of Li’s substrate integrated waveguide), through the substrate, and to the fourth electrically conductive layer (Li’17, II. Design and Fabrication teaches forming a Ti/Au layer on the top of Li’s substrate integrated waveguide), the second plurality of metalized vias being disposed between the first group (Fig 1b, top row of Vias, corresponding to left column of Yan’s Vias) and the second group (Fig 1b, bottom row of Vias, corresponding to right column of Yan’s Vias) of the first plurality of metalized vias. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor component of Liu modified by Bader modified by Gibb modified by Yan by adding another plurality of Vias to the SIW of Yan according to the teaching of Li’17 in order to improve outband performance by forming SIW resonance cavities (see II. Design and Fabrication in Li’17). Regarding claim 35, Liu modified by Bader modified by Gibb modified by Yan teaches the semiconductor component of claim 24, and Yan teaches that the first group (see left column of Vias in Yan Fig.2a, see II. Design Procedure, equivalent to left column of elements 240 in Fig.11 of the Specification of the instant application) and the second group (see right column of Vias in Yan Fig.2a, see II. Design Procedure, equivalent to right column of elements 240 in Fig.11 of the Specification of the instant application) of the first plurality of metalized vias are configured to form, in combination with the third electrically conductive layer and the fourth electrically conductive layer, a first waveguide (Yan Fig.2a, II. Design Procedure). Regarding claim 36, Liu modified by Bader modified by Gibb modified by Yan teaches the semiconductor component of claim 35. However, Yan does not explicitly teach a second plurality of metalized vias, extending from the third electrically conductive layer at the first side of the substrate, through the substrate, and to the fourth electrically conductive layer, the second plurality of metalized vias comprising a first group of metalized vias disposed between the first group and the second group of the first plurality of metalized vias at a first end of the first waveguide and comprising a second group of metalized vias disposed between the first group and the second group of the first plurality of metalized vias at a second end of the first waveguide. However, Li’17 teaches a second plurality of metalized vias vias (middle third of Vias in Figs. 1b & 4 of Li’17 between the top two rows of Vias, see II. Design and Fabrication, equivalent to elements 350 in Fig.12 of the Specification of the instant application), extending from the third electrically conductive layer at the first side of the substrate (Li’ 17, II. Design and Fabrication teaches forming an Au layer on the bottom of Li’s substrate integrated waveguide), through the substrate, and to the fourth electrically conductive layer (Li’17, II. Design and Fabrication teaches forming a Ti/Au layer on the top of Li’s substrate integrated waveguide), the second plurality of metalized vias (Fig 1b, top row of Vias, corresponding to left column of Yan’s Vias) comprising a first group of metalized vias (Fig. 1b, left group of Vias in between the top and bottom rows of Vias, equivalent to elements 330 of Fig. 12 of the Specification of the instant application) disposed between the first group and the second group of the first plurality of metalized vias at a first end of the first waveguide and comprising a second group of metalized vias (Fig. 1b, right group of Vias in between the top and bottom rows of Vias, equivalent to elements 360 of Fig. 12 of the Specification of the instant application) disposed between the first group and the second group of the first plurality of metalized vias at a second end of the first waveguide. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor component of Liu modified by Bader modified by Gibb modified by Yan by adding another plurality of Vias to the SIW of Yan according to the teaching of Li’17 in order to improve outband performance by forming SIW resonance cavities (see II. Design and Fabrication in Li’17). Regarding claim 37, Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 teaches that the first group (Fig. 1b, left group of Vias in between the top and bottom rows of Vias, equivalent to elements 330 of Fig. 12 of the Specification of the instant application) of the second plurality of metalized vias are disposed to close the first end of the first waveguide (Fig. 1b), save for a first opening configured to receive an input of electromagnetic radiation (Fig. 1b, opening in left group of Vias in between the top and bottom rows), and wherein the second group (Fig. 1b, right group of Vias in between the top and bottom rows of Vias, equivalent to elements 360 of Fig. 12 of the Specification of the instant application) of the second plurality of metalized vias are disposed to close the second end of the first waveguide, save for a second opening (Fig. 1b, opening in right group of Vias in between the top and bottom rows) configured to receive an output of electromagnetic radiation, to define a first cavity resonator (Figs. 1b & 4, cavity resonator 1, see III. Results and Discussion). Regarding claim 38, Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 teaches the semiconductor component of claim 36, and Li’17 teaches that the first group (Fig. 1b, left group of Vias in between the top and bottom rows of Vias, equivalent to elements 330 of Fig. 12 of the Specification of the instant application) of the second plurality of metalized vias are disposed to close the first end of the first waveguide, save for an opening configured to receive an input of electromagnetic radiation (Fig. 1b, opening in left group of Vias in between the top and bottom rows of Vias), wherein the second group (Fig. 1b, right group of Vias in between the top and bottom rows of Vias, equivalent to elements 360 of Fig. 12 of the Specification of the instant application) of the second plurality of metalized vias are disposed to close the second end of the first waveguide, save for an opening configured to receive an output of electromagnetic radiation (Fig. 1b, opening in right group of Vias in between the top and bottom rows),wherein the second plurality of metalized vias comprises a third group of metalized vias (Fig. 1b, middle group of Vias in between the top and bottom rows of Vias, equivalent to elements 350 of Fig. 12 of the Specification of the instant application) disposed between the first group and the second group of the first plurality of metalized vias and between the first group and the second group of the second plurality of metalized vias to define a first cavity resonator (Figs. 1b & 4, cavity resonator 1, see III. Results and Discussion) and a second cavity resonator (Figs. 1b & 4, cavity resonator 2, see III. Results and Discussion). Regarding claim 39, Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 teaches the semiconductor component of claim 38, and Li’17 teaches that the third group of metalized vias (Fig. 1b, middle group of Vias in between the top and bottom rows of Vias, equivalent to elements 350 of Fig. 12 of the Specification of the instant application) disposed between the first group and the second group of the first plurality of metalized vias defines an opening (Figs. 1b & 4, opening in middle group of Vias in between the top and bottom rows of Vias) enabling communication between the first cavity resonator and the second cavity resonator. Regarding claim 41, Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 teaches the semiconductor component of claim 38, and Li’17 teaches that the additional structure comprising the first plurality of metalized vias (Fig 1b, top row of Vias, corresponding to left column of Yan’s Vias) and the second plurality of metalized vias (Fig 1b, bottom row of Vias, corresponding to right column of Yan’s Vias) define a substrate integrated waveguide (SIW) (Li’17, see II. Design and Fabrication). Claims 40 and 42-46 are rejected under 35 U.S.C. 103 as being obvious over LIU et al. (Foreign Pub. No. CN 110474616 A (English translation attached)) in view of BADER et al. (“Gate-Recessed E-mode p-Channel HFET With High On-Current Based on GaN/AlN 2D Hole Gas”) and further in view of GIBB et al. (US Pub. No. 2019/0312027) and further in view of YAN (Li Yan, W. Hong, Guang Hua, Jixin Chen, K. Wu and Tie Jun Cui, "Simulation and experiment on SIW slot array antennas," in IEEE Microwave and Wireless Components Letters, vol. 14, no. 9, pp. 446-448, Sept. 2004) and further in view of LI'17 (Y. Li, L. -A. Yang, H. Zou, H. -S. Zhang, X. -H. Ma and Y. Hao, "Substrate Integrated Waveguide Structural Transmission Line and Filter on Silicon Carbide Substrate," in IEEE Electron Device Letters, vol. 38, no. 9, pp. 1290-1293, Sept. 2017) and further in view of LI'19 (Yang Li, Xiao-Hua Ma, Lin-An Yang, Jin-Ping Ao, Yue Hao; Terahertz monolithic integrated waveguide transmission lines based on wide bandgap semiconductor materials. J. Appl. Phys. 21 April 2019) and further in view of HICKMAN et al. (A. Hickman et al., "High Breakdown Voltage in RF AlN/GaN/AlN Quantum Well HEMTs," in IEEE Electron Device Letters, vol. 40, no. 8, pp. 1293-1296, Aug. 2019). Regarding claim 40, Liu modified by Bader modified by Gibb modified by Yan teaches the semiconductor component of claim 23, structure (a) defines a high-current p-type GaN/AlN field-effect transistor (FET) (Bader Abstract teaches that Bader’s device is a GaN/AlN wide bandgap p-FET), wherein structure (c) defines an AlN bulk acoustic wave filter (Liu Fig. 5, ¶¶ [0006] - [0009 & [0041] teaches that Liu’s structure is a BAW on an AlN layer). However, Liu modified by Bader modified by Gibb modified by Yan does not explicitly teach that structure (b) defines an AIN/GaN/AIN HEMT. However, Hickman is a pertinent art that teaches a second epi-layer of a second Group III nitride material (Fig. 1a, 30 nm GaN channel) epitaxially grown on the one not intentionally doped AIN buffer layer (II. Device Fabrication teaches AlN/GaN/AlN epitaxial structures grown by plasma-assisted molecular beam epitaxy (MBE) on semi insulating 6H silicon carbide substrates. There is no mention of the AlN buffer layer in Figure 1 being intentionally doped); and comprising a 2D hole gas (2DHG forms between AlN buffer and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the one not intentionally doped AIN buffer layer and the second epi-layer of the second Group III nitride material, wherein a difference between a normal component of a polarization of the second epi-layer of the second Group III nitride material and the one not intentionally doped AIN buffer layer is negative (the polarization difference between AlN and GaN is negative); wherein there is an energy band offset (see Ev at 2DHG in Fig. 1b) between valence bands of the not intentionally doped AIN buffer layer and the second epi-layer of the Group III nitride material and wherein an energy bandgap of the second epi-layer of the Group III nitride material being is smaller than an energy bandgap of AlN (see Ev and Ec at 2DHG in Fig. 1b) and the structure (b) further comprising a third Group III-N barrier layer deposited over a portion of the second epi-layer of the second Group III nitride material (Fig. 1A, 4 nm AlN barrier), wherein a thickness of the third Group III-N barrier layer and a composition and a thickness of a third Group III-N material are selected to form a two dimensional electron gas (2DEG) (Fig. 1A, 2DEG forms between 4 nm AlN barrier and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the second epi-layer of the second Group III nitride material and the third Group III-N barrier layer. Therefore, it would have been obvious to modify Liu modified by Bader modified by Gibb’s semiconductor component according to the teaching of Hickman (Figs. 1a-1b) in order to use an AlN/GaN/AlN quantum well HEMT as a platform for a high-power RF transistor (Hickman Abstract). Further, Hickman also teaches that Hickman’s AlN platform offers the possibility of integrating Bader’s p-Channel FET towards a nitride CMOS (Hickman I. Introduction) and Bader also notes the opportunity for monolithic integration with other AlN/Gan/AlN devices (Bader III. Conclusions and Benchmarking). Regarding claim 42, Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 teaches the semiconductor component of claim 41. However Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 does not explicitly teach that the structure (a), structure (b), structure (c), and the additional structure define an integrated monolithic RF signal- processing device. However, Hickman is a pertinent art that teaches a second epi-layer of a second Group III nitride material (Fig. 1a, 30 nm GaN channel) epitaxially grown on the one not intentionally doped AIN buffer layer (II. Device Fabrication teaches AlN/GaN/AlN epitaxial structures grown by plasma-assisted molecular beam epitaxy (MBE) on semi insulating 6H silicon carbide substrates. There is no mention of the AlN buffer layer in Figure 1 being intentionally doped); and comprising a 2D hole gas (2DHG forms between AlN buffer and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the one not intentionally doped AIN buffer layer and the second epi-layer of the second Group III nitride material, wherein a difference between a normal component of a polarization of the second epi-layer of the second Group III nitride material and the one not intentionally doped AIN buffer layer is negative (the polarization difference between AlN and GaN is negative); wherein there is an energy band offset (see Ev at 2DHG in Fig. 1b) between valence bands of the not intentionally doped AIN buffer layer and the second epi-layer of the Group III nitride material and wherein an energy bandgap of the second epi-layer of the Group III nitride material being is smaller than an energy bandgap of AlN (see Ev and Ec at 2DHG in Fig. 1b) and the structure (b) further comprising a third Group III-N barrier layer deposited over a portion of the second epi-layer of the second Group III nitride material (Fig. 1A, 4 nm AlN barrier), wherein a thickness of the third Group III-N barrier layer and a composition and a thickness of a third Group III-N material are selected to form a two dimensional electron gas (2DEG) (Fig. 1A, 2DEG forms between 4 nm AlN barrier and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the second epi-layer of the second Group III nitride material and the third Group III-N barrier layer. Therefore, it would have been obvious to modify Liu modified by Bader modified by Gibb’s semiconductor component according to the teaching of Hickman (Figs. 1a-1b) in order to use an AlN/GaN/AlN quantum well HEMT as a platform for a high-power RF transistor (Hickman Abstract). Further, Hickman also teaches that Hickman’s AlN platform offers the possibility of integrating Bader’s p-Channel FET towards a nitride CMOS (Hickman I. Introduction) and Bader also notes the opportunity for monolithic integration with other AlN/Gan/AlN devices (Bader III. Conclusions and Benchmarking). Furthermore, it would be obvious to one of ordinary skill in the art that Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 modified by Hickman’s semiconductor component would define an integrated monolithic RF-signal processing device. Regarding claim 43, Liu modified by Bader modified by Gibb modified by Yan teaches the semiconductor component of claim 23. However, Liu modified by Bader modified by Gibb modified by Yan does not explicitly teach that the second epi-layer of structure (a) and the second epi-layer of structure (b) comprise a same epi-layer, and wherein the second epi-layer of structure (a) and structure (b) comprise GaN and defines a GaN channel layer. However, Hickman is a pertinent art that teaches a second epi-layer of a second Group III nitride material (Fig. 1a, 30 nm GaN channel) epitaxially grown on the one not intentionally doped AIN buffer layer (II. Device Fabrication teaches AlN/GaN/AlN epitaxial structures grown by plasma-assisted molecular beam epitaxy (MBE) on semi insulating 6H silicon carbide substrates. There is no mention of the AlN buffer layer in Figure 1 being intentionally doped); and comprising a 2D hole gas (2DHG forms between AlN buffer and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the one not intentionally doped AIN buffer layer and the second epi-layer of the second Group III nitride material, wherein a difference between a normal component of a polarization of the second epi-layer of the second Group III nitride material and the one not intentionally doped AIN buffer layer is negative (the polarization difference between AlN and GaN is negative); wherein there is an energy band offset (see Ev at 2DHG in Fig. 1b) between valence bands of the not intentionally doped AIN buffer layer and the second epi-layer of the Group III nitride material and wherein an energy bandgap of the second epi-layer of the Group III nitride material being is smaller than an energy bandgap of AlN (see Ev and Ec at 2DHG in Fig. 1b) and the structure (b) further comprising a third Group III-N barrier layer deposited over a portion of the second epi-layer of the second Group III nitride material (Fig. 1A, 4 nm AlN barrier), wherein a thickness of the third Group III-N barrier layer and a composition and a thickness of a third Group III-N material are selected to form a two dimensional electron gas (2DEG) (Fig. 1A, 2DEG forms between 4 nm AlN barrier and 30 nm GaN channel in Figure 1a. See Fig. 1b) at a heterojunction between the second epi-layer of the second Group III nitride material and the third Group III-N barrier layer. Therefore, it would have been obvious to modify Liu modified by Bader modified by Gibb’s semiconductor component according to the teaching of Hickman (Figs. 1a-1b) in order to use an AlN/GaN/AlN quantum well HEMT as a platform for a high-power RF transistor (Hickman Abstract). Further, Hickman also teaches that Hickman’s AlN platform offers the possibility of integrating Bader’s p-Channel FET towards a nitride CMOS (Hickman I. Introduction) and Bader also notes the opportunity for monolithic integration with other AlN/Gan/AlN devices (Bader III. Conclusions and Benchmarking). Furthermore, it would be obvious to one of ordinary skill in the art that Liu modified by Bader modified by Gibb modified by Yan modified by Li’17 modified by Hickman’s semiconductor component would define an integrated monolithic RF-signal processing device. Furthermore, when modifying the AlN platform towards a nitride CMOS according to the teaching of Hickman (Hickman I. Introduction), it would be it would be obvious to one of ordinary skill in the art to modify Liu modified by Bader modified by Gibb modified by Yan modified by Hickman’s semiconductor component to have a same epi-layer, and a same GaN channel layer for both of Bader and Hickman’s devices because both devices require an GaN channel layer on an epitaxial AlN layer, and doing so would reduce manufacturing costs. Regarding claim 44, Liu modified by Bader modified by Yan modified by Li’17 modified by Hickman teaches the semiconductor component of claim 43, and Hickman teaches that a thickness of the GaN channel layer (Fig. 1a, II. Device Fabrication, teaches that Hickman’s GaN channel layer is 30nm) is between about 20-200nm, wherein the third Group III-N barrier layer (Fig. 1a, II. Device Fabrication, teaches that Hickman’s barrier layer is AlN) of structure (b) comprises AIN, InAIN,or AIGaN,wherein a thickness of the third Group III-N barrier layer is between about 1.4 nm - 20 nm (Fig. 1a, II. Device Fabrication, teaches that Hickman’s barrier layer is 4nm), and wherein a thickness of the GaN channel layer and a thickness of the third Group III-N barrier layer are selected to yield a high-density 2DEG of between about 0.5-4x10^13cm-2 (Hickman II. Device Fabrication teaches that Hickman’s device forms a 2DEG of 2.9 · 10^13 cm−2). Regarding claim 45, Liu modified by Bader modified by Yan modified by Li’17 modified by Hickman teaches the semiconductor component of claim 44, and Hickman teaches that the third Group III-N barrier layer of structure (b) is AIN (Fig. 1a, II. Device Fabrication, teaches that Hickman’s barrier layer is AlN), wherein a thickness of the AlN barrier between about 1.4 nm - 4 nm (Fig. 1a, II. Device Fabrication, teaches that Hickman’s barrier layer is 4nm), and wherein a gate length of structure (b) is about 10nm - 600nm (Hickman II. Device Fabrication teaches that Hickman’s device had gate lengths as short as 40 nm). Regarding claim 46, Liu modified by Bader modified by Yan modified by Li’17 modified by Hickman teaches the semiconductor component of claim 45, and Hickman teaches that a ratio of a gate length to the thickness of the third Group III-N barrier layer is greater than about five (Hickman II. Device Fabrication teaches a gate length of 40nm and barrier layer thickness of 4 nm, which is a ratio of greater than 5). Cited Prior Art The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHYS P. SHEKER whose telephone number is (703)756-1348. The examiner can normally be reached Monday - Friday 7:30 am to 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.P.S./ Examiner, Art Unit 2813 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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Prosecution Timeline

Dec 17, 2021
Application Filed
May 13, 2024
Non-Final Rejection — §103
Jul 31, 2024
Response Filed
Oct 10, 2024
Final Rejection — §103
Dec 03, 2024
Examiner Interview Summary
Dec 03, 2024
Applicant Interview (Telephonic)
Dec 04, 2024
Response after Non-Final Action
Dec 12, 2024
Examiner Interview (Telephonic)
Dec 12, 2024
Response after Non-Final Action
Jan 14, 2025
Request for Continued Examination
Jan 16, 2025
Response after Non-Final Action
Feb 28, 2025
Non-Final Rejection — §103
Jun 18, 2025
Applicant Interview (Telephonic)
Jun 18, 2025
Examiner Interview Summary
Jul 05, 2025
Response Filed
Oct 01, 2025
Final Rejection — §103
Feb 03, 2026
Request for Continued Examination
Feb 14, 2026
Response after Non-Final Action
Mar 10, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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5-6
Expected OA Rounds
85%
Grant Probability
91%
With Interview (+5.8%)
3y 3m
Median Time to Grant
High
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