DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 July 2025 has been entered.
Claims 1, 10, 13, and 21 have been amended. Claims 4, 6, 9, and 16 were previously cancelled. Claims 1-3, 5, 7, 8, 10-15, and 17-24 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5, 7-8, 10-15, 17-22, and 24 rejected under 35 U.S.C. 103 as being unpatentable over Lilak et al. US PGPUB 20200266218 (hereinafter Lilak) in view of Chu et al. US PGPUB 20230010502 (hereinafter Chu) and Chen et al. DE-102020119609-A1 (hereinafter Chen).
Examiner modified notations: Lilak uses 122 to denote gate dielectric elements throughout the IC structure 100. Consistent with labeling of other elements by Lilak:
Dielectric elements in lower portion 130-1 will hereinafter be labeled 122-1.
Dielectric elements in upper portion 130-2 will hereinafter be labeled 122-2.
Regarding claim 1, Lilak discloses (figs. 1-2, 14A-14B) an integrated circuit comprising:
a lower device portion (130-1 ¶18, 20-21, 24) including first body of semiconductor material (106-1 ¶20, 32, 47) extending horizontally between first source and drain regions (118-1 ¶21, 45);
a first gate structure (122-1 and 124-1 ¶23-24, 26-27) around the first body (106-1), the first gate structure (122-1 and 124-1) including a first gate electrode (124-1) and a first gate dielectric (122-1), the first gate dielectric (122-1) between the first body (106-1) and the first gate electrode (124-1) (figs. 1A-1B);
an upper device portion (130-2 ¶18, 20-21, 24, 32) above the lower device portion (130-1), the upper device portion (130-2) including a second body of semiconductor material (106-2 ¶20, 32, 47) spaced from the first body (130-1, fig. 1B) and extending horizontally between second source and drain regions (118-2 ¶21); and
a second gate structure (122-2 and 124-2 ¶23-24, 26-27) around the second body (106-2), the second gate structure (122-2 and 124-2) including a second gate electrode (124-2) and a second gate dielectric (122-2), the second gate dielectric (122) between the second body (106-2) and the second gate electrode (124-2);
wherein the first gate dielectric (122-1) is compositionally distinct from the second gate dielectric (122-2).
Lilak discloses distinct compositions for 122-1 and 122-2 (¶23, “Although a single ‘gate dielectric 122’ is used to refer to the gate dielectric present in all of the device strata 130 of the IC structures 100 disclosed herein, the material composition of the gate dielectric 122 used in different ones of the device strata 130 may differ, as desired. The gate dielectric 122 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.”)
Lilak does not disclose wherein the first gate dielectric is compositionally distinct from the second gate dielectric,
and wherein the first gate dielectric includes a first native oxide directly on the first body and a first high-k dielectric on the first native oxide, and wherein the second gate dielectric includes a second native oxide directly on the second body and a second high-k dielectric on the second native oxide, and
wherein a dipole species has a first peak concentration at an interface between the first high-k dielectric and the first native oxide and a second peak concentration, different from the first peak concentration, at an interface between the second high-k dielectric and the second native oxide.
In the same field of endeavor, Chu discloses (figs. 1A-2B) wherein the first gate dielectric includes a first native oxide (110a, Chu ¶28-30) directly on the first body (108a, Chu ¶25-28) and a first high-k dielectric (118a, Chu ¶44-45) on the first native oxide (Chu fig. 1F), and wherein the second gate dielectric includes a second native oxide (110b, Chu ¶28-30) directly on the second body (108b, Chu ¶25-28) and a second high-k dielectric 118b, Chu ¶44-45) on the second native oxide (Chu fig. 1F), and wherein a dipole species has a peak concentration (206 Chu fig. 2B ¶67) at an interface between the first high-k dielectric and the first native oxide and/or at an interface between the second high-k dielectric and the second native oxide (fig. 2A-2B, where the peak concentration is at the interface between 110a/110b and 118a/118b).
It would have been obvious to one of ordinary skill in the art at the time of filing to form a native silicon oxide interface layer 110 (Chu ¶29) as the) on a silicon body 108 (Chu ¶25) as disclosed by Chu, providing a low-cost dielectric interface with the desired thickness, further improving the density of transistors per unit area.
It would have been obvious to one of ordinary skill in the art at the time of filing to apply a dipole-inducing layer as disclosed by Chu, providing a peak in dipole concentration between the native oxide interface and the high-k dielectric layer, improving device performance by tuning carrier mobility and threshold voltages to desired values.
Lilak in view of Chu does not explicitly disclose wherein a dipole species has a first peak concentration at an interface of the first high-k dielectric and a second peak concentration, different from the first peak concentration, at an interface of the second high-k dielectric.
In the same field of endeavor, Chen discloses (fig. 1-23) wherein a dipole species has a first peak concentration at an interface (210A) of the first high-k dielectric and a second peak concentration, different from the first peak concentration, at an interface of the second high-k dielectric. (Chen fig. 7A-7C, 9A-9C, ¶31-39, where gate dielectric structure interface layers 210 are made with different dipole concentrations in 210A by varying depth from dipole layer 300 as shown in fig. 7A-7C and the peak is located at the interface, Chen ¶35, or by using materials, Chen ¶27). Chen discloses additional gate structures with interface layers (840) similar to those of layer 210, which provide dipole concentrations that can differ in dipole concentration from other IL 840 layers similar to differences in 210A for the different gate structures 200A-200F as well as 840 differing in concentration from the corresponding IL 210 layers (Chen ¶80-84).
It would have been obvious to one of ordinary skill in the art at the time of filing to apply different dipole concentrations as disclosed by Chen, improving device performance with increased flexibility in tuning the cutoff voltage and reduced gate resistance (Chen ¶8) for different gate structures within the overall device.
Regarding claim 2, Lilak, Chu, and Chen disclose the integrated circuit of claim 1,
wherein the first gate electrode (124-1, Lilak ¶23-24, 26-27) is compositionally distinct from the second gate electrode (124-2, Lilak ¶23-24, 26-27).
Lilak discloses (Lilak ¶24) “In some embodiments, the material composition of the gate metal 124 used in different ones of the device strata 130 may be different; for example, FIG. 1 illustrates a gate metal 124-1 in the device stratum 130-1 and a gate metal 124-2 in the device stratum 130-2.”
Regarding claim 5, Lilak, Chu, and Chen disclose the integrated circuit of claim 1,
wherein the first body (106-1, Lilak ¶20, 32, 47) is compositionally distinct from the second body (106-2, Lilak ¶20, 32, 47). Lilak discloses (Lilak ¶20) “In some embodiments, the material composition of the channel material 106 used in different ones of the device strata 130 may be different.”
Regarding claim 7, Lilak, Chu, and Chen disclose the integrated circuit of claim 1,
wherein the dipole species comprises one or more of aluminum, barium, cerium, chromium, cobalt, dysprosium, erbium, europium, gadolinium, holmium, lanthanum, lutetium, magnesium, manganese, molybdenum, neodymium, niobium, praseodymium, samarium, scandium, strontium, terbium, thulium, titanium, ytterbium, or yttrium (Lilak ¶23).
Regarding claim 8, Lilak and Chu disclose the integrated circuit of claim 1.
Lilak discloses first and second gate dielectrics with differing compositions (122-1 and 122-2 ¶23-24, 26-27). Chu discloses wherein the dipole species is in both the first gate dielectric and the second gate dielectric (Chu ¶31), and wherein a concentration of the dipole species in the first gate dielectric is different from a concentration of the dipole species in the second gate dielectric (Chu fig. 2A-2B, where Chu discloses different dipole concentrations that each peak at the native oxide and high-k dielectric interface).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to apply different concentrations of dipole dopants in order to provide the ability to precisely adjust threshold voltages of the different transistors, allowing for better device performance and scaling.
Regarding claim 10, Lilak and Chu disclose the integrated circuit of claim 7.
Lilak also discloses distinct compositions for 122-1 and 122-2 (¶23). Chu discloses the integrated circuit comprising a layer comprising titanium and nitrogen between the first gate dielectric and the first gate electrode (Chu ¶52, where the gate metal layer “124 may include relatively thin glue layers, barrier layers, or work function layers initially deposited on the high-K dielectric layer 118 a/118 b. These initial gate metal layers can include one or more of titanium nitride, tantalum nitride,”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to apply the interface layers disclosed by Chu on the high-k dielectric layer, improving device performance by providing increased control on the threshold voltage.
Regarding claim 11, Lilak, Chu, and Chen disclose the integrated circuit of claim 1,
wherein the first body (106-1, Lilak ¶20, 32, 47) is one of a first plurality of bodies (Lilak fig. 14A-B show many 106-1 elements) and the second body (106-2, Lilak ¶20, 32, 47) is one of a second plurality of bodies (Lilak fig. 14A-B show many 106-2 elements), the first and second pluralities of bodies selected from nanowires, nanoribbons, and nanosheets. Lilak discloses (Lilak ¶20), “the channel material 106-1 of the device stratum 130-1 as including multiple semiconductor wires (e.g., nanowires or nanoribbons), as does the channel material 106-2 of the device stratum 130-2.”
Regarding claim 12, Lilak, Chu, and Chen disclose the integrated circuit of claim 1,
wherein one of the lower device portion (130-1, Lilak ¶18, 20-21, 24) or the upper device portion (130-2, Lilak ¶18, 20-21, 24, 32) is configured as an n-MOS transistor device and the other of the lower device portion and the upper device portion is configured as a p-MOS transistor device. Lilak discloses (Lilak ¶27) gate metals (124) for different device strata “may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor of which it is a part is to be a PMOS or an NMOS transistor.”
Regarding claim 13, Lilak discloses an integrated circuit comprising:
at least one first body (106-1, Lilak ¶20, 32, 47) of semiconductor material extending horizontally between and connecting a first source and a first drain (118-1, Lilak ¶21, 45);
at least one second body (106-2, Lilak ¶20, 32, 47) of semiconductor material extending horizontally between and connecting a second source and a second drain (118-2, Lilak ¶21), the at least one second body (106-2) arranged with the at least one first body (106-1) in a spaced-apart vertical stack (Lilak fig. 1B);
a first gate structure (122-1 and 124-1, Lilak ¶23-24, 26-27) wrapped around the at least one first body (106-1), the first gate (122-1 and 124-1) structure comprising a first gate electrode (124-1) and a first gate dielectric (122-1) wherein the first gate dielectric (122-1) is between the first gate electrode (124-1) and the at least one first body (106-1) (Lilak fig. 1A-1B); and
a second gate structure (122-2 and 124-2, Lilak ¶23-24, 26-27) wrapped around the at least one second body (106-2), the second gate structure (122-2 and 124-2) comprising a second gate electrode (124-2) and a second gate dielectric (122-2) wherein the second gate dielectric (122-2) is between the second gate electrode (122-4) and the at least one second body (106-2) (Lilak figs. 1A-1B);
wherein the first gate dielectric is compositionally distinct from the second gate dielectric; (Lilak discloses distinct compositions for 122-1 and 122-2 (Lilak ¶23, “Although a single ‘gate dielectric 122’ is used to refer to the gate dielectric present in all of the device strata 130 of the IC structures 100 disclosed herein, the material composition of the gate dielectric 122 used in different ones of the device strata 130 may differ, as desired. The gate dielectric 122 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.”),
wherein the at least one first body and the at least one second body are selected from a nanowire, nanoribbon, or nanosheet. Lilak discloses (Lilak ¶20), “the channel material 106-1 of the device stratum 130-1 as including multiple semiconductor wires (e.g., nanowires or nanoribbons), as does the channel material 106-2 of the device stratum 130-2.”
Lilak does not disclose wherein the first gate dielectric includes a first native oxide directly on the first body and a first high-k dielectric on the first native oxide, and wherein the second gate dielectric includes a second native oxide directly on the second body and a second high-k dielectric on the second native oxide, and wherein a dipole species has a peak concentration at an interface between the first high-k dielectric and the first native oxide at an interface between the second high-k dielectric and the second native oxide.
In the same field of endeavor, Chu discloses (figs. 1A-2B) wherein the first gate dielectric includes a first native oxide (110a, Chu ¶28-30) directly on the first body (108a, Chu ¶25-28) and a first high-k dielectric (118a, Chu ¶44-45) on the first native oxide (Chu fig. 1F), and wherein the second gate dielectric includes a second native oxide (110b, Chu ¶28-30) directly on the second body (108b, Chu ¶25-28) and a second high-k dielectric 118b, Chu ¶44-45) on the second native oxide (Chu fig. 1F), and wherein a dipole species has a peak concentration at an interface between the first high-k dielectric and the first native oxide at an interface between the second high-k dielectric and the second native oxide (fig. 2A-2B, where the peak concentration is at the interface between 110a/110b and 118a/118b).
Lilak in view of Chu does not explicitly disclose wherein a dipole species has a first peak concentration at an interface of the first high-k dielectric and a second peak concentration, different from the first peak concentration, at an interface of the second high-k dielectric.
In the same field of endeavor, Chen discloses (fig. 1-23) wherein a dipole species has a first peak concentration at an interface (210A) of the first high-k dielectric and a second peak concentration, different from the first peak concentration, at an interface of the second high-k dielectric. (Chen fig. 7A-7C, 9A-9C, ¶31-39, where gate dielectric structure interface layers 210 are made with different dipole concentrations in 210A by varying depth from dipole layer 300 as shown in fig. 7A-7C and the peak is located at the interface, Chen ¶35, or by using materials, Chen ¶27). Chen discloses additional gate structures with interface layers (840) similar to those of layer 210, which provide dipole concentrations that can differ in dipole concentration from other IL 840 layers similar to differences in 210A for the different gate structures 200A-200F as well as 840 differing in concentration from the corresponding IL 210 layers (Chen ¶80-84).
It would have been obvious to one of ordinary skill in the art at the time of filing to apply different dipole concentrations as disclosed by Chen, improving device performance with increased flexibility in tuning the cutoff voltage and reduced gate resistance (Chen ¶8) for different gate structures within the overall device.
Regarding claim 14, Lilak, Chu, and Chen disclose the integrated circuit of claim 13,
wherein the first gate electrode (124-1, Lilak ¶23-24, 26-27) is compositionally distinct from the second gate electrode (124-2, Lilak ¶23-24, 26-27).
Lilak discloses (Lilak ¶24) “In some embodiments, the material composition of the gate metal 124 used in different ones of the device strata 130 may be different; for example, FIG. 1 illustrates a gate metal 124-1 in the device stratum 130-1 and a gate metal 124-2 in the device stratum 130-2.”
Regarding claim 15, Lilak, Chu, and Chen disclose the integrated circuit of claim 13,
wherein a composition of the dipole species in the first gate dielectric (122-1, Lilak ¶23-24, 26-27) is different from a composition of the dipole species in the second gate dielectric (122-2, Lilak ¶23-24, 26-27). Lilak discloses (¶23) “material composition of the gate dielectric 122 used in different ones of the device strata 130 may differ,” as well as different materials that could act as dipole species of different compositions between the first and second dielectric elements, such as barium strontium titanium oxide and barium titanium oxide which both exhibit a dipole moment.
Regarding claim 17, Lilak, Chu, and Chen disclose the integrated circuit of claim 13,
wherein the dipole species is selected from aluminum, barium, cerium, chromium, cobalt, dysprosium, erbium, europium, gadolinium, holmium, lanthanum, lutetium, magnesium, manganese, molybdenum, neodymium, niobium, praseodymium, samarium, scandium, strontium, terbium, thulium, titanium, ytterbium, or yttrium. The example dipole species above (Lilak ¶23) select barium, strontium, and titanium from this list.
Regarding claim 18, Lilak, Chu, and Chen disclose the integrated circuit of claim 13,
comprising a stacked transistor structure including at least one of a n-channel transistor and at least one of a p-channel transistor. Lilak discloses (Lilak ¶24) “the material composition of the gate metal 124 used in different ones of the device strata 130 may be different” and (Lilak ¶27) “may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor of which it is a part is to be a PMOS or an NMOS transistor.”
Regarding claim 19, Lilak, Chu, and Chen disclose the integrated circuit of claim 13. Lilak discloses an integrated circuit die (1502) comprising the integrated circuit (100 or suitable equivalent) of claim 13 (Lilak figs. 20-21 ¶19).
Regarding claim 20, Lilak, Chu, and Chen disclose the integrated circuit of claim 19. Lilak further discloses a processor comprising the integrated circuit die (1502) of claim 19 (Lilak, fig. 24, ¶76-78).
Regarding claim 21, Lilak, Chu, and Chen disclose the integrated circuit of claim 13.
Chu discloses an alternate embodiment wherein the dipole species is only in the first gate dielectric (Chu ¶50), the integrated circuit comprising a layer comprising titanium and nitrogen between the first gate dielectric and the first gate electrode (Chu ¶52, where the gate metal layer “124 may include relatively thin glue layers, barrier layers, or work function layers initially deposited on the high-K dielectric layer 118 a/118 b. These initial gate metal layers can include one or more of titanium nitride, …”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to apply the dipole doping of Chu to only the first gate dielectric, providing improved device performance by providing the ability to precisely adjust threshold voltages while not utilizing this method on a second gate dielectric that could be used a high voltage transistor (Lilak ¶40), providing reduced manufacturing time and expense.
Regarding claim 22, Lilak, Chu, and Chen disclose the integrated circuit of claim 13,
Chu discloses wherein the dipole species is in both the first gate dielectric and the second gate dielectric (Chu ¶31), and wherein a concentration of the dipole species in the first gate dielectric is different from a concentration of the dipole species in the second gate dielectric (Chu fig. 2A-2B, where Chu discloses different dipole concentrations that each peak at the native oxide and high-k dielectric interface).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to apply different concentrations of dipole dopants in order to provide the ability to precisely adjust threshold voltages of the different transistors, allowing for better device performance and scaling.
Regarding claim 24, Lilak, Chu, and Chen disclose the integrated circuit of claim 1. Chu further discloses further comprising: a first layer comprising titanium and nitrogen between the first gate dielectric and the first gate electrode; and a second layer comprising tantalum and nitrogen between the first layer and the gate electrode. (Chu ¶52, where the gate metal layer “124 may include relatively thin glue layers, barrier layers, or work function layers initially deposited on the high-K dielectric layer 118 a/118 b. These initial gate metal layers can include one or more of titanium nitride, tantalum nitride, …”).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to apply the interface layers disclosed by Chu on the high-k dielectric layer, improving device performance by providing increased control on the threshold voltage.
Claims 3 and 23 rejected under 35 U.S.C. 103 as being unpatentable over Lilak, Chu, and Chen in view of Ching et al. US PGPUB No. 20190067120 (hereinafter Ching).
Regarding claim 3, Lilak, Chu, and Chen disclose the integrated circuit of claim 2.
Lilak and Chu do not disclose the first and second gate electrode separated by an isolation layer, as (Lilak ¶26) “the gate metal 124-1 makes contact with the gate metal 124-2 in locations lateral to the dielectric material 108, as shown in FIG. 1B.”
In the same field of endeavor, Ching discloses (figs. 7A-7C) gate isolation structures (1202a with 604a and 1202b with 604b) that separate different gate electrode portions (1108 surrounding 504a/504b separated from 1108 surrounding 504c/504d) (Ching ¶79).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to include an isolation structure of Ching applied between the first gate electrode and the second gate electrode of Lilak in view of Chu, as the use of the isolation structures would reduce metal gate structure material used, providing reduced parasitic capacitance (Ching ¶36).
Regarding claim 23, Lilak, Chu, and Chen disclose the integrated circuit of claim 14.
Lilak and Chu do not disclose comprising a layer of isolation material between the first gate electrode and the second gate electrode, as (Lilak ¶26) “the gate metal 124-1 makes contact with the gate metal 124-2 in locations lateral to the dielectric material 108, as shown in FIG. 1B.”
In the same field of endeavor, Ching discloses (figs. 7A-7C) gate isolation structures (1202a with 604a and 1202b with 604b) that separate different gate electrode portions (1108 surrounding 504a/504b separated from 1108 surrounding 504c/504d) (Ching ¶79).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to include an isolation structure of Ching applied between the first gate electrode and the second gate electrode of Lilak in view of Chu, as the use of the isolation structures would reduce metal gate structure material used, providing reduced parasitic capacitance (Ching ¶36).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsu et al. (US20210066137A1) discloses a stacked gate structure with dipole oxide layer similar to the disclose of the instant application.
More et al (US20220216327A1) similarly discloses dipole species in an interfacial layer contacting a high-k dielectric layer.
Chang et al. (US20220310846A1) discloses multiple dopants forming different dipole species with different polarities.
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/Seth D Lawson/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893