Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed July 8, 2025 in response to the Office action dated February 11, 2025. Claim 19 has been amended. Claims 22-24 have been canceled. No new claims have been added. Claims 1-21 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 19, 2025 was filed after the mailing date of the non-final office action on February 11, 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 7-14, 16-20, and 22 is/are rejected under 35 U.S.C. 102 a(1) and a(2) as being anticipated by Nair (US 20210357222 A1), hereinafter Nair.
With regards to claim 1, Nair teaches a register file having a plurality of register file cells, each of the register file cells to include a register file entry and a shadow buffer; (¶0014 The fixed-point unit 112 includes a renaming unit 114, a scheduler unit 128, a picker unit 130, a master-shadow physical register file (MS-PRF 150), a load/store unit (LSU) 120, and one or more execution (EX) units 122, such as one or more arithmetic logic units (ALUs), and one or more address generation (AG) units 124.;
¶0015 The MS-PRF 151 includes master-shadow physical registers (depicted as MSPRs 230 in FIG. 2) that utilize master storage 117 and shadow storage 118 for storage of data.;
Wherein shadow buffer is shadow storage, register file entry is master storage, register file cell is master-shadow physical registers, and Register file is the master-shadow physical register file.) and
logic circuitry to cause storage of input data to the shadow buffer, while data stored in the register file entry is to be accessible to perform one or more operations. (¶0009 FIGS. 1-5 … Master storage 117 is storage that is configured to store active data, i.e., data currently being used in the execution of instructions. Shadow storage 118 is storage coupled to the master storage that stores dormant data, i.e., data not currently being executed.;
¶0159 In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processor described above with reference to FIGS. 1-5.)
With regards to claim 5, Nair teaches wherein the register file is to be partitioned into a plurality of domains, wherein each domain is to support a selectable mode for latching and/or transport of data. (¶0042 In addition to the clock signal 263, the selected MSPR 230 also receives the shadow write enable signal 262, which, when asserted, is used to indicate that data stored in the master storage elements 233 of MSPR 230 is dormant and should be transferred to the shadow storage elements 234 of MSPR 230.)
With regards to claim 7, Nair teaches wherein a processor, having one or more processor cores, is to access the data stored in the register file entry to perform the one or more operations. (¶0011 FIG. 1 illustrates a processor 100 that utilizes a master-shadow physical register file 151 to store data in accordance with some embodiments. The illustrated processor 100 can include, for example, a central processing unit (CPU) core based on an x86 instruction set architecture (ISA), an ARM ISA, and the like. In some embodiments the processor 100 implements a plurality of such processor cores ...;
¶0061 Method 500 commences …At block 510, processor 100 stores data associated with the first instruction in master storage 117 of master-shadow physical register 151.)
With regards to claim 8, Nair teaches wherein the one or more operations comprise a load operation and/or a store operation. (¶0061 Method 500 commences … At block 510, processor 100 stores data associated with the first instruction in master storage 117 of master-shadow physical register 151.)
With regards to claim 9, Nair teaches wherein the input data is to be read from a backing storage. (¶0014 The fixed-point ... The LSU 120 is coupled to a memory hierarchy, including one or more levels of cache (e.g., L1 cache, L2, cache, etc.), a system memory, such as system RAM, and one or more mass storage devices, such as a solid-state drive (SSD) or an optical drive.;
Mass storage device is interpreted to be backing storage.)
With regards to claim 10, Nair teaches wherein the backing storage comprises Static Random- Access Memory (SRAM). (¶0015 The MS-PRF 151 includes master-shadow physical registers (depicted as MSPRs 230 in FIG. 2) that utilize master storage 117 and shadow storage 118 for storage of data. In some embodiments, static random-access memory (SRAM) with multiple read and write ports is used to implement MS-PRF 151.)
With regards to claim 11, Nair teaches wherein a working data set is to be subdivided into a plurality of data blocks stored in the backing storage. (¶0014 The fixed-point unit … The LSU 120 is coupled to a memory hierarchy, including one or more levels of cache (e.g., L1 cache, L2, cache, etc.), a system memory, such as system RAM, and one or more mass storage devices, such as a solid-state drive (SSD) or an optical drive.; The LSU (load/store unit) reads data from the mass storage devices. It would be obvious that the LSU is sent divided data blocks when loading data to be sent to the MS-PRF.)
With regards to claim 12, Nair teaches wherein the backing storage and the plurality of register file cells are to communicate via a lower bandwidth interconnect than an interconnect coupled between a processor and the plurality of register file cells. (It would be obvious that the backing storage (mass storage device), which includes, but is not limited to, solid-state drive and optical drives, would be communicating to the register file cells via a lower bandwidth interconnect, than that of an interconnect coupled between a processor and the plurality of register file cells. Because the backing storage (mass storage device) cannot transfer data as fast as a processor and register file cells, there would need to be a lower bandwidth communication for the backing storage (mass storage device) to be able to communicate with the register file cells.)
With regards to claim 13, Nair teaches wherein a die stack comprises a separate die for the backing storage than a die for the plurality of register file cells. (Figure 1; Figure 1 shows the cache/memory Hierarchy as a separate unit from where the Fixed Point Unit (where the MS-PRF resides), therefore the mass storage device is located at a separate unit. It would be obvious to say that both the backing storage and plurality of register file cells are comprised of two separate dies.)
With regards to claim 14, Nair teaches wherein the register file has a functional capacity which can be as large as a capacity of the backing storage. (The phrasing "which can be" is interpreted as a possibility and therefore the register file's functional capacity can be both as large as a capacity of the backing storage, smaller, or equal.)
With regards to claim 16, Nair teaches wherein the shadow buffer comprises at least one of a latch and a flip-flop. (¶0051 The master-shadow element 400 includes a write multiplexer (MUX) 410, an AND gate 441, an AND-gate 442, a master flip-flop (MFF) 420, a shadow flip-flop (SFF) 430, and a MUX 470.;
It is well known in the art that SRAM comprises of flip flops and latches.)
With regards to claim 17, Nair teaches wherein a processor, having one or more processor cores, comprises the logic circuitry. (¶0011 FIG. 1 illustrates a processor 100 that utilizes a master-shadow physical register file 151 to store data in accordance with some embodiments. The illustrated processor 100 can include, for example, a central processing unit (CPU) core based on an x86 instruction set architecture (ISA), an ARM ISA, and the like. In some embodiments the processor 100 implements a plurality of such processor cores ...)
With regards to claim 18, Nair teaches wherein the processor comprises a graphics processing unit and/or a general-purpose processor. (¶0011 FIG. 1 illustrates a processor 100 that utilizes a master-shadow physical register file 151 to store data in accordance with some embodiments. The illustrated processor 100 can include, for example, a central processing unit (CPU) core based on an x86 instruction set architecture (ISA), an ARM ISA, and the like. In some embodiments the processor 100 implements a plurality of such processor cores ...;
The CPU core based on an x86 ISA is interpreted to be a general-purpose processor.)
With regards to claim 19, Nair teaches decode circuitry to decode an instruction; (¶0013 The instruction cache 106 stores instruction data which is fetched by the fetch unit 104 in response to demand fetch operations (e.g., a fetch to request the next instruction in an instruction stream identified by a program counter) or in response to speculative prefetch operations. The decode unit 108 decodes instructions fetched by the fetch unit 104 into one or more operations that are to be performed, or executed, by either the floating-point unit 110 or the fixed-point unit 112.)
and execution circuitry to execute the decoded instruction to perform one or more operations, (¶0012 In the depicted example, the processor 100 includes an instruction cache 106, a fetch unit 104, a decode unit 108, one or more floating-point units 110, and one or more fixed-point units 112 (also commonly referred to as “integer execution units”).; ¶0017 In an operation of the fixed-point unit 112, the renaming unit 114 receives operations from the decode unit 108 (usually in the form of operation codes, or opcodes). These dispatched operations typically also include, or reference, associated information used in the performance of the represented operation, such as a memory address at which operand data is stored, architectural registers at which operand data is stored, one or more constant values (also called “immediate values”), and the like.; ¶0159 In some embodiments, the apparatus and techniques described above are implemented in a system including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processor described above with reference to FIGS. 1-5. In some embodiments, variant 3, described above, also applies to scheme 2.)
wherein the one or more operations cause storage of input data to a shadow buffer of a register file cell, while data stored in a register file entry of the register file cell is to be accessible to execute one or more tasks. (¶0009 FIGS. 1-5 … Master storage 117 is storage that is configured to store active data, i.e., data currently being used in the execution of instructions. Shadow storage 118 is storage coupled to the master storage that stores dormant data, i.e., data not currently being executed. ¶0015 The MS-PRF 151 includes master-shadow physical registers (depicted as MSPRs 230 in FIG. 2) that utilize master storage 117 and shadow storage 118 for storage of data. … Data is stored in the master-shadow physical register file 150 when, for example, the data is operated on as part of a data processing operation.;
Wherein shadow buffer is shadow storage, register file entry is master storage, and register file cell is master-shadow physical registers.)
With regards to claim 20, Nair teaches wherein a processor, having one or more processor cores, is to access the data stored in the register file entry to perform the one or more tasks. (¶0011 FIG. 1 illustrates a processor 100 that utilizes a master-shadow physical register file 151 to store data in accordance with some embodiments. The illustrated processor 100 can include, for example, a central processing unit (CPU) core based on an x86 instruction set architecture (ISA), an ARM ISA, and the like. In some embodiments the processor 100 implements a plurality of such processor cores ...
¶0061 Method 500 commences at block 502, where processor 100 receives and decodes a first instruction. At block 504, renaming unit 114 renames the first instruction. At block 510, processor 100 stores data associated with the first instruction in master storage 117 of master-shadow physical register 151.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 15, and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nair (US 20210357222 A1), in view of Hsu (US 20060294344 A1), hereinafter Hsu.
With regards to claim 2, Nair teaches wherein contents of selected register file entries and their corresponding shadow buffers… (¶0009 FIGS. 1-5 … Master storage 117 is storage that is configured to store active data, i.e., data currently being used in the execution of instructions. Shadow storage 118 is storage coupled to the master storage that stores dormant data, i.e., data not currently being executed.)
Nair does not teach:
are to be exchanged simultaneously
However, Hsu does teach:
are to be exchanged simultaneously (¶0028 In one example … Upon swapping, the data, or context, associated with the first process is stored in the S portion of each stage, and that process is halted. Also, the working register file register set (the register file data for the first process) is switched to the shadow register file register set The data in all stages are swapped simultaneously and in one clock cycle, 10 and therefore a context switch is completed in one clock cycle.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the apparatus disclosed by Nair to exchange the contents of selected register file entries and their corresponding shadow buffers simultaneously using the teaching of Hsu. The modification would be obvious because one of ordinary skill in the art would be motivated to reduce latency when performing data operations. (Hsu: ¶0001 Most modern computer … A pipeline architecture does however increase the latency when performing data operations since data must pass through several stages before the operation is complete.; The prior art is trying to solve this problem.)
With regards to claim 3, Nair teaches wherein contents of selected register file entries and their corresponding shadow buffers … (¶0009 FIGS. 1-5 … Master storage 117 is storage that is configured to store active data, i.e., data currently being used in the execution of instructions. Shadow storage 118 is storage coupled to the master storage that stores dormant data, i.e., data not currently being executed.)
Nair does not teach:
are to be exchanged in a single clock cycle.
However, Hsu does teach:
are to be exchanged in a single clock cycle. (¶0028 Upon swapping, the data, or context, associated with the first process is stored in the S portion of each stage, and that process is halted. Also, the working register file register set (the register file data for the first process) is switched to the shadow register file register set The data in all stages are swapped simultaneously and in one clock cycle, 10 and therefore a context switch is completed in one clock cycle.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the apparatus disclosed by Nair to exchange the contents of selected register file entries and their corresponding shadow buffers in a single clock cycle using the teaching of Hsu. The modification would be obvious because one of ordinary skill in the art would be motivated to reduce latency when performing data operations. (Hsu: ¶0001 Most modern computer … A pipeline architecture does however increase the latency when performing data operations since data must pass through several stages before the operation is complete.; The prior art is trying to solve this problem.)
With regards to claim 4, Nair teaches wherein contents of selected register file entries and their corresponding shadow buffers … (¶0009 FIGS. 1-5 … Master storage 117 is storage that is configured to store active data, i.e., data currently being used in the execution of instructions. Shadow storage 118 is storage coupled to the master storage that stores dormant data, i.e., data not currently being executed.)
Nair does not teach:
are to be overwritten simultaneously.
However, Hsu does teach:
are to be overwritten simultaneously. (¶0028 Upon swapping, the data, or context, associated with the first process is stored in the S portion of each stage, and that process is halted. Also, the working register file register set (the register file data for the first process) is switched to the shadow register file register set The data in all stages are swapped simultaneously and in one clock cycle, 10 and therefore a context switch is completed in one clock cycle.; Swapping can be interpreted as overwritten simultaneously.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the apparatus disclosed by Nair to overwrite the contents of selected register file entries and their corresponding shadow buffers simultaneously using the teaching of Hsu. The modification would be obvious because one of ordinary skill in the art would be motivated to reduce latency when performing data operations. (Hsu: ¶0001 Most modern computer … A pipeline architecture does however increase the latency when performing data operations since data must pass through several stages before the operation is complete.; The prior art is trying to solve this problem.)
With regards to claim 15, Nair teaches wherein the register file entry and the shadow buffer … (¶0009 FIGS. 1-5 … Master storage 117 is storage that is configured to store active data, i.e., data currently being used in the execution of instructions. Shadow storage 118 is storage coupled to the master storage that stores dormant data, i.e., data not currently being executed.)
Nair does not teach:
have a same capacity.
However, Hsu does teach:
have a same capacity. (Claim 23: The system of claim 19 wherein said working registers and said shadow registers are 64 bits wide.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the apparatus disclosed by Nair to change the register file entry and the shadow buffer have the same capacity using the teaching of Hsu. The modification would be obvious because one of ordinary skill in the art would be motivated to be able to transfer content from the register file entry to the shadow buffer without errors.
With regards to claim 21, Nair teaches wherein a register file comprises a plurality of the register file cells, wherein contents of selected register file entries of the register file and their corresponding shadow buffers … (¶0014 The fixed-point unit 112 includes a renaming unit 114, a scheduler unit 128, a picker unit 130, a master-shadow physical register file (MS-PRF 150), a load/store unit (LSU) 120, and one or more execution (EX) units 122, such as one or more arithmetic logic units (ALUs), and one or more address generation (AG) units 124.;
Register file is the master-shadow physical register file;
¶0015 The MS-PRF 151 includes master-shadow physical registers (depicted as MSPRs 230 in FIG. 2) that utilize master storage 117 and shadow storage 118 for storage of data.)
Nair does not teach:
are to be at least one of exchanged and overwritten in a single clock cycle.
However, Hsu does teach:
are to be at least one of exchanged and overwritten in a single clock cycle. (¶0028 Upon swapping, the data, or context, associated with the first process is stored in the S portion of each stage, and that process is halted. Also, the working register file register set (the register file data for the first process) is switched to the shadow register file register set The data in all stages are swapped simultaneously and in one clock cycle, 10 and therefore a context switch is completed in one clock cycle.;
Swapping can be interpreted as overwriting or exchanging.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the apparatus disclosed by Nair to exchange and to overwrite the contents of selected register file entries and their corresponding shadow buffers in a single clock cycle using the teaching of Hsu. The modification would be obvious because one of ordinary skill in the art would be motivated to reduce latency when performing data operations. (Hsu: ¶0001 Most modern computer … A pipeline architecture does however increase the latency when performing data operations since data must pass through several stages before the operation is complete.; The prior art is trying to solve this problem.)
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nair (US 20210357222 A1), in view of Hofstee (US 20020116662 A1), hereinafter Hofstee.
With regards to claim 6, Nair teaches wherein the shadow buffer is capable to load … (¶009 FIGS. 1-5 … Shadow storage is storage coupled to the master storage that stores dormant data, e.g., data not currently being executed.)
Nair does not teach:
from one or more data streams and/or to write to the one or more data streams.
However, Hofstee does teach:
from one or more data streams and/or to write to the one or more data streams. (Figure 7; Shows a chart of instructions continuously being sent to a shadow stack. The continuous instructions are interpreted as a data stream and the shadow stack is interpreted as the shadow buffer.)
Nair and Hofstee are analogous art because they are from the same field of endeavor, that being register files. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus disclosed by Nair to have the shadow buffer load and/or write data streams using the teaching of Hofstee. The motivation would have been to have a faster restoration of results to the registers. (Hofstee: (¶0010))
Response to Arguments
Applicant’s arguments, see pages 6-7, filed July 08, 2025, with respect to Claims 1-4, 6-24 have been fully considered and are persuasive. The 101 rejection of February 11, 2025 has been withdrawn.
Applicant’s arguments, see pages 7-9, filed July 08, 2025, with respect to the rejection(s) of claim(s) 1-, 5, 7-14, 16-20, and 22 under 102(a) have been fully considered and are not persuasive.
Regarding Claim 1, the applicant argues that the quoted sections of Nair (¶0009 and ¶0159) do not describe the limitation, “logic circuitry to cause storage of input data to the shadow buffer, while data stored in the register file entry is to be accessible to perform one or more operations.” The applicant states, “There is no discussion that data can be input into the shadow storage 118 while the master storage 117 is accessible for reading or writing.”
The examiner asserts that the language of the claim “while data stored in the register file entry is to be accessible to perform one or more operations” is interpreted as having intended use. Specifically, the limitation “is to be accessible to perform one or more operations” is intended use of accessing data stored in the register file entry, and also intended use of performing one or more operations. The claim does not positively recite that 1) data stored in the register file entry is accessed nor that 2) the one or more operations are performed.
Furthermore, Nair teaches that both the master storage 117 and the shadow storage 118 have different threads associated to them in paragraph 145. This shows that master storage 117 is accessible during the same period of time that data was being stored into the shadow storage 118, given the different threads assigned to each storage. The rejection in view of Nair is maintained.
Regarding claim 19, the applicant argues that Nair does not teach the claim limitations “An apparatus comprising: decode circuitry to decode an instruction; and execution circuitry to execute the decoded instruction to perform one or more operations, wherein the one or more operations cause storage of input data to a shadow buffer of a register file cell, while data stored in a register file entry of the register file cell is to be accessible to execute one or more tasks.” The applicant states that there is less support for Nair describing a particular instruction and that the “storage of input data to a shadow buffer of a register file cell, while data stored in a register file entry of the register file cell is to be accessible to execute one or more tasks” is not described by Nair.
The examiner asserts that the decoder unit decoding the instructions fetched by the fetch unit, in Nair (¶0013), teaches the “particular instruction”.
Furthermore, the examiner asserts that the language of the claim “while data stored in a register file entry of the register file cell is to be accessible to execute one or more tasks” is interpreted as having intended use. Specifically, the limitation “is to be accessible to execute one or more tasks” is intended use of accessing data stored in the register file entry, and also intended use of executing one or more tasks. The claim does not positively recite that 1) data stored in the register file entry is accessed nor that 2) the one or more tasks are executed.
Furthermore, Nair teaches that both the master storage 117 and the shadow storage 118 have different threads associated to them in paragraph 145. This shows that master storage 117 is accessible during the same period of time that data was being stored into the shadow storage 118, given the different threads assigned to each storage. The rejection in view of Nair is maintained.
With respect to Applicant' s arguments regarding the dependent claims, the arguments rely on the allegation that the independent claims are patentable and therefore for the same reasons the dependent claims are patentable. However, as addressed above, the rejections of the independent claims are maintained and therefore for the same reasons, rejections of the dependent claims are maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Chaudhry (US 7565511 B2): A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR R CEDENO whose telephone number is (571)272-1030. The examiner can normally be reached Monday-Thursday 8:30 AM - 6:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/V.R.C./ Examiner, Art Unit 2137
/Arpan P. Savla/ Supervisory Patent Examiner, Art Unit 2137