Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/17/2025 has been entered.
This action is non-final, and is in response to the amendments filed on 11/14/2025. Claims 1-20 are pending and have been considered. Claims 1, 12, and 20 are independent claims. Claims 1-10 and 12-20 have been amended. No claims have been canceled.
Information Disclosure Statement (IDS)
The information disclosure statement (IDS) submitted on 11/14/2025 is in compliance with the provisions of 37 CFR 1.97.
Response to Amendments and Arguments
In the amendment filed on 11/14/2025, applicant amended independent claims 1-10 and 12-20 to include new limitations. The amendments have been fully considered.
In view of the amendments and arguments the rejection of claims 1-8 and 10-20 as being unpatentable under 35 U.S.C. § 103 over Tang et al. (Ramp Up/Down Functional Unit to Reduce Step Power, B. Falsa and T.N. Vijaykumar) (hereinafter "Tang") in view of US 2014/0078829 to Chen HE (hereinafter "Chen") has been withdrawn. A new ground of rejection under 35 U.S.C 103 is established.
In view of the amendments and arguments the rejection of claim 9 as being unpatentable under 35 U.S.C. § 103 over Tang et al. (Ramp Up/Down Functional Unit to Reduce Step Power, B. Falsa and T.N. Vijaykumar) (hereinafter "Tang") in view of US 2014/0078829 to Chen HE (hereinafter "Chen") in further view of US 2002/0040416 to Tsern (hereinafter "Tsern") has been withdrawn. A new ground of rejection under 35 U.S.C 103 is established.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 12, 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims use the terms “first series”. The term “first” introduces an ordinal term without a contextual basis. The scope is unclear, a first relative to what? The term “first” appears for the first time in the amended claim, and it was not used in the original specification.
Dependent claims 2-11, 13-19 are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph inherit the deficiencies of the parent claims. Some of these claims repeat the terms in their recitation.
For advancing prosecution the term combination “first series” will be interpreted as “series”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims with similar limitations are grouped, and the analysis is performed on the system claim; the other claims of the group are rejected under the same rationale.
Claims 1-8 and 10-20 are rejected under 35 U.S.C. § 103 over Tang et al. (Ramp Up/Down Functional Unit to Reduce Step Power, B. Falsa and T.N. Vijaykumar) (hereinafter "Tang") in view of Lorenz P. S., US 20140253358 A1 (hereinafter” Lorenz”) , in further view of 20210064294 to Kim et al (hereinafter "Kim").
Independent claim 12 is directed to a system and recites all of the limitations of independent method claim 1, and independent memory controller claim 20, along with additional limitations. The analysis is performed on the system claim 12. Claims 1 and 20 are rejected under the same rationale set forth for claim 12.
Claim interpretation
In broadest reasonable interpretation and in view of the specification, the independent claim 12 (representative for 1 and 20) is interpreted being fully covered by the combination of the following three groups of claim elements:
A method to increase power/current to (an) operational unit(s) of an integrated circuit, in a ramping up manner, in preparation for execution of an operation, but without the execution disabled while ramping - and similarly, a ramping down to decrease power after execution of the operation.
A method to obtain the ramping up current, by transmitting (a series of) data, such that an increase of amount of data corresponds to an increase in the with amount of power/current
A system with a memory controller in communications with a physical layer circuity, wherein memory controller comprises a processor configured to perform power management in conjunction with writing/reading from memory.
“A” is a general purpose method to ramp power/current to units, applicable regardless what is to be powered up or down; it indicates ramp/step-up before, and ramp-up down after an execution. “B” illustrates how ramping up and down of power/current can be achieved, again, general purpose. “C” instantiates the general ‘unit’ to the specifics of PHY/memory.
The term “simulated write” is not a term of the art, and not explicitly defined in the specification, but from the examples it is interpreted as an operation executed in preparation of a write, aimed to lead to the power increase, but without writing into the memory. Physical circuit layer (PHY), as understood in the practice, and according to Wikipedia (https://en.wikipedia.org/wiki/Physical_layer) is interpreted as the circuitry layer most closely associated with the physical connection between devices.
Consistent with the above interpretation, the claim is mapped to the prior art as follows:
Part A: A method to increase power/current to (an) operational unit(s) of a semiconductor integrated circuit (IC), in a ramping up manner, in preparation for execution of an operation, but without actually executing the operation while ramping (disabled); and similarly, a ramping down to decrease power after execution of the operation.
Regarding claim 12 (representative for claims 1, 20) Tang discloses
sending a first series of simulated write operations to a physical layer circuitry (PHY) to increase power of the PHY in a ramping manner,
wherein a respective simulated write operation of the first series causes transmission of an amount of data to the PHY with output disabled for the data from the PHY [to a memory], ..{ see at least (Abstract) Two mechanisms at the microarchitecture level are proposed in this paper to reduce the step power; Page 15, line 3, we define step power as the power difference between the previous and present clock cycles. We use the step power as figure of merit for power surges at the microarchitecture level, and study how to reduce the step power by ramping up and ramping down functional units for high-performance processors. We use the floating point unit (FPU) to illustrate our ideas. Page 14, Line 15- we proposed two new mechanisms to ramp up/down (turn on/off gradually) the FPU based on either the instruction fetch queue (IFQ) scanning or the PC+N instruction prediction; Page 15 Line 21-30 We introduce several artificial workload states… The relation-ship of the inactive state, artificial workload states, and active state of FPU is illustrated in Figure 1 (c)…. A special power state, which is only one step below the active state, is called subactive state and dissipates Ps power. After a floating point instruction is predicted, the FPU will ramp up and stay in the subactive state. The FPU enters the active state when the instruction gets executed; Page 16, Fig1(c) The relationship of states, Active Workload States, Subactive State, Inactive State, Active State.; P.17 (3) To ramp up/down the FPU based on instruction prediction, one more instruction will be fetched and predecoded in the IF stage for every clock cycle. In this case, a small predecode and control logic is needed.. In terms of circuit implementation, both the clock network and FPU can be partitioned into subcircuits. One subcircuit will be enabled or disabled per cycle during ramping up or ramping down via clock gating as discussed in [20,21] } Simulated write operation to the physical layer to increase circuit power level interpreted as the Artificial workload states which increase before the Active state; with output disabled for the data until the memory operation begins interpreted as illustrated by the wait in Subactive state (in which the state is not active, hence disabled) – entering active state when the instruction gets executed. Physical layer circuits though not explicitly referred to are inherent to how the operation is executed.
Fig 1 from Tang is used here for illustration; Tang introduces the method in the context of microarchitectures, refers to the instructions received, etc.
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Fig. 1: Shows fig 1 from page 16 in Tang, illustrating the relationship of states. Simulated write is interpreted as Artificial workload state; shows inactive state (to which idle state is interpreted as) , active state (to which write and read state are interpreted as), etc. Output disabled is interpreted as the state being ‘subactive’ but not ‘active/activated’
Part B: A method to obtain the ramping up is by transmitting (a series of) data, such that amount of data increases with amount of power/current (needed)
As discussed above, Tang discloses the simulated write operation and the increase in power/current. Tang does not disclose, however Lorenz discloses:
wherein the amount of data of the respective [simulated write] operation increases with increase in power of the respective [simulated write] operation {Lorenz [Abstract]…This pulse count data can be communicated to a processor configured to count the pulses in the pulse train, and convert this pulse count data into digital data corresponding to the analog information; [0012] In an one implementation, the input circuitry can be configured to include: (a) digital counter circuitry responsive to a start count signal, and configured to output a digital count that increases according to a predetermined count frequency from the start count signal until a stop count signal is received; (b) digital to analog conversion (DAC) circuitry configured to generate an analog DAC output that increases in magnitude corresponding to the increase in the digital count; Fig. 2}
The amount of data is the amount counted by the counter (how many pulses) and this leads to an increase in current or voltage (power) at the output of the DAC.. The analog output of the DAC is increasing with the amount of pulses/data received. Thus a method to obtain the ramping up by transmitting (a series of) data, such that amount of data increases with amount of power/current (needed) is disclosed.
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In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Tang using the ramping up of current, and Lorenz’s scheme of ramping up current to obtain the advantage of ramping up with a well known method ensuring precise control of current level with number of pulses counted. Furthermore, the Supreme Court has supported that combining well known prior art elements, in a well-known manner, to obtain predictable results is sufficient to determine an invention obvious over such combination (see KSR International Co. v. Teleflex Inc. (KSR), 550 U.S.,82 USPQ2d 1385 (2007) & MPEP 2143). In the instant case, Tang evidently discloses the method to gradual increase in power in ‘artificial’ or ‘simulated; workload steps. Lorenz is merely relied upon to illustrate and increasing data amount at the same time with power. Both refer to microarchitectures and increasing power/current and combining their features as above would be reasonable, according to one of ordinary skill in the art. Moreover, since the elements disclosed by Tang and Lorenz would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable. Accordingly, the claimed subject matter would have been obvious over Tang in view of Lorenz.
Part C Wherein the operation is to a memory.
The methods described by Tang/Lorenz teach the simulated write to a unit in which power is increased incrementally and proportional with the amount of data transmitted, are means of increasing power to a variety of circuits. Though the method is generic they don’t explicitly refer to a memory.
However, Kim teaches the gradual changing the current in an operation with a memory.
to a memory {see at least [0006] Embodiments provide a memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, and an operating method of the memory controller. In an embodiment, the memory controller may sequentially apply a dummy pulse to a plurality of channels coupled to the plurality of memory devices to sequentially increase the total current consumed by the plurality of memory devices, or sequentially interrupt the dummy pulse applied to the plurality of channels to sequentially decrease the total current, or both. As a result, noise in a voltage source due to a sudden change in total current consumption in the plurality of memory devices may be substantially prevented}.
Thus, Kim explicit teaches a system in which the current is for a memory operation. Applying the known structure of Kim to implement the power increase of Tang /Lorenz would have been obvious to a POSITA in order to realize the disclosed method in a practical and operable way.
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Tang/Lorenz for increasing /ramping up the power with increasing amount of data, generally applicable, and Kim increase in current for memory. o avoid the power surge in memory operations , in voltage glitch proportional with di/dt (the current changing rate) and large surge current, known to cause timing and logic errors and reduce reliability. As Kim describes the motivation [0006] As a result, noise in a voltage source due to a sudden change in total current consumption in the plurality of memory devices may be substantially prevented. Furthermore, the Supreme Court has supported that combining well known prior art elements, in a well-known manner, to obtain predictable results is sufficient to determine an invention obvious over such combination (see KSR International Co. v. Teleflex Inc. (KSR), 550 U.S.,82 USPQ2d 1385 (2007) & MPEP 2143). In the instant case, Tang/Lorenz evidently discloses the method to gradual increase in power in ‘artificial’ or ‘simulated; workload steps, and increasing data amount at the same time with power. Kim is merely relied upon to illustrate in the specific case/application of a memory operation. Both refer to managing power in microarchitecture operations and combining their features as above would be reasonable, according to one of ordinary skill in the art. Moreover, since the elements disclosed by Tang/Lorenz and Kim would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable. Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz in view of Kim.
Regarding Claims 2, 13 Tang/Lorenz/Kim discloses the limitations of claim 1 and 12, respectively. Kim further discloses,
wherein a first simulated write operation of the first series instructs the PHY to increase circuit power to a level above an idle state that is below a power level state of the memory operation. {[p.15 2.2] If there exist floating point instructions, a request signal will be sent to the EXE stage directly to ramp up the FPU from the inactive state to the subactive state within pre-diction time by adding artificial workloads gradually.} thus the first simulated write operation of the first series which instructs the physical circuit to increase power to a level above an idle state that is below a power level state of the memory operation is interpreted as the as the request signal will be sent to the EXE stage directly to ramp up the FPU from the inactive state to the subactive state within pre-diction time by adding artificial workloads gradually .
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Regarding claims 3, 14 Tang/Lorenz/Kim discloses the limitations of claim 2 and 13, respectively. Tang further discloses
wherein a second simulated write operation of the first series increases the circuit power of the PHY a first power level above the idle state.
Fig. 3 shows annotation (gray box) made on fragment from Fig. 1(c) in Tang. The figure illustrates the interpretation: First simulated write, interpreted as first artificial workload state while a first power level above idle, interpreted as the first level above the inactive state.
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Fig, 3 Interpretation of second simulated write is a first power level above idle (annotation in gray box and bold arrows)
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz in view of Kim.
Regarding claims 4, 15 Tang/Lorenz/Kim discloses the limitations of claims 3, 14. Tang further discloses wherein a third simulated write operation of the first series is associated with a second power level of the circuit power of the PHY that is above the first power level.
Fig. 4 shows annotation (gray box) made on fragment from Fig. 1(c) in Tang. The figure illustrates the interpretation: third simulated write with an increased second power level above the first power level as the second level above the inactive state.
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Fig, 4 Interpretation of third simulated write with an increased second power level, associated with a second power level, above the first power level (annotation in gray box and arrows)
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Regarding claims 5, 16, Tang/Lorenz/Kim discloses the limitations of claim 4, 15. Tang further discloses
performing the second simulated write before the third simulated write operation.
Fig. 5 shows annotation (gray box) made on fragment from Fig. 1(c) in Tang. The figure illustrates the interpretation: Second simulated write, interpreted as first artificial workload state while a first power level above idle, interpreted as the first level above the inactive state.
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Fig. 5 Interpretation of second simulated write before the third simulated write (annotation in gray box and bold arrows)
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Regarding claims 6, 17, Tang/Lorenz/Kim discloses the limitations of claims 5, 16.Tang further discloses
wherein the second simulated write operation and the third simulated write are performed before a memory operation.
Fig. 6 shows annotation (gray box) made on fragment from Fig. 1(c) in Tang. The figure illustrates the interpretation: second simulated write and the third simulated write performed before a memory operation, wherein second simulated write is interpreted as first artificial workload state, third simulated write as the second artificial workload state and before a memory operation interpreted as before the active state.
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Fig. 6 Interpretation of first simulated write and the second simulated write performed before a memory operation (annotation in gray box and bold arrows)
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Regarding claims 7, 18 Tang/Lorenz/Kim discloses the limitations of claims 4, 15. Tang further discloses
performing the second simulated write after the third simulated write operation.
Fig. 7 shows annotation (gray box) made on fragment from Fig. 1(c) in Tang. The figure illustrates the interpretation: Second simulated write, interpreted as first artificial workload state AFTER the third simulated write, interpreted as after the second, (of higher power level) artificial workload state.
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Fig. 7 Interpretation of performing the second simulated write after the third simulated write. (annotation in gray box and bold arrows)
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Re Claims 8, 19 Tang/Lorenz/Kim discloses the limitations of claims 7, 18. Tang further discloses wherein the second simulated write operation is performed at the completion of a memory operation.
Fig. 8 shows annotation (gray box) made on fragment from Fig. 1(c) in Tang. The figure illustrates the interpretation: Second simulated write, interpreted as first artificial workload state at the completion of the write operation, interpreted as the completion of the active state.
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Fig. 8 Interpretation of second simulated write performed at the completion of a memory operation (annotation in gray box and bold arrows)
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Re Claim 10 Tang/Lorenz/Kim discloses the limitations of Claim 1. Tang further discloses scheduling the simulated write based upon a criteria. {page 15, line 26 After a floating point instruction is predicted, the FPU will ramp up and stay in the subactive state. The FPU enters the active state when the instruction gets executed.} Scheduling the simulated write up based in a criteria is interpreted as the ramp up time upon instruction prediction.}
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Re Claim 11 Tang/Lorenz/Kim discloses the limitations of Claim 10. Tang further discloses wherein the criteria includes one or more of the following: in between a load step and load release of a memory operation, a scheduled time between a read operation and a write operation, or a predefined period between a read operation or a write operation.{ After a floating point instruction is predicted, the FPU will ramp up and stay in the subactive state. The FPU enters the active state when the instruction gets executed}. A scheduled time between a read operation and a write operation is interpreted as the subactive step which is between two active steps.
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim.
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (Ramp Up/Down Functional Unit to Reduce Step Power, B. Falsa and T.N. Vijaykumar) (hereinafter "Tang") in view of Lorenz P. S., US 20140253358 A1 (hereinafter” Lorenz”) , in further view of 20210064294 to Kim et al (hereinafter "Kim") in further view of Tsern (US 2002/0040416) (“Tsern”)
Regarding claim 9, Tang/Lorenz/Kim discloses the limitations of 4. Tang/Lorenz/Kim does not the disclose the using a number of bytes for first simulated write and a larger number of bytes for second simulated write. However, Tsern discloses , wherein the first simulated write includes a first number of data bytes and the second simulated write includes a second number of data bytes that is more than the first number of data bytes. {[0027] As indicated in the summary, depending on the particular memory devices being controlled, the number of possible power states and the exact definition of those power states will vary, but will generally includes at least a first (active) state, a second (mid-power) state, and a third (low power) state… While the invention will be described with respect to Active, Standby and Nap states, in other implementations these power states may be replaced by first, second and third power states, as well as other additional power states, whose definitions are different from those of Active, Standby and Nap; [0028] Referring to FIG. 3, a memory device in the Active state may be "relaxed" to the Standby state to reduce power consumption, and then put in a Nap state to further reduce power consumption. Any memory device in the Standby state may transition directly to the Active state, by issuing a Sense command to it. A device in the Nap state must be sent a wake up command prior to sending it a Sense command. } The changes from one state to another state are incremental – from nap state first a wake up command, changing it to second level, the a Sense command to change to the next level. Thus, the second number of bytes is more that the first number of bytes, etc. It is clear that since states move from one to another incrementally, the higher the level the more commands are needed.
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the teachings of Tang/Lorenz/Kim of increasing power levels with the programming scheme of Tsern to increase the power levels gradually by adding an additional instruction for each step for full controllability and gradual increase. Furthermore, the Supreme Court has supported that combining well known prior art elements, in a well-known manner, to obtain predictable results is sufficient to determine an invention obvious over such combination (see KSR International Co. v. Teleflex Inc. (KSR), 550 U.S.,82 USPQ2d 1385 (2007) & MPEP 2143). In the instant case, Tang/Lorenz/Kim evidently discloses the method to gradual increase in power in steps. Tsern is merely relied upon to illustrate a specific way of sending the commands to induce the power level increases. Both refer to managing power in microarchitecture operations and combining their features as above would be reasonable, according to one of ordinary skill in the art. Moreover, since the elements disclosed by Tang/Lorenz/Kim and Tsern would function in the same manner in combination as they do in their separate embodiments, it would be reasonable to conclude that the results of the combination would be predictable.
Accordingly, the claimed subject matter would have been obvious over Tang/Lorenz/Kim in further view of Tsern.
Prior art made of record
The prior art made of record and not relied upon which, however, is considered pertinent to applicant's disclosure:
US 20140078829 A1
US 20170032838 A1
Conclusion
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/A.S./Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188