DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 03/31/2026, in which claims 1, 4, 5, 9, 15 were amended, claim 6 was cancelled, has been entered.
Claim Objections
The status of claim 4 is not in accordance with 37 CFR 1.121(c)(2) which requires all claims being currently amended in an amendment paper shall be presented in the claim listing, indicate a status of "currently amended," and be submitted with markings to indicate the changes that have been made relative to the immediate prior version of the claims. Only claims having the status of "currently amended," or "withdrawn" if also being amended, shall include markings.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al. (US Pub. 20190305111), hereafter Subramanian111 in view of Deng et al. (US Pub. 20170141111).
Regarding claim 1, Subramanian111 discloses in Fig. 8, Fig. 11C, paragraph [0063]-[0072], [0086], [0094]-[0100] an integrated circuit structure, comprising:
a first gate structure [816 and 830 left] over a first semiconductor fin [804 left];
a second gate structure [816 and 830 middle] over a second semiconductor fin [804 middle]; and
a first gate endcap isolation structure [832 middle] between the first gate structure [816 and 830 left] and the second gate structure [816 and 830 middle]; and
a second gate endcap isolation structure [832 left] adjacent to the first gate structure [816 and 830 left], the first gate structure [816 and 830 left] between the first gate endcap isolation structure [832 left] and the second gate endcap isolation structure [832 middle], each of the first gate endcap isolation structure [832 left] and the second gate endcap isolation structure [832 middle] having a higher-k dielectric cap layer [upper portion of SAGE 832] on a lower-k dielectric wall [lower portion of SAGE 832], the higher-k dielectric cap layer [upper portion of SAGE 832] comprising hafnium and oxygen [hafnium oxide][paragraph [0072], “one or both of the first gate endcap isolation structure and the second gate endcap isolation structure includes an upper dielectric layer on a lower dielectric layer, the upper dielectric layer having a greater dielectric constant than the lower dielectric layer”; paragraph [0086], “a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide”; paragraph [0098], “gate endcap isolation structure 1150 further includes a third dielectric layer 1156, such as a layer of silicon oxide”, paragraph [0099] “layers 1130 and 1154 may be composed of a same material, such as hafnium oxide”], and
the higher- k dielectric cap [upper portion of SAGE 832] having an uppermost surface at a same level as an uppermost surface of the first gate structure [816 and 830 left] and at a same level as an uppermost surface of the second gate structure [816 and 830 middle][paragraph [0066] “SAGE walls 832 are shown as tall SAGE wall portions that act as a gate endcap plug and are co-planar with an upper metal layer 830 of the gate electrode 830/832”; paragraph [0070] “the uppermost surface of the first gate endcap isolation structure is co-planar with an uppermost surface of a dielectric cap of each of the first gate structure and the second gate structure”].
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Subramanian111 fails to disclose in Fig. 8, Fig. 11C
the first semiconductor fin comprises a first pair of semiconductor fins;
the second semiconductor fin comprises a second pair of semiconductor fins.
However, Subramanian111 suggests in Fig. 5B, paragraph [0055] that a gate structure [557] can form over a single semiconductor fin or a pair of semiconductor fins.
For further support, Deng et al. is cited.
Deng et al. discloses in Fig. 2, paragraph [0038], [0057]
the first semiconductor fin comprises a first pair of semiconductor fins [102a][at least one first fin];
the second semiconductor fin comprises a second pair of semiconductor fins [102b][at least one second fin].
Deng et al. further discloses in Fig. 1I and paragraph [0038] that alternatively, the first semiconductor fin comprises a first single semiconductor fin and the second semiconductor fin comprises a second single semiconductor fin.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Deng et al. into the method of Subramanian111 to include the first semiconductor fin comprises a first pair of semiconductor fins; the second semiconductor fin comprises a second pair of semiconductor fins. The ordinary artisan would have been motivated to modify Subramanian111 in the above manner for the purpose of providing suitable number of first semiconductor fin the first gate formed across and suitable number of second semiconductor fin the second gate formed across to yield a device having desired performance [paragraph [0038] of Deng et al.]. In addition, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI B.
Regarding claim 4, Subramanian111 discloses in Fig. 8, Fig. 11C, paragraph [0072], [0099]-[0100]
wherein each of the first gate endcap isolation structure and the second gate endcap isolation structure comprises a vertical seam [1158] centered within the lower-k dielectric wall [1156].
Regarding claim 9, Subramanian111 discloses in Fig. 8, Fig. 11C, Fig. 12, paragraph [0063]-[0072], [0086], [0094]-[0112], a computing device [1200], comprising:
a board [1202]; and
a component [1204] coupled to the board [1202], the component [1204] including an integrated circuit structure, comprising:
a first gate structure [816 and 830 left] over a first semiconductor fin [804 left];
a second gate structure [816 and 830 middle] over a second semiconductor fin [804 middle]; and
a first gate endcap isolation structure [832 middle] between the first gate structure [816 and 830 left] and the second gate structure [816 and 830 middle]; and
a second gate endcap isolation structure [832 left] adjacent to the first gate structure [816 and 830 left], the first gate structure [816 and 830 left] between the first gate endcap isolation structure [832 left] and the second gate endcap isolation structure [832 middle], each of the first gate endcap isolation structure [832 left] and the second gate endcap isolation structure [832 middle] having a higher-k dielectric cap layer [upper portion of SAGE 832] on a lower-k dielectric wall [lower portion of SAGE 832], the higher-k dielectric cap layer [upper portion of SAGE 832] comprising hafnium and oxygen [hafnium oxide][paragraph [0072], “one or both of the first gate endcap isolation structure and the second gate endcap isolation structure includes an upper dielectric layer on a lower dielectric layer, the upper dielectric layer having a greater dielectric constant than the lower dielectric layer”; paragraph [0086], “a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide”; paragraph [0098], “gate endcap isolation structure 1150 further includes a third dielectric layer 1156, such as a layer of silicon oxide”, paragraph [0099] “layers 1130 and 1154 may be composed of a same material, such as hafnium oxide”], and
the higher- k dielectric cap [upper portion of SAGE 832] having an uppermost surface at a same level as an uppermost surface of the first gate structure [816 and 830 left] and at a same level as an uppermost surface of the second gate structure [816 and 830 middle][paragraph [0066] “SAGE walls 832 are shown as tall SAGE wall portions that act as a gate endcap plug and are co-planar with an upper metal layer 830 of the gate electrode 830/832”; paragraph [0070] “the uppermost surface of the first gate endcap isolation structure is co-planar with an uppermost surface of a dielectric cap of each of the first gate structure and the second gate structure”].
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Subramanian111 fails to disclose in Fig. 8, Fig. 11C
the first semiconductor fin comprises a first pair of semiconductor fins;
the second semiconductor fin comprises a second pair of semiconductor fins.
However, Subramanian111 suggests in Fig. 5B, paragraph [0055] that a gate structure [557] can form over a single semiconductor fin or a pair of semiconductor fins.
For further support, Deng et al. is cited.
Deng et al. discloses in Fig. 2, paragraph [0038], [0057]
the first semiconductor fin comprises a first pair of semiconductor fins [102a][at least one first fin];
the second semiconductor fin comprises a second pair of semiconductor fins [102b][at least one second fin].
Deng et al. further discloses in Fig. 1I and paragraph [0038] that alternatively, the first semiconductor fin comprises a first single semiconductor fin and the second semiconductor fin comprises a second single semiconductor fin.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Deng et al. into the method of Subramanian111 to include the first semiconductor fin comprises a first pair of semiconductor fins; the second semiconductor fin comprises a second pair of semiconductor fins. The ordinary artisan would have been motivated to modify Subramanian111 in the above manner for the purpose of providing suitable number of first semiconductor fin the first gate formed across and suitable number of second semiconductor fin the second gate formed across to yield a device having desired performance [paragraph [0038] of Deng et al.]. In addition, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI B.
Regarding claims 10-14, Subramanian111 discloses in Fig. 12, paragraph [0106]-[0112]
a memory [ROM, DRAM] coupled to the board [1202];
a communication chip [1206] coupled to the board [1202];
a camera coupled to the board [1202];
wherein the component [1204] is a packaged integrated circuit die [paragraph [0109];
wherein the computing device [1200] is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set- top box [paragraph [0112]].
Claims 1, 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al. (US Pub. 20200286891), hereafter Subramanian891 in view of Deng et al. (US Pub. 20170141111).
Regarding claim 1, Subramanian891 discloses in Fig. 1, Fig. 2, paragraph [0026], [0030], and [0083] an integrated circuit structure, comprising:
a first gate structure [104/204 left] over a first pair of semiconductor fin [102/202 left];
a second gate structure [104/204 right] over a second semiconductor fin [102/202 right]; and
a first gate endcap isolation structure [113/213 middle] between the first gate structure [104/204 left] and the second gate structure [104/204 right]; and
a second gate endcap isolation structure [113/213 left] adjacent to the first gate structure [104/204 left], the first gate structure [104/204 left] between the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left],each of the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left] having a higher-k dielectric cap layer [upper portion of SAGE 113/213] on a lower-k dielectric wall [lower portion of SAGE 113/213], wherein the higher-k dielectric cap layer comprising hafnium oxygen [paragraph [0083], “self-aligned gate endcap isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another…Exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide]; and
the higher-k dielectric cap [upper portion of SAGE 113/213] having an uppermost surface at a same level as an uppermost surface the first gate structure [104/204 left] and at a same level as an uppermost surface of the second gate structure [104/204 right].
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Subramanian891 fails to disclose in Fig. 1, Fig. 2
the second semiconductor fin comprises a second pair of semiconductor fins.
However, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI B.
For further support, Deng et al. is cited.
Deng et al. discloses in Fig. 2, paragraph [0038], [0057]
the second semiconductor fin comprises a second pair of semiconductor fins [102b][at least one second fin].
Deng et al. further discloses in Fig. 1I and paragraph [0038] that alternatively, the second semiconductor fin comprises a second single semiconductor fin.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Deng et al. into the method of Subramanian891 to include the second semiconductor fin comprises a second pair of semiconductor fins. The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of providing suitable number of second semiconductor fin the second gate formed across to yield a device having desired performance [paragraph [0038] of Deng et al.].
Regarding claim 9, Subramanian891 discloses in Fig. 1, Fig. 2, Fig. 9, paragraph [0026], [0030], [0083], [0099]-[0105] a computing device [900], comprising:
a board [902]; and
a component [904] coupled to the board [902], the component [904] including an integrated circuit structure, comprising:
a first gate structure [104/204 left] over a first pair of semiconductor fins [102/202 left];
a second gate structure [104/204 right] over a second semiconductor fin [102/202 right]; and
a first gate endcap isolation structure [113/213 middle] between the first gate structure [104/204 left] and the second gate structure [104/204 right]; and
a second gate endcap isolation structure [113/213 left] adjacent to the first gate structure [104/204 left], the first gate structure [104/204 left] between the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left],each of the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left] having a higher-k dielectric cap layer [upper portion of SAGE 113/213] on a lower-k dielectric wall [lower portion of SAGE 113/213], wherein the higher-k dielectric cap layer comprising hafnium oxygen [paragraph [0083], “self-aligned gate endcap isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another…Exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide]; and
the higher-k dielectric cap [upper portion of SAGE 113/213] having an uppermost surface at a same level as an uppermost surface the first gate structure [104/204 left] and at a same level as an uppermost surface of the second gate structure [104/204 right].
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Subramanian891 fails to disclose in Fig. 1, Fig. 2
the second semiconductor fin comprises a second pair of semiconductor fins.
However, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI B.
For further support, Deng et al. is cited.
Deng et al. discloses in Fig. 2, paragraph [0038], [0057]
the second semiconductor fin comprises a second pair of semiconductor fins [102b][at least one second fin].
Deng et al. further discloses in Fig. 1I and paragraph [0038] that alternatively, the second semiconductor fin comprises a second single semiconductor fin.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Deng et al. into the method of Subramanian891 to include the second semiconductor fin comprises a second pair of semiconductor fins. The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of providing suitable number of second semiconductor fin the second gate formed across to yield a device having desired performance [paragraph [0038] of Deng et al.].
Regarding claims 10-14, Subramanian891 discloses in Fig. 9, paragraph [0099]-[0105]
a memory [ROM, DRAM] coupled to the board [902];
a communication chip [906] coupled to the board [902];
a camera coupled to the board [902];
wherein the component [904] is a packaged integrated circuit die [paragraph [0102]];
wherein the computing device [900] is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set- top box [paragraph [0105]].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al. (US Pub. 20190305111), hereafter Subramanian111 in view of Deng et al. (US Pub. 20170141111) as applied to claim 1 above and further in view of Ando (US Pub. 20090230488).
Regarding claim 2, Subramanian111 fails to disclose
wherein the higher-k dielectric cap layer further comprises tantalum.
Ando discloses in Fig. 4, paragraph [0020], [0045]-[0046]
wherein the higher-k dielectric cap layer [235] further comprises tantalum.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ando into the method of Subramanian111 to include wherein the higher-k dielectric cap layer further comprises tantalum. The ordinary artisan would have been motivated to modify Subramanian111 in the above manner for the purpose of creating an interface that exhibits a larger quantity of fixed charges, reducing dark current, and/or improving the thermal stability of the isolation structure [paragraph [0020], [0046] of Ando].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al. (US Pub. 20190305111), hereafter Subramanian111 in view of Deng et al. (US Pub. 20170141111) as applied to claim 1 above and further in view of Ando (US Pub. 20090230488) and Chang et al. (US Pub. 20220328627).
Regarding claim 3, Subramanian111 fails to disclose
wherein the higher-k dielectric cap layer consists essentially of tantalum-doped hafnium oxide (Ta-HfO2) having 70% or greater monoclinic crystallinity.
Ando discloses in Fig. 4, paragraph [0020], [0045]-[0046]
wherein the higher-k dielectric cap layer [235] consists essentially of tantalum-doped hafnium oxide (Ta-HfO2).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ando into the method of Subramanian111 to include wherein the higher-k dielectric cap layer consists essentially of tantalum-doped hafnium oxide (Ta-HfO2). The ordinary artisan would have been motivated to modify Subramanian111 in the above manner for the purpose of creating an interface that exhibits a larger quantity of fixed charges, reducing dark current, and/or improving the thermal stability of the isolation structure [paragraph [0020], [0046] of Ando].
Subramanian111 and Ando fails to disclose
the higher-k dielectric cap layer having 70% or greater monoclinic crystallinity.
Chang et al. discloses in Fig. 14A-14E, paragraph [0044]-[0045], [0059], [0063], [0100]
the higher-k dielectric cap layer [80] having 70% or greater monoclinic crystallinity [it would be obvious that crystalline hafnium oxide can have the crystallinity up to 100%].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chang et al. into the method of Subramanian111 and Ando to include the higher-k dielectric cap layer having 70% or greater monoclinic crystallinity. The ordinary artisan would have been motivated to modify Subramanian111 and Ando in the above manner for the purpose of improving properties of the higher-k dielectric cap layer to protect the lower-k dielectric wall during the subsequent process [paragraph [0063] of Chang et al.].
In addition, Applicant has not provided criticality of the claimed range. The ordinary artisan would have been motivated to modify Chang et al., Subramanian111 and Ando to provide the claimed range for at least the purpose of optimization and routine experimentation to obtain the higher-k dielectric cap layer having desired properties. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
The combination of Subramanian111, Chang et al. and Ando would result to the limitation “wherein the higher-k dielectric cap layer consists essentially of tantalum-doped hafnium oxide (Ta-HfO2) having 70% or greater monoclinic crystallinity.”
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al. (US Pub. 20200286891), hereafter Subramanian891 in view of Deng et al. (US Pub. 20170141111) as applied to claim 1 above and further in view of Subramanian et al. (US Pub. 20190305112), hereafter Subramanian112.
Regarding claim 4, Subramanian891 fails to disclose
wherein the gate endcap isolation structure comprises a vertical seam centered within the lower-k dielectric wall.
Subramanian112 discloses in Fig. 9C, paragraph [0087], [0101]-[0102]
wherein the gate endcap isolation structure [926] comprises a vertical seam [958] centered within the lower-k dielectric wall [928 or 956].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Subramanian112 into the method of Subramanian891 to include wherein the gate endcap isolation structure comprises a vertical seam centered within the lower-k dielectric wall. The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of providing suitable configuration of a self-aligned gate endcap isolation structure including a multi-layer stack having lower portion and an upper portion higher dielectric constant material [paragraph [0087], [0102] of Subramanian112].
Claims 5, 7, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al. (US Pub. 20200286891), hereafter Subramanian891 in view of Deng et al. (US Pub. 20170141111) and Ando (US Pub. 20090230488).
Regarding claim 5, Subramanian891 discloses in Fig. 1, Fig. 2, paragraph [0026], [0030], and [0083] an integrated circuit structure, comprising:
a first gate structure [104/204 left] over a first pair of semiconductor fins [102/202 left];
a second gate structure [104/204 right] over a second semiconductor fin [102/202 right]; and
a first gate endcap isolation structure [113/213 middle] between the first gate structure [104/204 left] and the second gate structure [104/204 right]; and
a second gate endcap isolation structure [113/213 left] adjacent to the first gate structure [104/204 left], the first gate structure [104/204 left] between the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left], each of the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left] having a higher-k dielectric cap layer [upper portion of SAGE 113/213] on a lower-k dielectric wall [lower portion of SAGE 113/213], wherein the higher-k dielectric cap layer comprising hafnium oxygen [paragraph [0083], “self-aligned gate endcap isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another…Exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide]; and
the higher-k dielectric cap [upper portion of SAGE 113/213] having an uppermost surface at a same level as an uppermost surface the first gate structure [104/204 left] and at a same level as an uppermost surface of the second gate structure [104/204 right]; and
a local interconnect [106/206] on the first gate structure [104/204 left], on the higher-k dielectric cap layer [upper portion of SAGE 113/213] of the first gate endcap isolation structure [113/213 middle], and on the second gate structure [104/204 right], the local interconnect [106/206] having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer [upper portion of SAGE 113/213] of the first gate endcap isolation structure [113/213 middle].
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Subramanian891 fails to disclose in Fig. 1, Fig. 2
the second semiconductor fin comprises a second pair of semiconductor fins.
However, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI B.
For further support, Deng et al. is cited.
Deng et al. discloses in Fig. 2, paragraph [0038], [0057]
the second semiconductor fin comprises a second pair of semiconductor fins [102b][at least one second fin].
Deng et al. further discloses in Fig. 1I and paragraph [0038] that alternatively, the second semiconductor fin comprises a second single semiconductor fin.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Deng et al. into the method of Subramanian891 to include the second semiconductor fin comprises a second pair of semiconductor fins. The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of providing suitable number of second semiconductor fin the second gate formed across to yield a device having desired performance [paragraph [0038] of Deng et al.].
Subramanian891 fails to disclose
wherein the higher-k dielectric cap layer consists essentially of tantalum-doped hafnium oxide (Ta-HfO2).
Ando discloses in Fig. 4, paragraph [0020], [0045]-[0046]
wherein the higher-k dielectric cap layer [235] consists essentially of tantalum-doped hafnium oxide (Ta-HfO2)[an HfO2 which is doped with Ta].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ando into the method of Subramanian891 to include wherein the higher-k dielectric cap layer consists essentially of tantalum-doped hafnium oxide (Ta-HfO2). The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of creating an interface that exhibits a larger quantity of fixed charges, reducing dark current, and/or improving the thermal stability of the isolation structure [paragraph [0020], [0046] of Ando].
Regarding claim 7, Subramanian891 discloses in Fig. 2
wherein the local interconnect [206] electrically connects the first gate structure [204 left] and the second gate structure [204 right].
Regarding claim 15, Subramanian891 discloses in Fig. 1, Fig. 2, Fig. 9, paragraph [0026], [0030], [0083], [0099]-[0105] a computing device [900], comprising:
a board [902]; and
a component [904] coupled to the board [902], the component [904] including an integrated circuit structure, comprising:
a first gate structure [104/204 left] over a first pair of semiconductor fin [102/202 left];
a second gate structure [104/204 right] over a second semiconductor fin [102/202 right]; and
a first gate endcap isolation structure [113/213 middle] between the first gate structure [104/204 left] and the second gate structure [104/204 right]; and
a second gate endcap isolation structure [113/213 left] adjacent to the first gate structure [104/204 left], the first gate structure [104/204 left] between the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left], each of the first gate endcap isolation structure [113/213 middle] and the second gate endcap isolation structure [113/213 left] having a higher-k dielectric cap layer [upper portion of SAGE 113/213] on a lower-k dielectric wall [lower portion of SAGE 113/213], wherein the higher-k dielectric cap layer comprising hafnium oxygen [paragraph [0083], “self-aligned gate endcap isolation structures may be composed of a material or materials suitable to ultimately electrically isolate, or contribute to the isolation of, portions of permanent gate structures from one another…Exemplary materials or material combinations include a multi-layer stack having lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide]; and
the higher-k dielectric cap [upper portion of SAGE 113/213] having an uppermost surface at a same level as an uppermost surface the first gate structure [104/204 left] and at a same level as an uppermost surface of the second gate structure [104/204 right]; and
a local interconnect [106/206] on the first gate structure [104/204 left], on the higher-k dielectric cap layer [upper portion of SAGE 113/213] of the first gate endcap isolation structure [113/213 middle], and on the second gate structure [104/204 right], the local interconnect [106/206] having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer [upper portion of SAGE 113/213] of the first gate endcap isolation structure [113/213 middle].
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Subramanian891 fails to disclose in Fig. 1, Fig. 2
the second semiconductor fin comprises a second pair of semiconductor fins.
However, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI B.
For further support, Deng et al. is cited.
Deng et al. discloses in Fig. 2, paragraph [0038], [0057]
the second semiconductor fin comprises a second pair of semiconductor fins [102b][at least one second fin].
Deng et al. further discloses in Fig. 1I and paragraph [0038] that alternatively, the second semiconductor fin comprises a second single semiconductor fin.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Deng et al. into the method of Subramanian891 to include the second semiconductor fin comprises a second pair of semiconductor fins. The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of providing suitable number of second semiconductor fin the second gate formed across to yield a device having desired performance [paragraph [0038] of Deng et al.].
Subramanian891 fails to disclose
wherein the higher-k dielectric cap layer consists essentially of tantalum-doped hafnium oxide (Ta-HfO2).
Ando discloses in Fig. 4, paragraph [0020], [0045]-[0046]
wherein the higher-k dielectric cap layer [235] consists essentially of tantalum-doped hafnium oxide (Ta-HfO2)[an HfO2 which is doped with Ta].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ando into the method of Subramanian891 to include wherein the higher-k dielectric cap layer consists essentially of tantalum-doped hafnium oxide (Ta-HfO2). The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of creating an interface that exhibits a larger quantity of fixed charges, reducing dark current, and/or improving the thermal stability of the isolation structure [paragraph [0020], [0046] of Ando].
Regarding claims 16-20, Subramanian891 discloses in Fig. 9, paragraph [0099]-[0105]
a memory [ROM, DRAM] coupled to the board [902];
a communication chip [906] coupled to the board [902];
a camera coupled to the board [902];
wherein the component [904] is a packaged integrated circuit die [paragraph [0102]];
wherein the computing device [900] is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set- top box [paragraph [0105]].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Subramanian et al. (US Pub. 20200286891), hereafter Subramanian891 in view of Deng et al. (US Pub. 20170141111) and Ando (US Pub. 20090230488) as applied to claim 5 above and further in view of Subramanian et al. (US Pub. 20190305112), hereafter Subramanian112.
Regarding claim 8, Subramanian891 fails to disclose
wherein the gate endcap isolation structure comprises a vertical seam centered within the lower-k dielectric wall.
Subramanian112 discloses in Fig. 9C, paragraph [0087], [0101]-[0102]
wherein the gate endcap isolation structure [926] comprises a vertical seam [958] centered within the lower-k dielectric wall [928 or 956].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Subramanian112 into the method of Subramanian891 to include wherein the gate endcap isolation structure comprises a vertical seam centered within the lower-k dielectric wall. The ordinary artisan would have been motivated to modify Subramanian891 in the above manner for the purpose of providing suitable configuration of a self-aligned gate endcap isolation structure including a multi-layer stack having lower portion and an upper portion higher dielectric constant material [paragraph [0087], [0102] of Subramanian112].
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7-20 have been considered but are moot in view of the new ground of rejection and in view of the newly cited prior art.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
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