Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements submitted on 12/21/2021 and 08/01/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of Claims
The present application is being examined under the claims filed on 12/21/2021.
Claims 1-20, 22-26 are rejected.
Claims 1-20, 22-26 are pending.
Claims 21, 27-39 are canceled.
Response to Remarks
In reference to the objection to the title.
Examiner response:
Applicant’s amendment to the title is acceptable and the objection is withdrawn.
In reference to the 101 remarks.
Applicant remarks:
“The Federal Circuit has held claims resulting in a technological improvement as directed to patent-eligible subject matter regardless of the claimed improvement being implemented on "general-purpose computer equipment" or "conventional computer components." See Enfish 822 F.3d at 1338-39 (describing that "[m]oreover, we are not persuaded that the invention's ability to run on a general-purpose computer dooms the claims" and that "[s]imilarly, that the improvement is not defined by reference to 'physical' components does not doom the claims .... Much of the advancement made in computer technology consists of improvements to software that, by their very nature, may not be defined by particular physical features but rather by logical structures and processes. We do not see in Bilski or Alice, or our cases, an exclusion to patenting this large field of technological progress"). See also, e.g., Core Wireless, 880 F.3d at 1362-63 (finding that "[t]he asserted claims in this case are directed to an improved user interface for computing devices ... " and "[l]ike the improved systems claimed in Enfish, Visual Memory, and Finjan, these claims recite a specific improvement over prior systems, resulting in an improved user interface for electronic devices") (emphasis added); Finjan, 879 F.3d at 1305 (describing that "[s]imilarly, the method of claim 1 employs a new kind of file that enables a computer security system to do things it could not do before") (emphasis added); Enfish, 822 F3d at 1337- 38, so too are claims directed to a new and useful technique for using sensors to more efficiently track an object on a moving platform") (emphasis added); Visual Memory 867 F.3d at 1262 (describing that "[n]or is the '740 patent's use of conventional computer components, by itself, fatal to patent eligibility where the claims are 'directed to an improvement in the functioning of a computer.' Enfish, 822 F 3d at 1338") (emphasis added); and McRO, 837 F.3d at 1316 (finding that "[w]hen looked at as a whole, claim 1 is directed to a patentable, technological improvement over the existing, manual 3-D animation techniques. The claim uses the limited rules in a process specifically designed to achieve an improved technological result in conventional industry practice.") (emphasis added).
Looking to the instant specification confirms the eligibility of claim 1 under§ 101. For example, the Enfish court looked to the specification of the patent at issue which confirmed the technological improvement over conventional database structures as not requiring preconfiguration of a database structure and additionally having increased flexibility, faster search times, and smaller memory requirements compared to traditional databases. Enfish, 822 F.3d at 1337. Similarly, here, the Applicant's specification confirms that claim 1 improves the functionality of a computer itself” (pg. 18-19)
Examiner response:
Applicant’s arguments filed have been fully considered and they are persuasive. The 35 U.S.C. 101 rejections have been withdrawn.
In reference to the 102, 103 remarks.
Applicant remarks:
“the foregoing amendments render the § 103 rejections moot. Therefore, the art-based rejections of claims 9, 13-14, 18, 19 and 21-25 are not discussed further herein.” (pg. 22)
“Samsung does not teach or suggest each and every limitation of claim 1.” (pg. 23)
Examiner response:
Applicant’s arguments filed have been fully considered and they are persuasive. The amended claim language overcomes the previous prior art rejection and further search and consideration are required. The claims previously taught by Samsung and rejected under 35 U.S.C. 102 have been updated below to be rejected under 35 U.S.C. 103 as being taught by Samsung in view of Tenne in further view of Soliman.
Claim Interpretation – 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Such claim limitation(s) are:
Claim #
Claim Text (bold indicates interpretation under 35 U.S.C. 112(f))
12
An apparatus to generate a compute node, the apparatus comprising: first means for generating a first configuration of one or more machine-learning models based on a workload (support in [00109] “processor”, “ASIC”, “FPGA”, etc.), the first configuration stored in a first configuration database, the first configuration database including a plurality of machine-learning models, the plurality of the machine-learning models including the one or more machine-learning models; second means for generating a second configuration of hardware (support in [001131] “processor”, “ASIC”, “FPGA”, etc.), the second configuration stored in a second configuration database, the second configuration database including one or more portions of a plurality of hardware, the plurality of the hardware including the hardware; means for determining an evaluation parameter based on an execution of the workload (support in [00117] “processor”, “ASIC”, “FPGA”, etc.), the execution of the workload based on the first configuration and the second configuration; and means for executing the one or more machine-learning models (support in [00119] “processor”, “ASIC”, “FPGA”, etc.) in the first configuration on the hardware in the second configuration in response to the evaluation parameter satisfying a threshold, the one or more machine-learning models and the hardware to execute the workload.
13
13. The apparatus of claim 12, wherein the one or more portions include at least one of a first block, a second block, or a third block, and the second means for generating is to (support as in claim 12): identify the first block of the hardware to execute a matrix-matrix workload; identify the second block of the hardware to execute a vector-vector workload; identify the third block of the hardware to execute a matrix-vector workload; and identify register files for respective ones of the first block, the second block, and the third block, the register files to store states for the respective ones of the first block, the second block, and the third block, the second configuration based on a topology including at least one of the first block, the second block, or the third block.
14
14. The apparatus of claim 12, wherein the one or more machine-learning models include a first machine-learning model, and the first means for generating is to (support as in claim 12), in response to the evaluation parameter not satisfying the threshold: identify a second machine-learning model in the first configuration database; generate a third configuration of the second machine-learning model; determine the evaluation parameter based on an execution of the workload based on the third configuration; and deploy the second machine-learning model to execute the workload based on the third configuration.
15
15. The apparatus of claim 12, wherein the one or more machine-learning models include a first machine-learning model, and the first means for generating is to (support as in claim 12), in response to the evaluation parameter not satisfying the threshold: determine one or more first layers of the first machine-learning model to execute a first portion of the workload; identify a second machine-learning model in the first configuration database; determine one or more second layers of the second machine-learning model to execute a second portion of the workload; and determine a third configuration based on a topology of the one or more first layers and the one or more second layers, the topology based on an output from the one or more first layers as an input to the one or more second layers.
16
16. The apparatus of claim 12, wherein the one or more machine-learning models include a first machine-learning model, and the first means for generating is to (support as in claim 12): identify the first machine-learning model in the first configuration database; identify a second machine-learning model based on a query of an ontology database with an identifier of the first machine-learning model as an input, the ontology database including an association of the first machine-learning model and the second machine-learning model; and in response to the evaluation parameter satisfying the threshold, update the ontology database based on the first configuration.
17
17. The apparatus of claim 12, wherein the hardware is first hardware, and the second means for generating is to (support as in claim 12), in response to the evaluation parameter not satisfying the threshold: identify second hardware in the second configuration database; generate a third configuration of the second hardware; determine the evaluation parameter based on an execution of the workload by the second hardware in the third configuration; and deploy the second hardware with the third configuration to execute the one or more machine-learning models to execute the workload.
18
18. The apparatus of claim 12, wherein the hardware is first hardware, and the second means for generating is to (support as in claim 12), in response to the evaluation parameter not satisfying the threshold: determine one or more first portions of the first hardware to execute a first portion of the workload; identify second hardware in the first configuration database; determine one or more second portions of the second hardware to execute a second portion of the workload; and determine a third configuration based on a topology of the one or more first portions and the one or more second portions, the topology based on an output from the one or more first portions as an input to the one or more second portions.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Prior Art References
The short names that are used to identify the references of prior art in the analysis that follows are:
Short Name
Reference
Samsung
[US20210081763A1] Samsung, Electronic Device..., 2020
Oracle
[US20210081848A1] Oracle, Techniques for Adaptive Pipelining Composition for Machine Learning (ML), 2021
Soliman
Soliman et al., FPGA Implementation and Evaluation of a Simple Processor for Multi-scalar/vector/matrix instructions, 2014
Lenc
Lenc et al., Understanding Image Representations 2015 CVPR, 2015
Li
Li et al., Improving CNN Performance on FPGA Clusters through, March 2021
Tenne
Tenne, Y., 2017, June. An adaptive ensemble-based algorithm. In AIP Conference Proceedings (Vol. 1836, No. 1, p. 020040). AIP Publishing LLC.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 and 22-26 are rejected under 35 U.S.C. 103.
35 U.S.C. 103 – Samsung, Tenne, Soliman
Claims 1,2,3,4,7,9,10,11,12,13,14,17,19,20,22,23,26 are rejected under 35 U.S.C. 103 as being unpatentable over Samsung in view of Tenne, in further view of Soliman.
In reference to claim 1.
Samsung teaches:
— “1. (Currently Amended) An apparatus to generate a compute node, the apparatus comprising: interface circuitry to receive a workload; instructions in the apparatus; and processor circuitry to at least one of execute or instantiate the instructions to:” (Samsung [0040], “The memory 110 may store instructions or data related to at least one other component of the electronic device 100. An instruction may refer, for example, to one action statement which can be executed by the processor 120 in a program creation language, and may be a minimum unit for the execution or operation of the program. The memory 110 may be accessed by the processor 120, and reading/writing/modifying/updating, or the like, data by the processor 120 may be performed.”)
— “generate one or more machine-learning models in a software configuration based on the workload and based on a software configuration database,” (Samsung [0042, 0046], “The memory 110 may store a plurality of accelerators (e.g., including various processing circuitry and/or executable program elements) 10-1, 10-2, ... , 10-N and a plurality of neural networks (e.g., including various processing circuitry and/or executable program elements) 20-1, 20-2, ... , 20-N. [...] In one example, the accelerator may be implemented as a platform for implementing a neural network, such as, for example, and without limitation, a field-programmable gate-array (FPGA) accelerator or an application-specific integrated circuit (ASIC), or the like.”)
Generating one or more ML models is taught by “the accelerator may be implemented as a platform for implementing a neural network”.
A software configuration based on the workload is taught by the evaluative process described in Samsung for iterating over model and accelerator alternatives.
A software configuration based on the software configuration database is taught by “The memory 110 may store […] a plurality of neural networks”
— “the software configuration database including descriptions of various machine-learning model properties,” (Samsung [0042], “The memory 110 may store […] a plurality of neural networks (e.g., including various processing circuitry and/or executable program elements) 20-1, 20-2, ... , 20-N.”)
The software configuration database including various ML model descriptions is taught by “The memory 110 may store […] a plurality of neural networks”. The neural network itself is descriptive.
— “generate a hardware configuration of hardware based on the workload and based on a hardware configuration database, (Samsung [0042, 0046], “The memory 110 may store a plurality of accelerators (e.g., including various processing circuitry and/or executable program elements) 10-1, 10-2, ... , 10-N and a plurality of neural networks (e.g., including various processing circuitry and/or executable program elements) 20-1, 20-2, ... , 20-N. [...] In one example, the accelerator may be implemented as a platform for implementing a neural network, such as, for example, and without limitation, a field-programmable gate-array (FPGA) accelerator or an application-specific integrated circuit (ASIC), or the like.”)
Generating a hardware configuration is taught by “the accelerator may be implemented as a platform for implementing a neural network”.
A hardware configuration based on the workload is taught by the evaluative process described in Samsung for iterating over model and accelerator alternatives.
A hardware configuration based on a hardware configuration database is taught by “The memory 110 may store a plurality of accelerators (e.g., including various processing circuitry and/or executable program elements) 10-1, 10-2, ... , 10-N”
— the hardware configuration database including at least a description of a first portion of execution hardware and a description of a second portion of the execution hardware,” (Samsung [0042], “The memory 110 may store a plurality of accelerators (e.g., including various processing circuitry and/or executable program elements) 10-1, 10-2, ... , 10-N”)
The hardware configuration database including hardware descriptions is taught by “The memory 110 may store a plurality of accelerators (e.g., including various processing circuitry and/or executable program elements) 10-1, 10-2, ... , 10-N”.
— “determine an evaluation parameter by executing first portions of the one or more machine-learning models with the first portion of the execution hardware and executing second portions of the one or machine-learning models with the second portion of the execution hardware, [the executing based on the software topology and the hardware topology];” (Samsung [0088], “The electronic device 100 can obtain an estimated value of the hardware performance corresponding to the first neural network through the second predictive model in step S320.”)
— “determine whether the evaluation parameter satisfies a threshold; after a determination that the evaluation parameter does not satisfy the threshold, iteratively generate one or more machine-learning models in another software configuration based on the workload and the software configuration database, generate another hardware configuration based on the workload and the hardware configuration database, or update the evaluation parameter and after a determination that the evaluation parameter satisfies the threshold, execute the workload according to a software topology in a most recent software configuration and according to a hardware topology in a most recent hardware configuration.” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”) (Samsung [0091], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network and the first accelerator satisfies the second hardware criteria (“Yes” in S330), the electronic device 100 can select the accelerator to implement the first neural network among the plurality of accelerators in step S350.”)
The estimated value of the hardware performance not satisfying the second hardware reference teaches iteratively generating another software and hardware configuration.
The estimated value of the hardware performance satisfying the second hardware criteria teaches determining whether the evaluation parameter satisfies a threshold.
The electronic device selecting the accelerator and neural network teaches executing the workload according to the software and hardware configurations.
Tenne teaches:
— “the software configuration to connect the one or more machine-learning models to one another in a software topology;” (Tenne 2, “As an example, Table 1 shows the prediction accuracies of different ensemble topologies consisting of radial basis functions (RBFs), radial basis functions neural network (RBFN), and Kriging metamodels. […] It follows that the optimal topology varied between the cases, and that no single topology was the overall best. To address this issue the proposed algorithm dynamically adapts the ensemble topology, as explained in Section 3.”)
Table 1 teaches software configurations for connecting ensemble topologies.
Motivation to combine Samsung and Tenne.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Samsung and Tenne. Samsung discloses a system and method for optimizing machine-learning model performance on arbitrary hardware. Tenne teaches an adaptive ensemble algorithm. One would be motivated to combine these two references because the machine learning models of Samsung could be expanded to include ensemble models for increased accuracy. One of ordinary skill would have motivation to combine these references because MPEP 2143 sets forth the Supreme Court rationales for obviousness including:
(E) "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
Soliman teaches:
— “the executing based on the software topology and the hardware topology;” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
— “the hardware configuration to connect the first portion of the execution hardware and the second portion of the execution hardware to one another in a hardware topology;” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
The dependency checking of the instructions and subsequent parallel execution teaches execution in a hardware topology.
Motivation to combine Samsung, Tenne and Soliman.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Samsung and Soliman. Samsung, Tenne discloses a system and method for optimizing machine-learning model performance on arbitrary hardware. Soliman teaches FPGA operations regarding vector and matrix mathematics. One would be motivated to combine these two references because optimizing the matrix algebra performed on the target hardware of Samsung would in turn provide further performance gains of the overall system. One of ordinary skill would have motivation to combine these references because MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results.
In reference to claim 2.
Samsung teaches:
— “2. (Currently Amended) The apparatus of claim 1, wherein the software configuration database includes at least one of a number of model layers, weights for the model layers, a type of machine-learning training, or one or more hyperparameters associated with the one or more machine-learning models.” (Samsung [0045], “The first configurable parameter may include at least one of an operational mode of each neural network, or a layer connection scheme. The operational mode may include the type of operation performed between layers included in the neural network, the number of times, and the like. The layer connection scheme may include the number of layers included in each operation network, the number of stacks or cells included in the layer, the connection relationship between layers, and the like.”)
In reference to claim 3.
— “3. (Currently Amended) The apparatus of claim 1, wherein the execution hardware is first execution hardware , and wherein the processor circuitry is to at least one of execute or instantiate the instructions to:” (preamble)
Samsung teaches:
— “identify the first portion of the first execution hardware to execute a matrix-matrix workload; identify the second portion of the first execution hardware to execute a vector- vector workload; identify second execution hardware described in the hardware configuration database, the second execution hardware to execute a matrix-vector workload;” (Samsung FIG. 6 402, “CPU - Control unit and scheduler”, Examiner notes that the hardware mentioned in the claim language are not necessarily distinct and thus may all refer to the same one block of hardware (Instant specification; [0023]; “In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.”“. Thus, Figure 6 of Samsung teaches the processor circuitry (i.e., CPU) that identifies the block of hardware to execute matrix and vector workloads (i.e. the FPGA).)
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Soliman teaches:
— “and identify register files for respective ones of the first portion of the first execution hardware, the second portion of the execution hardware, and the second execution hardware, the register files to store states for the respective ones of the first portion of the first execution hardware, the second portion of the execution hardware, and the second execution hardware, the hardware configuration based on a topology including at least one of the first portion of the first execution hardware, the second portion of the execution hardware, and the second execution hardware.” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
In reference to claim 4.
Samsung teaches:
— “4. (Currently Amended) The apparatus of claim 1, wherein to iteratively generate one or more machine-learning models in another software configuration based on the workload and the software configuration database, and to iteratively update the evaluation parameter, the processor circuitry is to at least one of execute or instantiate the instructions to generate a third machine-learning model based on the workload and the software configuration database;” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
— “and redetermine the evaluation parameter based on an execution of the third machine-learning model to perform the workload.” (Samsung; [0093]; “The electronic device 100 can obtain the reward value based on the information related to the obtained implementation in step S408.”)
In reference to claim 7.
— “7. (Currently Amended) The apparatus of claim 1,” (preamble)
Samsung teaches:
— “wherein the execution hardware is first execution hardware, wherein the hardware configuration is a first hardware configuration, and wherein to iteratively generate another hardware configuration based on the workload and the hardware configuration database, and to iteratively update the evaluation parameter, [[and]] the processor circuitry is to at least one of execute or instantiate the instructions to generate a second hardware configuration that includes second execution hardware described in the hardware configuration database;” (Samsung [0084], “If the estimated value of the hardware performance corresponding to the first neural network and the first accelerator does not satisfy the first hardware criteria (“No” in S230), the electronic device 100 can select a second accelerator to implement the first neural network among the accelerators except the first accelerator in step S240. That an estimated value of the hardware performance corresponding to the first neural network and the first accelerator does not satisfy the first hardware criteria may mean that a high reward value may not be obtained via the first neural network and the first accelerator.”)
— “and redetermine the evaluation parameter based on an execution of the workload by the second hardware configuration.” (Samsung [0088], “The electronic device 100 can obtain an estimated value of the hardware performance corresponding to the first neural network through the second predictive model in step S320.”)
In reference to claim 9.
Samsung teaches:
— “9. (Currently Amended) The apparatus of claim [[8]] 1, wherein the execution hardware [[are]] is one of a central processor unit, a graphics processing unit, a digital signal processor, an Artificial Intelligence processor, a Neural Network processor, or a Field Programmable Gate Array.” (Samsung [0046], “The accelerator may refer, for example, to a hardware device capable of increasing the amount or processing speed of data to be processed by a neural network learned on the basis of an artificial intelligence (AI) algorithm. In one example, the accelerator may be implemented as a platform for implementing a neural network, such as, for example, and without limitation, a field-programmable gate-array (FPGA) accelerator or an application-specific integrated circuit (ASIC), or the like.”)
In reference to claim 10.
Samsung teaches:
— “10. (Currently Amended) The apparatus of claim 1, wherein the evaluation parameter is a first evaluation parameter, and the processor circuitry is to at least one of execute or instantiate the instructions to:” (preamble)
— “output a reward function including the first evaluation parameter with a first weight and a second evaluation parameter with a second weight, the first weight greater than the second weight;” (Samsung [0071, 0072], “As described above, the evaluation model 30 may normalize the accuracy metrics and the efficiency metrics, and perform a weighted sum operation on the normalized index to output a reward value. […] If the first reward value is obtained by implementing the first neural network on the first accelerator, the processor 120 may select a second neural network to be implemented on the first accelerator of the plurality of neural networks. The processor 120 may select a second neural network by searching for a neural network that may obtain a higher reward value than when implementing the first neural network on the first accelerator among the plurality of neural networks.”)
— “and in response to determining that at least one of the first evaluation parameter or the second evaluation parameter does not satisfy the threshold, generate at least another software configuration or another hardware configuration to at least one of increase the first evaluation parameter or decrease the second evaluation parameter.” (Samsung, FIG. 2 FIG. 3 S230 S240 S250 S330 S340 S350)
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In reference to claim 11.
— “11. (Original) The apparatus of claim 1,” (preamble)
Samsung teaches:
— “wherein the evaluation parameter is at least one of an accuracy, a cost, an energy consumption, a latency, a performance, or a throughput associated with at least one of the one or more machine-learning models or the hardware.” (Samsung [0049, 0053], “The evaluation model 30 may perform a weighted sum operation on the normalized accuracy metrics and the efficiency metrics to output a reward value. [...] The accuracy metrics may refer, for example, to a value that indicates with which accuracy the neural network has been implemented on the accelerator. The efficiency metrics may refer, for example, to a value that indicates at which degree the neural networks can perform an optimized implementation on the accelerator. The efficiency metrics may include, for example, and without limitation, at least one of a latency metrics, a power metrics, an area metrics of the accelerator when a neural network is implemented on the accelerator, or the like.”)
In reference to claim 12.
— “12. (Currently Amended) An apparatus to generate a compute node, the apparatus comprising:” (preamble)
Samsung teaches:
— “first means for generating a software configuration of one or more machine-learning models based on a workload and based on a software configuration database, the software configuration database including descriptions of various machine-learning model properties, [the software configuration to connect the one or more machine- earning models to one another in a software topology]; second means for generating a hardware configuration of hardware based on the workload and based on a hardware configuration database, the hardware configuration database including at least a description of a first portion of execution hardware and a description of a second portion of the execution hardware, [the hardware configuration to connect the first portion of the execution hardware and the second portion of the execution hardware to one another in a hardware topology];” (Samsung [0042, 0046], “The memory 110 may store a plurality of accelerators (e.g., including various processing circuitry and/or executable program elements) 10-1, 10-2, ... , 10-N and a plurality of neural networks (e.g., including various processing circuitry and/or executable program elements) 20-1, 20-2, ... , 20-N. [...] In one example, the accelerator may be implemented as a platform for implementing a neural network, such as, for example, and without limitation, a field-programmable gate-array (FPGA) accelerator or an application-specific integrated circuit (ASIC), or the like.”)
The means for generating one generating configurations is taught by “the accelerator may be implemented as a platform for implementing a neural network”.
A software configuration based on the workload is taught by the evaluative process described in Samsung for iterating over model and accelerator alternatives.
A software configuration based on the software configuration database is taught by “The memory 110 may store […] a plurality of neural networks”
— “means for determining an evaluation parameter by executing first portions of the one or more machine-learning by executing first portions of the one or more machine-learning models with the first portion of the execution hardware and executing second portions of the one or machine-learning models with the second portion of the execution hardware, [the executing based on the software configuration and the hardware configuration];” (Samsung [0088], “The electronic device 100 can obtain an estimated value of the hardware performance corresponding to the first neural network through the second predictive model in step S320.”)
— “the means for determining the evaluation parameter to determine whether the evaluation parameter satisfies a threshold; the first means for generating, the second means for generating, and the means for determining to, after a determination that the evaluation parameter does not satisfy the threshold, iteratively generate one or more machine-learning models in another software configuration based on the workload and the software configuration database, generate another hardware configuration based on the workload and the hardware configuration database, or update the evaluation parameter; and means for executing the workload according to a software topology in a most recent software configuration and according to a hardware topology in most recent hardware configuration, the execution after a determination that the evaluation parameter satisfies the threshold.” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”) (Samsung [0091], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network and the first accelerator satisfies the second hardware criteria (“Yes” in S330), the electronic device 100 can select the accelerator to implement the first neural network among the plurality of accelerators in step S350.”)
The estimated value of the hardware performance not satisfying the second hardware reference teaches iteratively generating another software and hardware configuration.
The estimated value of the hardware performance satisfying the second hardware criteria teaches determining whether the evaluation parameter satisfies a threshold.
The electronic device selecting the accelerator and neural network teaches executing the workload according to the software and hardware configurations.
Tenne teaches:
— “the software configuration to connect the one or more machine-learning models to one another in a software topology” (Tenne 2, “As an example, Table 1 shows the prediction accuracies of different ensemble topologies consisting of radial basis functions (RBFs), radial basis functions neural network (RBFN), and Kriging metamodels. […] It follows that the optimal topology varied between the cases, and that no single topology was the overall best. To address this issue the proposed algorithm dynamically adapts the ensemble topology, as explained in Section 3.”)
Table 1 teaches software configurations for connecting ensemble topologies.
Soliman teaches:
— “the hardware configuration to connect the first portion of the execution hardware and the second portion of the execution hardware to one another in a hardware topology” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
The dependency checking of the instructions and subsequent parallel execution teaches execution in a hardware topology.
— “the executing based on the software configuration and the hardware configuration” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
In reference to claim 13.
— “13. (Currently Amended) The apparatus of claim 12, wherein the execution hardware is first execution hardware, and wherein the second means for generating is to:” (preamble)
Samsung teaches:
— “identify the first portion of the first execution hardware to execute a matrix-matrix workload; identify the second portion of the first execution hardware to execute a vector- vector workload; identify second execution hardware described in the hardware configuration database, the second execution hardware to execute a matrix-vector workload;” (Samsung FIG. 6 402, “CPU - Control unit and scheduler”, Examiner notes that the hardware mentioned in the claim language are not necessarily distinct and thus may all refer to the same one block of hardware (Instant specification; [0023]; “In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.”“. Thus, Figure 6 of Samsung teaches the processor circuitry (i.e., CPU) that identifies the block of hardware to execute matrix and vector workloads (i.e. the FPGA).)
Soliman teaches:
— “and identify register files for respective ones of the first portion of the first execution hardware, the second portion of the execution hardware, and the second execution hardware, the register files to store states for the respective ones of the first block portion of the first execution hardware, the second block portion of the execution hardware, and the third block second execution hardware, the second hardware configuration based on a topology including at least one of the first block portion of the first execution hardware, the second block portion of the execution hardware, and the third block second execution hardware.” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
In reference to claim 14.
Samsung teaches:
— “14. (Currently Amended) The apparatus of claim 12, to iteratively generate one or more machine- learning models in another software configuration based on the workload and the software configuration database, and to iteratively update the evaluation parameter the first means for generating and the means for determining are to generate a third machine-learning model based on the workload and the software configuration database;” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
— “and redetermine the evaluation parameter based on an execution of the third machine-learning model to perform the workload.” (Samsung [0093], “The electronic device 100 can obtain the reward value based on the information related to the obtained implementation in step S408.”)
In reference to claim 17.
Samsung teaches:
— “17. (Currently Amended) The apparatus of claim 12, execution hardware is first execution hardware, wherein the hardware configuration is a first hardware configuration, and wherein to iteratively generate another hardware configuration based on the workload and the hardware configuration database, and to iteratively update the evaluation parameter, [[and]] the second means for generating and the means for determining [[is]] are to generate a second hardware configuration that includes second execution hardware described in the hardware configuration database;” (Samsung [0084], “If the estimated value of the hardware performance corresponding to the first neural network and the first accelerator does not satisfy the first hardware criteria (“No” in S230), the electronic device 100 can select a second accelerator to implement the first neural network among the accelerators except the first accelerator in step S240. That an estimated value of the hardware performance corresponding to the first neural network and the first accelerator does not satisfy the first hardware criteria may mean that a high reward value may not be obtained via the first neural network and the first accelerator.”)
— “and redetermine the evaluation parameter based on an execution of the workload by the second hardware configuration.” (Samsung [0088], “The electronic device 100 can obtain an estimated value of the hardware performance corresponding to the first neural network through the second predictive model in step S320.”)
In reference to claim 19.
— “19. (Currently Amended) The apparatus of claim 12, wherein the evaluation parameter is a first evaluation parameter, and the means for determining is to:” (preamble)
Samsung teaches:
— “determine a reward function including the first evaluation parameter with a first weight and a second evaluation parameter with a second weight, the first weight greater than the second weight;” (Samsung; [0071], [0072]; “As described above, the evaluation model 30 may normalize the accuracy metrics and the efficiency metrics, and perform a weighted sum operation on the normalized index to output a reward value. […] If the first reward value is obtained by implementing the first neural network on the first accelerator, the processor 120 may select a second neural network to be implemented on the first accelerator of the plurality of neural networks. The processor 120 may select a second neural network by searching for a neural network that may obtain a higher reward value than when implementing the first neural network on the first accelerator among the plurality of neural networks.”)
— “and in response to determining that at least one of the first evaluation parameter or the second evaluation parameter does not satisfy the threshold, generate at least another software configuration or another hardware configuration to at least one of increase the first evaluation parameter or decrease the second evaluation parameter.” (Samsung, FIG. 2 FIG. 3 S230 S240 S250 S330 S340 S350)
In reference to claim 20.
— “20. (Currently Amended) At least one non-transitory computer readable storage medium comprising instructions that, when executed, cause processor circuitry to at least:” (preamble)
Samsung teaches:
— “generate one or more machine-learning models in a software configuration based on [[the]] a workload and based on a software configuration database, the software configuration database including-descriptions of various machine-learning model properties, [the software configuration to the software configuration to connect the one or more machine-learning models to one another in a software topology]; generate a hardware configuration of hardware based on the workload and based on a hardware configuration database, the hardware configuration database including at least a description of a first portion of execution hardware and a description of a second portion of the execution hardware, [the hardware configuration to connect the first portion of the execution hardware and the second portion of the execution hardware to one another in a hardware topology];” (Samsung [0042, 0046], “The memory 110 may store a plurality of accelerators (e.g., including various processing circuitry and/or executable program elements) 10-1, 10-2, ... , 10-N and a plurality of neural networks (e.g., including various processing circuitry and/or executable program elements) 20-1, 20-2, ... , 20-N. [...] In one example, the accelerator may be implemented as a platform for implementing a neural network, such as, for example, and without limitation, a field-programmable gate-array (FPGA) accelerator or an application-specific integrated circuit (ASIC), or the like.”)
The means for generating one generating configurations is taught by “the accelerator may be implemented as a platform for implementing a neural network”.
A software configuration based on the workload is taught by the evaluative process described in Samsung for iterating over model and accelerator alternatives.
A software configuration based on the software configuration database is taught by “The memory 110 may store […] a plurality of neural networks”
— “determine an evaluation parameter by executing first portions of the one or more machine-learning models with the first portion of the execution hardware and executing second portions of the one or machine- learning models with the second portion of the execution hardware, [the executing based on the software configuration and the hardware configuration];” (Samsung [0088], “The electronic device 100 can obtain an estimated value of the hardware performance corresponding to the first neural network through the second predictive model in step S320.”)
— “determine whether the evaluation parameter satisfies a threshold; after a determination that the evaluation parameter does not satisfy the threshold, iteratively generate one or more machine-learning models in another software configuration based on the workload and the software configuration database, generate another hardware configuration based on the workload and the hardware configuration database, or update the evaluation parameter; and after a determination that the evaluation parameter satisfies the threshold, execute the workload according to a software topology in a most recent software configuration and according to a hardware topology in a most recent hardware configuration.” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”) (Samsung [0091], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network and the first accelerator satisfies the second hardware criteria (“Yes” in S330), the electronic device 100 can select the accelerator to implement the first neural network among the plurality of accelerators in step S350.”)
The estimated value of the hardware performance not satisfying the second hardware reference teaches iteratively generating another software and hardware configuration.
The estimated value of the hardware performance satisfying the second hardware criteria teaches determining whether the evaluation parameter satisfies a threshold.
The electronic device selecting the accelerator and neural network teaches executing the workload according to the software and hardware configurations.
Tenne teaches:
— “the software configuration to connect the one or more machine- earning models to one another in a software topology” (Tenne 2, “As an example, Table 1 shows the prediction accuracies of different ensemble topologies consisting of radial basis functions (RBFs), radial basis functions neural network (RBFN), and Kriging metamodels. […] It follows that the optimal topology varied between the cases, and that no single topology was the overall best. To address this issue the proposed algorithm dynamically adapts the ensemble topology, as explained in Section 3.”)
Table 1 teaches software configurations for connecting ensemble topologies.
Soliman teaches:
— “the hardware configuration to connect the first portion of the execution hardware and the second portion of the execution hardware to one another in a hardware topology” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
— “the executing based on the software configuration and the hardware configuration” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
In reference to claim 22.
— “22. (Currently Amended) The at least one non-transitory computer readable storage medium of claim 20, wherein the execution hardware is first execution hardware , and wherein the instructions, when executed, cause the processor circuitry to:” (preamble)
Samsung teaches:
— “select the first portion of the first execution hardware to execute a matrix-matrix workload; select the second portion of the first execution hardware to execute a vector-vector workload; select second execution hardware described in the hardware configuration database, the second execution hardware to execute a matrix-vector workload;” (Samsung FIG. 6 402, “CPU - Control unit and scheduler”, Examiner notes that the hardware mentioned in the claim language are not necessarily distinct and thus may all refer to the same one block of hardware (Instant specification; [0023]; “In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.”“. Thus, Figure 6 of Samsung teaches the processor circuitry (i.e., CPU) that identifies the block of hardware to execute matrix and vector workloads (i.e. the FPGA).)
Soliman teaches:
— “and create register files for respective ones of the first portion of the first execution hardware, the second portion of the execution hardware, and the second execution hardware, the register files to store states for the respective ones of the first portion of the first execution hardware, the second portion of the execution hardware, and the second execution hardware, the hardware configuration based on a topology including at least one of the first portion of the first execution hardware, the second portion of the execution hardware, and the second execution hardware.” (Soliman 1, “The parallelism found in data-parallel applications can be explicitly expressed directly to SuperSMP in the following sets of instructions: scalar-scalar instructions (OD DLP), vector-scalar instructions (ID DLP), vector-vector instructions (ID DLP), matrix-scalar instructions (2D DLP), matrix-vector instruction (2D DLP), and matrix-matrix instructions (2D or 3D DLP). [...] Like simple in-order superscalar processors, SuperSMP fetches multiple instructions, decodes and checks dependency among fetched instructions executes multiple scalar/vector/matrix operations on parallel execution units, and writes back multiple scalar/vector/matrix results into scalar/matrix register files.”)
In reference to claim 23.
Samsung teaches:
— “23. (Currently Amended) The at least one non-transitory computer readable storage medium of claim 20, wherein to iteratively generate one or more machine-learning models in another software configuration based on the workload and the software configuration database, and to iteratively update the evaluation parameter, the instructions, when executed, cause the processor circuitry to generate a third machine-learning model based on the workload and the software configuration database;” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
— “and redetermine the evaluation parameter based on an execution of the third machine-learning model to perform the workload.” (Samsung; [0093]; “The electronic device 100 can obtain the reward value based on the information related to the obtained implementation in step S408.”)
In reference to claim 26.
Samsung teaches:
— “26. (Currently Amended) The at least one non-transitory computer readable storage medium of claim 20, wherein the hardware is first hardware, and the instructions, when executed, cause the processor circuitry to, in response to the evaluation parameter not satisfying the threshold: generate a second hardware configuration that includes second execution hardware described in the hardware configuration database;” (Samsung [0084], “If the estimated value of the hardware performance corresponding to the first neural network and the first accelerator does not satisfy the first hardware criteria (“No” in S230), the electronic device 100 can select a second accelerator to implement the first neural network among the accelerators except the first accelerator in step S240. That an estimated value of the hardware performance corresponding to the first neural network and the first accelerator does not satisfy the first hardware criteria may mean that a high reward value may not be obtained via the first neural network and the first accelerator.”)
— “and redetermine the evaluation parameter based on an execution of the workload by the second hardware configuration.” (Samsung [0088], “The electronic device 100 can obtain an estimated value of the hardware performance corresponding to the first neural network through the second predictive model in step S320.”)
35 U.S.C. 103 – Samsung, Tenne, Soliman, Lenc
Claims 5,15,24 are rejected under 35 U.S.C. 103 as being unpatentable over Samsung in view of Tenne, in further view of Soliman in further view of Lenc.
In reference to claim 5.
Samsung teaches:
— “5. (Currently Amended) The apparatus of claim 1, wherein the one or more machine- learning models include a first machine-learning model and to generate the software configuration, the processor circuitry is to at least one of execute or instantiate the instructions to:” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
— “identify a second machine-learning model in the software configuration database;” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
Lenc teaches:
— “determine one or more first layers of the first machine-learning model to execute a first portion of the workload;” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
— “determine one or more second layers of the second machine-learning model to execute a second portion of the workload;” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
— “and determine the software topology based on an output from the one or more first layers as an input to the one or more second layers.” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
Motivation to combine Samsung Tenne, Soliman, and Lenc.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Samsung, Tenne, Soliman and Lenc. Samsung, Tenne, Soliman discloses a system and method for optimizing machine-learning model performance on arbitrary hardware. Lenc teaches a stitching technique for amalgamating distinct convolutional models. One would be motivated to combine these two references because the stitching methodology of Lenc provides an expanded database of models for the search space of Samsung and thus provides the potential for an additional performance gain. One of ordinary skill would have motivation to combine these references because MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art.
In reference to claim 15.
Samsung teaches:
— “15. (Currently Amended) The apparatus of claim 12, wherein the one or more machine- learning models include a first machine-learning model and to generate the software configuration, the first means for generating is to” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
— “identify a second machine-learning model in the software configuration database;” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
Lenc teaches:
— “determine one or more first layers of the first machine-learning model to execute a first portion of the workload;” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
— “determine one or more second layers of the second machine-learning model to execute a second portion of the workload;” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
— “and determine the software topology based on an output from the one or more first layers as an input to the one or more second layers.” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
In reference to claim 24.
Samsung teaches:
— “24. (Currently Amended) The at least one non-transitory computer readable storage medium of claim 20, wherein the one or more machine-learning models include a first machine-learning model and to generate the software configuration, the instructions, when executed, cause the processor circuitry to” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
— “identify a second machine-learning model in the software configuration database;” (Samsung [0090], “If it is identified that the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware reference (“No” in S330), the electronic device 100 may select one of the plurality of neural networks except for the first neural network in step S340. That the estimated value of the hardware performance corresponding to the first neural network does not satisfy the second hardware criteria may mean that it does not obtain a high reward value via the first neural network.”)
Lenc teaches:
— “determine one or more first layers of the first machine-learning model to cause an execution of a first portion of the workload;” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
— “determine one or more second layers of the second machine-learning model to cause an execution of a second portion of the workload;” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
— “and determine the software topology based on an output from the one or more first layers as an input to the one or more second layers.” (Lenc 991, “To answer this question we learn stitching layers that allow swapping parts of different networks.”)
35 U.S.C. 103 – Samsung, Tenne, Soliman, Oracle
Claims 6, 16, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Samsung in view of Tenne, in further view of Soliman, in further view of Oracle.
In reference to claim 6.
Samsung teaches:
— “6. (Currently Amended) The apparatus of claim 1, wherein the one or more machine-learning models include a first machine-learning model, wherein to generate the software configuration, [[and]] the processor circuitry is to at least one of execute or instantiate the instructions to” (Samsung FIG. 6 402, “CPU - Control unit and scheduler”)
Oracle teaches:
“identify the first machine-learning model in the software configuration database;” (Oracle [0375], “At 1902, the functionality can include identifying a first machine learning model.”)
— “identify a second machine-learning model based on a query of an ontology database with an identifier of the first machine-learning model as an input, the ontology database including an association of the first machine-learning model and the second machine-learning model;” (Oracle [0381], “At 1914, the functionality can include referring an ontology of the first data set to identify a second machine learning model based at least in part on comparing metadata of the second machine learning model with the metrics for the first machine learning model. The second machine learning model can be identified to test with the current machine learning model using a background process.”)
— “and in response to the evaluation parameter satisfying the threshold, update the ontology database based on the software configuration.” (Oracle [0388], “In various embodiments the techniques can include saving supplemental metadata concerning the second machine learning model based at least in part on the one or more first parameters the one or more second results.”)
Motivation to combine Samsung Tenne, Soliman, and Oracle.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Samsung, Tenne, Soliman and Oracle. Samsung, Tenne, Soliman discloses a system and method for optimizing machine-learning model performance on arbitrary hardware. Oracle discloses a system and method for adaptively composing machine learning models. One would be motivated to combine these two references because the ontological database of Oracle may serve as a cache for past performance by the system of Samsung and thus improves the performance of the hardware and model search. One of ordinary skill would have motivation to combine these references because MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art.
In reference to claim 16.
Samsung teaches:
— “16. (Currently Amended) The apparatus of claim 12, wherein the one or more machine-learning models include a first machine-learning model and to generate the software configuration, the first means for generating is to:” (Samsung FIG. 6 402, “CPU - Control unit and scheduler”)
Oracle teaches:
— “identify the first machine-learning model in the software configuration database;” (Oracle [0375], “At 1902, the functionality can include identifying a first machine learning model.”)
— “identify a second machine-learning model based on a query of an ontology database with an identifier of the first machine-learning model as an input, the ontology database including an association of the first machine-learning model and the second machine-learning model;” (Oracle [0381], “At 1914, the functionality can include referring an ontology of the first data set to identify a second machine learning model based at least in part on comparing metadata of the second machine learning model with the metrics for the first machine learning model. The second machine learning model can be identified to test with the current machine learning model using a background process.”)
— “and in response to the evaluation parameter satisfying the threshold, update the ontology database based on the software configuration.” (Oracle [0388], “In various embodiments the techniques can include saving supplemental metadata concerning the second machine learning model based at least in part on the one or more first parameters the one or more second results.”)
In reference to claim 25.
Samsung teaches:
— “25. (Currently Amended) The at least one non-transitory computer readable storage medium of claim 20, wherein the one or more machine-learning models include a first machine-learning model, wherein to generate the software configuration, [[and]] the instructions, when executed, cause the processor circuitry to:” (Samsung FIG. 6 402, “CPU - Control unit and scheduler”)
Oracle teaches:
— “discover the first machine-learning model in the software configuration database;” (Oracle [0375], “At 1902, the functionality can include identifying a first machine learning model.”)
— “discover a second machine-learning model based on a query of an ontology database with an identifier of the first machine-learning model as an input, the ontology database including an association of the first machine-learning model and the second machine-learning model;” (Oracle [0381], “At 1914, the functionality can include referring an ontology of the first data set to identify a second machine learning model based at least in part on comparing metadata of the second machine learning model with the metrics for the first machine learning model. The second machine learning model can be identified to test with the current machine learning model using a background process.”)
— “and in response to the evaluation parameter satisfying the threshold, update the ontology database based on the software configuration.” (Oracle [0388], “In various embodiments the techniques can include saving supplemental metadata concerning the second machine learning model based at least in part on the one or more first parameters the one or more second results.”)
35 U.S.C. 103 – Samsung, Tenne, Soliman, Li
Claims 8, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Samsung in view of Tenne, in further view of Soliman, in further view of Li.
In reference to claim 8.
Li teaches:
— “8. (Currently Amended) The apparatus of claim 1,” (preamble)
— “wherein to generate the hardware configuration, [[and]] the processor circuitry is to at least one of execute or instantiate the instructions to determine the hardware topology based on an output from the first portion of the execution hardware as an input to the second portion of the execution hardware.” (Li 129, “As shown in Fig. 5, the inputs of our system are the FPGA configuration (the number of LUTs, BRAMs, DSPs, FFs, etc.), total number of boards (M) and the CNN configuration (information of the n layers, see Table 1 as an example). The outputs of our system are the topology of the FPGA clusters, the partition of the input batches, and the resource allocation inside each sub-cluster”; Examiner notes that the system of Li outputs a topology of clusters, each cluster corresponding to a portion of hardware in terms of the claim language wherein the output of one cluster is fed in as the input of another.)
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Motivation to combine Samsung Tenne, Soliman, and Li.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine Samsung, Tenne, Soliman and Li. Samsung, Tenne, Soliman discloses a system and method for optimizing machine-learning model performance on arbitrary hardware. Li teaches improvements to convolutional models executed on FPGA clusters. One would be motivated to combine these two references because the optimal subcluster search of Li speaks to the hardware cluster optimization necessary in Samsung. One of ordinary skill would have motivation to combine these references because MPEP 2143 sets forth the Supreme Court rationales for obviousness including: (F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art.
In reference to claim 18.
Li teaches:
— “18. (Currently Amended) The apparatus of claim 12, wherein to generate the hardware configuration, [[and]] the second means for generating is to: determine the hardware topology based on an output from the first portion of the execution hardware as an input to the second portion of the execution hardware.” (Li 129, “As shown in Fig. 5, the inputs of our system are the FPGA configuration (the number of LUTs, BRAMs, DSPs, FFs, etc.), total number of boards (M) and the CNN configuration (information of the n layers, see Table 1 as an example). The outputs of our system are the topology of the FPGA clusters, the partition of the input batches, and the resource allocation inside each sub-cluster”; Examiner notes that the system of Li outputs a topology of clusters, each cluster corresponding to a portion of hardware in terms of the claim language wherein the output of one cluster is fed in as the input of another.)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CODY RYAN GILLESPIE/Examiner, Art Unit 2147
/VIKER A LAMARDO/Supervisory Patent Examiner, Art Unit 2147
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