CTFR 17/558,419 CTFR 82250 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Acknowledgment is made of applicant’s amendment, filed on 09 June 2025. The changes and remarks disclosed therein have been considered. Claims 1-5, 7, 9-15 and 22-28 are pending in the application. Claims 1-5, 7, 9-10, 12 and 15 are amended. Claims 22-28 are new. Claims 1, 10 and 22 are independent claims. Election/Restrictions 08-06 AIA Claim s 10-15 and 26-27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 October 2025 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 22-25 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2020/0083225) (hereinafter, “Ma”) in view of Derner et al. (US 2018/0061468) (hereinafter, “Derner”) . Re: independent claim 22, Ma discloses in figs. 1A-1F a memory device, comprising: a three-dimensional (3D) array of memory cells over a substrate (102), the substrate comprising a lateral surface, individual ones of the memory cells of the 3D array comprising: a transistor (150) comprising a channel structure (108) adjacent and orthogonal to a word line (116), the channel structure (108) and the word line (116) substantially parallel to the lateral surface; and at least a portion of a capacitor structure (170), the capacitor structure comprising a capacitor dielectric (142) between first and second metal plates (140, 144), wherein the channel structure (108) extends between and contacts a bit line (148) and the first metal plate (140), wherein the bit line (148) is substantially orthogonal to the lateral surface. Ma does not disclose wherein the capacitor dielectric includes a ferroelectric layer, wherein the ferroelectric layer comprises one of lead zirconium titanate or lead titanate. Derner discloses in fig. 5B a capacitor dielectric (118) including a ferroelectric layer, wherein the ferroelectric layer comprises one of lead zirconium titanate or lead titanate [0051]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a ferroelectric layer including lead zirconium titanate or lead titanate as the capacitor dielectric since ferroelectric memory cells have persistent storage of logic values without the need for periodic refresh operations (Derner, [0032]) and lead zirconium titanate or lead titanate are common and well known ferroelectric materials as exemplified by Derner [0051]. Re: claim 23, Ma in view of Derner discloses in figs. 1A-1F of Ma the memory device of claim 22, wherein a plurality of first memory cells each (150) accessed by the bit line (148) are stacked vertically (z-direction) over the lateral surface and the capacitor structure (170) comprises a plurality of regions extending laterally from a trunk structure of the capacitor structure (fig. 1A), each of the plurality of regions adjacent to a corresponding transistor (150) of individual ones of the plurality of first memory cells. Re: claim 24, Ma in view of Derner discloses in figs. 1A-1F of Ma the memory device of claim 23, wherein a plurality of second memory cells each accessed by a second bit line (148 in fig. 1E) are stacked vertically (z-direction) over the lateral surface and laterally adjacent the plurality of first memory cells (x-direction in fig. 1E), wherein the regions of the capacitor structure (170) are adjacent a corresponding transistor of individual ones of the plurality of second memory cells, and wherein the first and second bit lines are separated by dielectric material (134 in fig. 1E). Re: claim 25, Ma in view of Derner discloses in figs. 1A-1F of Ma the memory device of claim 23, wherein a plurality of second memory cells each accessed by a second bit line (148 in fig. 1A) are stacked vertically over the lateral surface and laterally opposite (y-direction in fig. 1A) the capacitor structure (170) from the plurality of first memory cells, wherein second regions of the capacitor structure extending from the trunk structure are adjacent a corresponding transistor of individual ones of the plurality of second memory cells, individual ones of the regions and second regions extending from the trunk structure substantially parallel to the lateral surface (fig. 1A). Re: claim 28, Ma in view of Derner discloses in figs. 1A-1F and 29 of Ma the memory device of claim 22, further comprising: a die comprising the 3D array of memory cells; and a power supply coupled to the die (fig. 29) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 1-5, 7 and 9 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 1, a memory device, comprising: a three-dimensional (3D) array of memory cells over a substrate, the substrate comprising a lateral surface, individual ones of the memory cells of the 3D array each comprising: a transistor comprising a channel structure adjacent and orthogonal to a corresponding word line, the channel structure and the word line substantially parallel to the lateral surface; and at least a portion of a capacitor structure, the capacitor structure comprising a ferroelectric layer between first and second metal plates, wherein the channel structure extends between and contacts a bit line and the first metal plate, wherein the bit line is substantially orthogonal to the lateral surface, wherein a plurality of first memory cells each accessed by a first bit line are stacked vertically over the lateral surface, each of the plurality of first memory cells comprising a first transistor and a laterally corresponding first capacitor structure, wherein vertically adjacent ones of the first capacitor structures are separated by dielectric material vertically between the vertically adjacent ones of the first capacitor structures, and wherein a plurality of second memory cells each accessed by a second bit line are stacked vertically over the lateral surface and laterally adjacent the plurality of first memory cells, individual ones of the second memory cells comprising a second transistor and the laterally adjacent one of the corresponding the first capacitor structures of the first memory cells . Response to Arguments 07-38 AIA Applicant’s arguments with respect to claim 22 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 05/15/2026 Application/Control Number: 17/558,419 Page 2 Art Unit: 2824 Application/Control Number: 17/558,419 Page 3 Art Unit: 2824 Application/Control Number: 17/558,419 Page 4 Art Unit: 2824 Application/Control Number: 17/558,419 Page 5 Art Unit: 2824 Application/Control Number: 17/558,419 Page 6 Art Unit: 2824 Application/Control Number: 17/558,419 Page 7 Art Unit: 2824
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