Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on August 4, 2025. These drawings are acceptable. Accordingly, previously stated objection(s) are withdrawn.
Response to Amendment
In response to the Non-Final Office action dated on May 2, 2025, Applicant submitted claim amendments, specification, along with remarks on August 4, 2025. Specifically, claims 1, 2, 5, and 14 are amended as well as claims 21-24 are newly added.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6 and 11-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action, including newly discovered prior art references US-20020196653-A1 and US-20120003808-A1. See below for details.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 13, 23, and 24 are rejected under 35 U.S.C. 103 as obvious over Chia, CN-113540099, in view of Kim, US 2002/0196653.
Regarding claim 1, Chia discloses an integrated circuit (IC) die (Fig. 15), comprising:
host circuitry comprising first transistors (Fig. 15/701 CMOS transistors, [0032] line 311 of the translated description provided); and
an embedded memory array structure (Fig. 15/101 and 801 memory cells and transistors shown in an array, [0069] line 812 and [0104] line 1250) coupled to the host circuitry (Fig. 15/101 are coupled to 701 through at least the 632), wherein the embedded memory array structure comprises:
a plurality of capacitors (Fig. 15/101 ferroelectric capacitor, [0102] line 1224), each of the capacitors comprising a first conductor (Fig. 15/130 first electrode, [0106] line 1271-1272), a ferroelectric material (Fig. 15/140 ferroelectric material which is between 130 and 160, [0106] line 1272) over, and in contact with the first conductor, and a second conductor (Fig. 15/160 second electrode, [0106] line 1272) over, and in contact with the ferroelectric material, two or more of the capacitors that are further coupled to either a same one of a plurality of wordlines or a same one of a plurality of bitlines (wordline, [0107] lines 1280-1281 field effect transistor 701 configured to control a gate of second transistor 801, which is a wordline connection);
a plurality of second transistors (Fig. 15/801, [0104] line 1250), wherein a first terminal of each of the second transistors is connected to the first conductor (Fig. 15/832 connects to 101, [0104] line 1255), a second terminal of the second transistors is coupled to one of a plurality of bitlines ({0109] lines 1301-1303 second transistor 801 connected to sensing field effect transistor 701 which is a bitline connection) and a third terminal of the second transistors is coupled to one of a plurality of wordlines ([0107] lines 1280-1281 field effect transistor 701 configured to control a gate of second transistor 801, which is a wordline connection); and
a plurality of plate line straps (Fig. 15/190 metal interconnect structure, [0104] lines 1248-1249), each of the plate line straps extending in parallel to and coupled to a corresponding one of the second conductors of the capacitors (Fig. 15/190 are connected to 160 by the 180) that are coupled to the same one of the wordlines or the same one of the bitlines (Fig. 15/190 are coupled to the 160 and also to the 280/632 — which can be either a wordline or a bitline — and thus down to the source/drain of 701).
Claim 1 also recites that the second conductor extends between two or more of the capacitors, and that each of the plate line straps extending parallel with, and coupled to, a corresponding one of the second conductors of individual ones of the capacitors. The top electrodes of the group of capacitors connected by line 190 are all electrically connected, and thus at the same voltage, but in Chia the top electrodes are not a single electrode extending across multiple capacitors. However, this structure was known in the art. See Kim, FIG. 6, top electrode 190 (second conductor) extending across multiple capacitors and with a plate strap 113 above it, extending parallel with, and coupled to the second conductor. This was a known arrangement in the art, and would have been obvious with advantages such as reducing the resistance by eliminating interconnects 180.
Regarding claim 2, CHIA discloses the IC die of claim 1, further comprising one or more first levels of metallization over the first transistors (Fig. 15/612+618+622+628, [0114] lines 1347- 1348), and wherein:
the memory array structure is over the first levels of metallization (Fig. 15/801, 101 are over the 612+618+622+628);
the plurality of second transistors is between the capacitors and the first levels of metallization (Fig. 15/801 are between the capacitors 101 and the 612+6184+622+628); and
the plurality of plate lines straps (Fig. 15/190) are within a second level of metallization over the memory array structure (Fig. 15/190 are within a second level over the 101), and comprise co-planar metal lines (Fig. 15/190 are co-planar with one another) having a first pitch approximately equal to a first pitch of the capacitors (Fig. 15/180 which provide a pitch to the 190 equal to the pitch of the 101), and wherein individual ones of the co-planar metal lines are coupled to the corresponding second conductor of the capacitors (Fig.15/190 couple to 101 by the 180) that are coupled to either the same one of the wordlines or the same one of the bitlines (Fig. 15/190 are coupled to the 160 and also to the 280/632 — which can be either a wordline or a bitline — and thus down to the source/drain of 701).
Regarding claim 3, Chia discloses the IC die of claim 2, wherein individual ones of the co-planar metal lines (Fig. 15/190) are coupled to the second conductor through a plurality of intervening conductive vias having a second pitch (Fig. 10/180 repeated N times along the second horizontal hd2, one for each 101 and 801, [0087] lines 1013-1017; and having a second pitch along hd2, [0051], line 575) in a direction orthogonal (array is rectangular, [0051] line 574) to the first pitch (Fig. 15/180 repeated M times along the first horizontal direction, [0087] lines 1015-1016; and having a first spacing along hd1, [0051] lines 574-574).
In case applicant disagrees that the prior art discloses the plurality of vias repeated N times and having the second pitch, which the examiner does not concede, there is a motivation to access each memory cell with the field effect transistors 701 ([0087] lines 1017-1018), and it would be obvious to repeat the 190 and 180 in each of the N rows to accomplish this. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the intervening vias of Fig. 10 of CHIA into the two- dimensional array of the embodiment in [0087] to access a plurality of capacitors on one horizontal level.
Regarding claim 4, Chia discloses the IC die of claim 3, wherein the second pitch of the vias is approximately equal to a second pitch of the capacitors (Fig. 10/180 repeated N times along the second horizontal hd2, one for each capacitor 101 and second transistor 801, [0087] lines 1013- 1017; and having a second pitch along hd2, [0051], line 575).
Regarding claim 5, Chia discloses the IC die of claim 3, wherein the second conductor has a first composition (Fig. 8/160L second electrode material layer, [0066] line 765 which can have a composition of Al, [0066] line 769-770), and the co-planar metal lines and plurality of conductive vias have a second composition, different than the first composition (Fig. 15/190 is formed in an interconnect cavity over 170 and can comprise copper, [0075] line 874-875).
Regarding claim 6, Chia discloses the IC die of claim 5, wherein the co-planar metal lines and plurality of conductive vias comprise primarily Cu (190 comprises Cu except for a barrier layer and thus is primarily Cu, [0075] lines 874-875, and the via cavity is integral with the line cavity for 190, [0074] lines 857-860, and thus has the same Cu fill).
Regarding claim 13, Chia discloses the IC die of claim 1, wherein a channel material of the second transistors comprises predominantly one or more metals and oxygen (Fig. 4/semiconductive channel is a metal oxide, [0010] lines 105-106).
Regarding claims 23 and 24, Chia Fig. 15 shows that lines 190 are coupled to the 160 and also to the 280/632 — which can be either a wordline or a bitline — and thus down to the source/drain of 701). For Chia in view of Kim, the second conductor extends between two or more of the capacitors (Kim FIG. 6) that are further coupled to a same one the plurality of bitlines/wordlines; and each of the plate line straps extends parallel with, and is coupled to, the corresponding second conductor of the capacitors that are coupled to the same one the bitlines/wordlines (Kim FIG. 6, Chia FIG. 15).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over CHIA, in view of “Ab initio study of high permittivity phase stabilization in HfSiO” by Fischer.
Regarding claim 11. Chia discloses The IC die of claim 1.
Chia does not disclose wherein the ferroelectric material has a relative permittivity over 25.
Fischer teaches wherein the ferroelectric material has a relative permittivity over 25 (material with a dielectric constant of 26; page 2041, col. 1, lines 27-30).
There is a motivation to replace conventional oxides with higher permittivity materials as size scaling of devices decreases (page 2039, col. 1, lines 1-4). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the high permittivity material of Fischer into the memory device of Chia to improve memory performance.
Regarding Claim 12. Chia in view of Fischer discloses the IC die of claim 11.
Chia does not disclose wherein the ferroelectric material comprises predominantly Hf, O, and one or impurity dopants that comprise at least one of Si or Ge.
Fischer further teaches wherein the ferroelectric material comprises predominantly Hf, O, and one or impurity dopants that comprise at least one of Si or Ge. (AfSiO with 10% minority Si component; page 2041, col. 1, lines 27-30).
There is a motivation to use dielectrics based on HfSiO due to its advantageous properties (page 2039, col. 1, line 10 —col. 2, line 2). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the HfSiO material of FISCHER into the memory device of CHIA to improve memory performance.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over CHIA, in view of Kim and Derner, US 10,872,650.
Regarding claim 14. Chia discloses a system comprising:
an integrated circuit (IC) die (Fig. 15), comprising:
a plurality of first transistors (Fig. 15/701 CMOS transistors, [0032] line 311) with monocrystalline channel material ({0027] line 233);
one or more first levels of metallization over the first transistors (Fig. 15/612, 618, 622, 628 — [0037] line 371);
a memory array structure over the first levels of metallization (Fig. 15/101 and 801 memory cells and transistors shown in an array, [0069] line 812 and [0104] line 1250), wherein the memory array structure comprises:
a plurality of capacitors (Fig. 15/101 ferroelectric capacitor, [0102] line 1224), each comprising a first conductor (Fig. 15/130 first electrode, [0106] line 1271-1272) and with a ferroelectric material (Fig. 15/140 ferroelectric material which is between 130 and 160, [0106] line 1272) over, and in contact with, the first conductor, and a second conductor (Fig. 15/160 second electrode, [0106] line 1272) over, and in contact with, the ferroelectric material, the second conductor coupled to either a same one of a plurality of wordlines or a same one of a plurality of bitlines (wordline, [0107] lines 1280-1281 field effect transistor 701 configured to control a gate of second transistor 801, which is a wordline connection);
a plurality of second transistors (Fig. 15/801, [0104] line 1250) between the capacitors and the first levels of metallization (the 801 are between the 101 and the 628), wherein a first terminal of the second transistors is connected to the first conductor (Fig. 15/832 connects to 101, [0104] line 1255); and
one or more second levels of metallization over the memory array structure (Fig. 15/180, 190, 280, 290; [0076] lines 887-888), wherein the second levels of metallization comprise co- planar metal lines (Fig. 15/190, which are co-planar) having a first pitch approximately equal to a first pitch of the capacitors (Fig. 15/180 which provide a pitch to the 190 equal to the pitch of the 101), and wherein an individual one of the co-planar metal lines extends parallel with, and is coupled to a corresponding second conductor of the two or more capacitors that are coupled to the same one of the wordlines or the same one of the bitlines (Fig. 15/190 couple to 101 by the 180).
Claim 14 also recites that the second conductor extends between two or more of the capacitors, and that each of the plate line straps extending parallel with, and coupled to, a corresponding one of the second conductors of individual ones of the capacitors. The top electrodes of the group of capacitors connected by line 190 are all electrically connected, and thus at the same voltage, but in Chia the top electrodes are not a single electrode extending across multiple capacitors. However, this structure was known in the art. See Kim, FIG. 6, top electrode 190 (second conductor) extending across multiple capacitors and with a plate strap 113 above it, extending parallel with, and coupled to the second conductor. This was a known arrangement in the art, and would have been obvious with advantages such as reducing the resistance by eliminating interconnects 180.
Chia does not disclose a power supply coupled to the IC to power to the IC.
Derner teaches a power supply coupled to the IC to power the IC (Fig. 1/40 voltage controller, col. 5, lines 9-11).
There is motivation to power the memory, as it is non-functional without this. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the voltage supply of DERNER into the memory device of CHIA to make the system functional.
Regarding claim 15. Chia in view of Derner discloses the system of claim 14.
Chia does not disclose that the IC die includes at least one of microprocessor core circuitry or floating-point gate array (FPGA) circuitry.
Derner further teaches wherein:
the IC die includes at least one of microprocessor core circuitry or floating point gate array (FPGA) circuitry (Fig. 15/40 memory controller may be integrated into processor 1510 and include an FPGA, col. 34, lines 57-62).
There is a motivation to have logic circuitry to operate the memory array (col. 34, lines 65-66). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to incorporate the FPGA of DERNER into the memory system of CHIA to operate the memory.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as obvious over Chia in view of Kim and Lee, US 2012/0003808.
Regarding claim 21: Chia does not disclose the capacitor structure recited in claim 21. However, this is common in the art. See e.g. Sharma, FIG. 4j, which discloses that:
the first conductor (92) is cylindrical ([0085]);
the ferroelectric material (93, [0057]) is lining an interior sidewall of the first conductor;
the second conductor (94) is adjacent to an interior sidewall of the ferroelectric material.
It would have been obvious to have used this structure as a known capacitor structure for ferroelectric memory devices.
Regarding claim 22: Chia discloses that the second transistor (801) is between the first transistor (701) and one or more of the capacitors (101).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB Y CHOI whose telephone number is (469)295-9060. The examiner can normally be reached Mondays - Thursdays from 5:30 a.m. to 3:30 p.m. CT.
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/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897