Detailed Action
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-21 are presented for examination.
Claims 3,5,10 and 14-15 are presented for examination.
Claims 1-2,4,6-9,11,13,16-21 are previously presented .
Claims 1-11 and 13-21 are rejected.
This Action is Non-Final.
Response to Arguments
Applicant's arguments filed 02/12/2026 have been fully considered but they are not persuasive.
Applicant’s representative on Pages 7-8 of the remarks argues that , “As explained below, the Office has failed to show that Du and Thyamagondlu, individually and in combination, disclose or render obvious at least the features of dynamically assigning, via software management and based at least in part on runtime system resource availability, a device different from the first processor device to assist in transfer of at least a first portion of the data transfer, as set forth in claim 1.”.
Applicant’s representative further argues that, “Du and Thyamagondlu, individually and in combination, disclose or render obvious at least the features of dynamically assigning, via software management and based at least in part on runtime system resource availability, a device different from the first processor device to assist in transfer of at least a first portion of the data transfer, as set forth in claim 1.”.
In response to applicant's argument that “The combination of Roberts and Dasari thus fails to present a prima facie case of obviousness against claim 1.”, the examiner recognizes that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992).
In this case, Du and Thyamagondlu are analogous art because they are from the same field of endeavor an apparatus for performing graphics processing; and a method of performing direct memory accesses in a multi-host system. At the time of invention, it would have been obvious to one of ordinary skill in the art, having the teaching of Du and Thyamagondlu before him or her, to modify the teaching of Du by adding performing direct memory accesses in a multi-host system of Thyamagondlu. The motivation for doing so would ensure that the data engines are independently configurable to access different ones of the interfaces for different flows of a DMA operation based on the host profiles, so that the performance of the computing system can be improved.
Therefore it would have been obvious to combine Du and Thyamagondlu to obtain the invention as specified in the instant the claims.
With regards to “Du and Thyamagondlu, individually and in combination, disclose or render obvious at least the features of dynamically assigning, via software management and based at least in part on runtime system resource availability, a device different from the first processor device to assist in transfer of at least a first portion of the data transfer, as set forth in claim 1.”.
Examiner respectfully disagree with the argument. Du and Thyamagondlu teach,disclose or suggest “dynamically assigning, via software management and based at least in part on runtime system resource availability, a device different from the first processor device to assist in transfer of at least a first portion of the data transfer, as set forth in claim 1.”.Du teaches dynamically assigning resources during runtime [Du, Paragraphs 0004;0016;0030; 0078, By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application.].Du discloses resources requested at runtime by a processor and a subset of data dynamically determined during runtime [Du, Paragraphs 0078-0079, Referring again to FIG. 4, as applications evolved, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application.]. Thyamagondlu discloses performing a data transfer in host system and selecting using a descriptor engine DMA system [Thyamagondlu, col.1,ll.43-54, …, a method of performing a data transfer in a multi-host system includes selecting, using a descriptor engine of a DMA system, a first host profile from a plurality of host profiles stored in a memory based on a received doorbell message.].
Therefore it would have been obvious to combine Du and Thyamagondlu to obtain the invention as specified in the instant the claims.
9. Applicant’s representative on Page 8 of the remark, “They do not disclose a DMA transfer command that instructs a processor device to perform a direct memory access data transfer independent of processor execution.”.
Examiner respectfully disagree with the argument. Du and Thyamagondlu teach, disclose or suggest “a DMA transfer command that instructs a processor device to perform a direct memory access data transfer independent of processor execution.”. Du teaches dynamically assigning resources during runtime [Du, Paragraphs 0049;0065;0082,The command processor 310 may be configured to receive a command stream representing operations for the graphics processor 300 to perform.]. Thyamagondlu discloses a DMA supporting different processors and assigning flows of DMA operations to different processors [Thyamagondlu, col.2, ll.47-57,…, a DMA system is provided that supports the use of two or more different host processors. The DMA system supports the assignment of different flows of DMA operations to different host processors in the multi-host system. These different flows may be controlled by hardware while retaining the flexibility of software programmability.].
Therefore it would have been obvious to combine Du and Thyamagondlu to obtain the invention as specified in the instant the claims.
10. Applicant’s representative on Pages 8-9 of the remark argues that, “The Applicant respectfully submits that the Office has not established that these disclosures disclose or suggest the dynamic assignment, via software management, based on runtime system resource availability, of a device different from the first processor device to assist in transfer of at least a first portion of the data transfer, as required by claim 1.”
The argument submitted above is substantially the same as the argument
submitted previously. Therefore, the response provided with respect to the preceding
argument, is applicable with respect the above argument as well.
11. Applicant’s representative on Pages 9-10 of the remark argues that, “Even assuming arguendo that Thyamagondlu discloses DMA transfers involving multiple hosts, the Office has not established that the combination of Du and Thyamagondlu would result in the claimed method. Du operates in the context of graphics workload management and shader execution, while Thyamagondlu operates in the context of DMA descriptor processing in a multi-host system. The Office has not articulated a sufficient rationale explaining why a person of ordinary skill in the art would modify Du's graphics resource assignment mechanisms to dynamically assign processor devices to assist in DMA transfers as described in Thyamagondlu. The asserted motivation that performance "can be improved" is conclusory and does not explain how or why the specific combination would yield the claimed dynamic device assignment based on runtime system resource availability.
The argument submitted above is substantially the same as the argument submitted previously. Therefore, the response provided with respect to the preceding argument, is applicable with respect the above argument as well.
12. Applicant’s representative on Pages 11-12 of the remark argues that, “Moreover , claim 16 requires that the dynamic assignment occurs during execution of a DMA transfer operation. This temporal feature excludes pre-dispatch configuration, static setup, or assignment decisions made before a DMA operation begins. Instead, claim 16 requires that the host processor monitor runtime system resource availability and dynamically assign a different processor device while the DMA transfer operation is already executing. The Office has not identified any disclosure in Du or Thyamagondlu demonstrating this execution-time reassignment behavior.”
The argument submitted above is substantially the same as the argument submitted previously. Therefore, the response provided with respect to the preceding argument, is applicable with respect the above argument as well.
13. Applicant’s representative on Pages 12-13 of the remark argues that, “Accordingly, claim 16 does not stand or fall with claim 1. Even assuming arguendo that the Office had established a prima facie case with respect to claim 1, which the Applicant does not concede, the Office has failed to independently establish a prima facie case of obviousness for claim 16. The Office has failed to show that the cited references disclose or suggest a host processor that dynamically assigns, during execution of a DMA transfer operation and based on runtime system resource availability, a device different from the first processor device to assist in the DMA transfer. For at least these reasons, claim 16 is novel and non-obvious over the cited art. ”.
In response to applicant's argument that ,“Accordingly, claim 16 does not stand or fall with claim 1. Even assuming arguendo that the Office had established a prima facie case with respect to claim 1, which the Applicant does not concede, the Office has failed to independently establish a prima facie case of obviousness for claim 16. The Office has failed to show that the cited references disclose or suggest a host processor that dynamically assigns, during execution of a DMA transfer operation and based on runtime system resource availability, a device different from the first processor device to assist in the DMA transfer. For at least these reasons, claim 16 is novel and non-obvious over the cited art. ”, the examiner recognizes that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992).
In this case, Du and Thyamagondlu are analogous art because they are from the same field of endeavor an apparatus for performing graphics processing; and a method of performing direct memory accesses in a multi-host system. At the time of invention, it would have been obvious to one of ordinary skill in the art, having the teaching of Du and Thyamagondlu before him or her, to modify the teaching of Du by adding performing direct memory accesses in a multi-host system of Thyamagondlu. The motivation for doing so would ensure that the data engines are independently configurable to access different ones of the interfaces for different flows of a DMA operation based on the host profiles, so that the performance of the computing system can be improved.
Therefore it would have been obvious to combine Du and Thyamagondlu to obtain the invention as specified in the instant the claims.
14. Applicant’s representative on Page 13 of the remark argues that, “Du does not disclose instructing a DMA engine to perform a read-copy-write operation, does not disclose reading a copy of data corresponding to a DMA transfer command, and does not disclose writing that copy into a local memory of another processor device. Du's dynamic assignment is limited to software-level graphics resource binding, not hardware-level DMA engine control.”.
Examiner respectfully disagree with the argument. Du and Thyamagondlu teach, disclose or suggest “instructing a DMA engine to perform a read-copy-write operation, does not disclose reading a copy of data corresponding to a DMA transfer command, and does not disclose writing that copy into a local memory of another processor device. Du's dynamic assignment is limited to software-level graphics resource binding, not hardware-level DMA engine control.”. Du teaches dynamically assigning resources during runtime [Du, Paragraph 0078,…, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application. For example, bindless resources may be requested at runtime by the graphics processor 430 and are not assigned (or bound) to the processing of a particular object, as described above with respect to the binding mechanism.]. Thyamagondlu discloses a DMA read and write operations from selected memory [Thyamagondlu, col.8,ll.16-27, Hardware such as DMA system 204 (e.g., a descriptor engine therein) reads from these queues. The H2C queues include descriptors for DMA read operations from a selected host processor memory. The C2H queues carry descriptors for DMA write operations to a selected host processor memory.].
Therefore it would have been obvious to combine Du and Thyamagondlu to obtain the invention as specified in the instant the claims.
15. Applicant’s representative on Pages 14-15 of the remark argues that, “Accordingly, the rejection of claim 4 relies on an improper conflation of generic "dynamic resource assignment" with the specific DMA-engine-level operations recited in the claim. The Office has not established that the cited references disclose or suggest the claimed method, nor has it provided a reasoned explanation, supported by the references, for combining them in the manner proposed. For at least these reasons, claim 4 is novel and non-obvious over Du and Minkin.”.
The argument submitted above is substantially the same as the argument submitted previously. Therefore, the response provided with respect to the preceding argument, is applicable with respect the above argument as well.
16. Applicant’s representative on Pages 16-17 of the remark argues that, “As explained below, the Office has failed to show Chung and Du, individually and in combination, disclose or render obvious at least the feature of a plurality of DMA engines that are dynamically assigned via software management and based at least in part on runtime system resource availability to perform at least portions of a DMA transfer command, as set forth in claim 8.”.
In response to applicant's argument that “Accordingly, claim 16 does not stand or fall with claim 1. Even assuming arguendo that the Office had established a prima facie case with respect to claim 1, which the Applicant does not concede, the Office has failed to independently establish a prima facie case of obviousness for claim 16. The Office has failed to show that the cited references disclose or suggest a host processor that dynamically assigns, during execution of a DMA transfer operation and based on runtime system resource availability, a device different from the first processor device to assist in the DMA transfer. For at least these reasons, claim 16 is novel and non-obvious over the cited art.”, the examiner recognizes that obviousness can only be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988) and In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992).
In this case, Chung and Du are analogous art because they are from the same field of endeavor a Stacked processor device and an apparatus for performing graphics processing. At the time of invention, it would have been obvious to one of ordinary skill in the art, having the teaching of Chuang and Du before him or her, to modify the teaching of Chuang by adding
a method involves receiving, at a graphics processor, a shader program including a preamble section and a main instruction section of Du. The motivation for doing so would ensure that the memory is provided with adjustable memory portion and adjustable cache portion such that memory is allowed to operate simultaneously in both memory and cache modes, also the process for operating dynamic RAM can be achieved and a method enables reducing the power consumption of the graphics processing unit (GPU), thus reducing the cost of the GPU; and also allows the GPU to be operated in a power-efficient manner, thus improving the performance of GPUs, and hence improving the graphics performance of the apparatus; and reduces the power consumed by the GPU, thus reducing power consumption and improving the power efficiency of the GPUs.
Therefore it would have been obvious to combine Chung and Du to obtain the invention as specified in the instant the claims.
17. Applicant’s representative on Pages 18-19 of the remark argues that, “Accordingly, Du fails to disclose the dynamic DMA engine assignment required by claim 8.”.
The argument submitted above is substantially the same as the argument submitted previously. Therefore, the response provided with respect to the preceding argument, is applicable with respect the above argument as well.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
18. Claims 1-2 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over DU et al.(US Patent Application Pub. No: 20230019763 A1) in view of Thyamagondlu et al. (US Patent No;11,232,053 B1).
As per claim 1,DU teaches a method, comprising:
receiving, transfer command instructing a data transfer by a first processor device [Paragraphs 0049;0065;0082,The command processor 310 may be configured to receive a command stream representing operations for the graphics processor 300 to perform.]; and
dynamically assigning, via software management, based at least in part on runtime system resource availability [Paragraphs 0004;0016;0030; 0078, By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application.].
DU does not explicitly disclose a direct memory access (DMA) transfer command;
a device different from the first processor device to assist in transfer of at least a first portion of the data transfer.
Thyamagondlu disclose a direct memory access (DMA) transfer command [col.3,ll.32-40,…the DMA system facilitates shared resource utilization among the multiple host processors….];
a device different from the first processor device to assist in transfer of at least a first portion of the data transfer [Fig.2A; col.1,ll. 43-50; col.7,ll.32-41,…, performing a data transfer in a multi-host system includes selecting, using a descriptor engine of a DMA system, a first host profile from a plurality of host profiles stored in a memory based on a received doorbell message.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Thyamagondlu 's system for performing direct memory accesses in a multi-host system into DU’s an apparatus for performing graphics processing for the benefit of the data engines are independently configurable to access different ones of the interfaces for different flows of a DMA operation based on the host profiles, so that the performance of the computing system can be improved (Thyamagondul,col.1,ll.43-54) to obtain the invention as specified in claim 1.
As per claim 2, DU and Thyamagondul teach all the limitations of claim 1 above, where DU teaches, a method, wherein dynamically assigning the device different from the first processor device further comprises:
initiating, based at least in part on the runtime system resource availability, transfer of a second portion of the data transfer by a second processor device [Du, Paragraph 0078,…, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application. For example, bindless resources may be requested at runtime by the graphics processor 430 and are not assigned (or bound) to the processing of a particular object, as described above with respect to the binding mechanism.].
As per claim 21, DU and Thyamagondul teach all the limitations of claim 1 above, where DU and Thyamagondul teach, a method, wherein dynamically assigning the device different from the first processor device further comprises:
initiating, based at least in part on the runtime system resource availability, transfer of a second portion of the data transfer by instructing a DMA engine at another processor device to read a copy of data corresponding to the DMA transfer command and write the copy of data to a local memory of a processor device different from the first processor device [Du, Paragraph 0078,…, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application. For example, bindless resources may be requested at runtime by the graphics processor 430 and are not assigned (or bound) to the processing of a particular object, as described above with respect to the binding mechanism.].
19. Claims 3-7 are rejected DU et al.(US Patent Application Pub. No: 20230019763 A1) in view of Thyamagondlu et al. (US Patent No;11,232,053 B1) ,and further in view of Minkin et al. (US Patent No: 11,175,919 B1).
As per claim 3, DU and Minkin teach all the limitations of claim 2 above, where DU teaches, a method, further comprising: initiating transfer [Du, Paragraph 0078,…, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application. For example, bindless resources may be requested at runtime by the graphics processor 430 and are not assigned (or bound) to the processing of a particular object, as described above with respect to the binding mechanism.].
However, Du does not explicitly disclose initiating a first DMA engine at the first processor device to transfer a copy of data corresponding to the DMA transfer command to a second DMA engine at the second processor device; and
initiating the second DMA engine to transfer the copy of data to a local memory of the second processor device.
Minkin discloses initiating a first DMA engine at the first processor device to transfer a copy of data corresponding to the DMA transfer command to a second DMA engine at the second processor device [col.14,ll.33-43, The first execution engine 610 may execute an instruction, for example, copying weights to a state buffer. When the instruction is complete, the first execution engine 610 may execute an instruction to set a value (i.e., a checkpoint) in a local checkpoint register associated with the second execution engine 620.]; and
initiating the second DMA engine to transfer the copy of data to a local memory of the second processor device [col.6, ll.20-32,…,the edge 122 from the second computation operation (node 120 in the first execution engine 210 to the data transfer operation at node 150 in the first execution engine 210 may not have an assigned checkpoint value because both operations are executed on the same engine (i.e., the first execution engine 210).].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include Minkin 's an integrated circuit device such as neural network processor into DU’s an apparatus for performing graphics processing for the benefit of enables reducing the size of the memory of the integrated circuit device by reducing the number of times that the data is retrieved from the memory during execution of the execution engine, thus reducing the amount of time required to retrieve the data and allows the data to be written to the memory in an efficient manner, thus improving the performance of the device (Minkin,col.2,ll.9-20) to obtain the invention as specified in claim 1.
As per claim 4, DU and Minkin teach all the limitations of claim 2 above, where DU and Minkin teach, a method, wherein dynamically assigning the device different from the first processor device [Du, Paragraph 0078,…, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application. For example, bindless resources may be requested at runtime by the graphics processor 430 and are not assigned (or bound) to the processing of a particular object, as described above with respect to the binding mechanism.], further comprises:
initiating a first DMA engine at a third processor device to read a copy of data, corresponding to the DMA transfer command, from a second DMA engine and write the copy of data to a local memory of a second processor device [Minkin, col.14,ll.33-43, The first execution engine 610 may execute an instruction, for example, copying weights to a state buffer. When the instruction is complete, the first execution engine 610 may execute an instruction to set a value (i.e., a checkpoint) in a local checkpoint register associated with the second execution engine 620.].
As per claim 5, DU and Minkin teach all the limitations of claim 1 above, where Minkin teaches, a method, wherein the DMA transfer command instructs the first processor device to write a copy of data to a second processor device [Minkin, col.14,ll.33-43, The first execution engine 610 may execute an instruction, for example, copying weights to a state buffer. When the instruction is complete, the first execution engine 610 may execute an instruction to set a value (i.e., a checkpoint) in a local checkpoint register associated with the second execution engine 620.].
As per claim 6, DU and Minkin teach all the limitations of claim 5 above, where DU and Minkin teach, a method, further comprising:
initiating transfer of the copy of data from the first processor device to the second processor device [Du, Paragraph 0078,…, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application. For example, bindless resources may be requested at runtime by the graphics processor 430 and are not assigned (or bound) to the processing of a particular object, as described above with respect to the binding mechanism.], via a first direct inter-chip data fabric between the first processor device and the second processor device [Minkin, col.21,ll.31-37, …accelerator 900, the various components can communicate over a chip interconnect 920. The chip interconnect 920 primarily includes wiring for routing data between the components of the accelerator 900.]; and
initiating transfer of the copy of data from the second processor device to a third processor device via a second direct inter-chip data fabric between the second processor device and the third processor device [Minkin, col.14,ll.33-43, The first execution engine 610 may execute an instruction, for example, copying weights to a state buffer. When the instruction is complete, the first execution engine 610 may execute an instruction to set a value (i.e., a checkpoint) in a local checkpoint register associated with the second execution engine 620.].
As per claim 7, DU and Minkin teach all the limitations of claim 5 above, where DU and Minkin teach, a method, further comprising: further comprising:
splitting of the DMA transfer command into a plurality of smaller workloads [Du, Paragraph 0078,…, control of the resources for processing a workload shifted from the graphics driver 416 to the application 412. By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application. For example, bindless resources may be requested at runtime by the graphics processor 430 and are not assigned (or bound) to the processing of a particular object, as described above with respect to the binding mechanism.]; and
initiating transfer of at least a first portion of the data transfer corresponding to one of the plurality of smaller workloads via a multi-hop communications path between the first processor device and a third processor device [Minkin, col.21,ll.31-37,…accelerator 900, the various components can communicate over a chip interconnect 920. The chip interconnect 920 primarily includes wiring for routing data between the components of the accelerator 900.].
20. Claims 8-11 and 13-15 are rejected Chung et al.(US Patent Application Pub. No: 20120221785 A1) in view of DU et al.(US Patent Application Pub. No: 20230019763 A1).
As per claim 8,Chung teaches a processor device [Fig.1, a 3D stacked processor device.], comprising:
a first base integrated circuit (IC) die including a plurality of processing stacked die chiplets 3D stacked on top of the first base IC die, wherein the first base IC die includes an inter-chip data fabric communicably coupling the plurality of processing stacked die chiplets together [Paragraphs 0007;0015;claim 2,…,a stacked processor device and fabrication methodology are provided for forming a plurality of chips into a multi-chip stack which includes a polymorphic stacked memory. …, the stacked processor device includes a processor chip as a first layer, where the processor chip may be formed as a central-processing-unit (CPU), a graphics-processing-unit (GPU), a baseband, a digital-signal-processing (DSP), a wireless local area network (WLAN), a multi-core CPU, a multi-core graphical processing unit GPU, or a hybrid CPU/GPU system.]; and
a plurality of direct memory access (DMA) engines 3D stacked on top of the first base IC die, wherein the plurality of DMA engines are each configured to perform at least a portion of a DMA transfer command [Paragraphs 0031-0032, At step 416, any required off-chip data read/write operations are performed using the direct memory access (DMA) engine which enables data movement between the on-chip stacked DRAM memory and off-chip memory. While the basic requirements remain the same as a conventional off-chip memory-to-disk DMA engine, the DMA engine is configured to be flexible in terms of adapting to the requirements of servicing the cache or the memory regions. The need arises from the difference in the data transfer granularities for the cache and memory portion, 512B for caches and 4 KB for memory. The coherency requirements differ as well, evicting an entry from cache requiring flushing data from caches higher up in the hierarchy. For memory though, page replacement leads to a TLB shootdown.].
Chung does not explicitly disclose dynamically assigned via software management and based at least in part on runtime system resource availability.
Du discloses dynamically assigned via software management and based at least in part on runtime system resource availability [Paragraphs 0004;0016;0030; 0078, By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include DU’s an apparatus for performing graphics processing in to Chung’s Stacked processor device for the benefit of enables reducing the power consumption of the graphics processing unit (GPU), thus reducing the cost of the GPU; and allows the GPU to be operated in a power-efficient manner, thus improving the performance of GPUs, and hence improving the graphics performance of the apparatus; and also reduces the power consumed by the GPU, thus reducing power consumption and improving the power efficiency of the GPUs (DU,[0109]) to obtain the invention as specified in claim 8.
As per claim 9, Chung and DU teach all the limitations of claim 8 above, where Chung and DU teach, a processor device, further comprising: a first DMA engine at the first base IC die configured to transfer, based on instructions during software runtime [DU, Paragraphs 0004;0016;0030; 0078, By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application.], a copy of data corresponding to the DMA transfer command to a second DMA engine at a second base IC die [Chung, Paragraphs 0031-0032, At step 416, any required off-chip data read/write operations are performed using the direct memory access (DMA) engine which enables data movement between the on-chip stacked DRAM memory and off-chip memory. While the basic requirements remain the same as a conventional off-chip memory-to-disk DMA engine, the DMA engine is configured to be flexible in terms of adapting to the requirements of servicing the cache or the memory regions.].
As per claim 10, Chung and DU teach all the limitations of claim 9 above, where Chung and DU teach, a processor device, wherein the second DMA engine is further configured to transfer, based on instructions during software runtime [DU, Paragraphs 0004;0016;0030; 0078, By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application.], the copy of data to a local memory of the second base IC die [Chung, Paragraphs 0031-0032, At step 416, any required off-chip data read/write operations are performed using the direct memory access (DMA) engine which enables data movement between the on-chip stacked DRAM memory and off-chip memory. While the basic requirements remain the same as a conventional off-chip memory-to-disk DMA engine, the DMA engine is configured to be flexible in terms of adapting to the requirements of servicing the cache or the memory regions.].
As per claim 11, Chung and DU teach all the limitations of claim 9 above, where Chung and DU teach, a processor device, further comprising: a third DMA engine at a third base IC die configured to transfer, based on instructions during software runtime [DU, Paragraphs 0004;0016;0030; 0078, By enabling the application 412 to handle resource control, resources may be dynamically assigned during runtime of the application.], a copy of data corresponding to the DMA transfer command from the first base IC die to a local memory of a second base IC die [Chung, Paragraphs 0031-0032, At step 416, any required off-chip data read/write operations are performed using the direct memory access (DMA) engine which enables data movement between the on-chip stacked DRAM memory and off-chip memory. While the basic requirements remain the same as a conventional off-chip memory-to-disk DMA engine, the DMA engine is configured to be flexible in terms of adapting to the requirements of servicing the cache or the memory regions.].
As per claim 13, Chung and DU teach all the limitations of claim 11 above, where Chung and DU teach, a processor device, further comprising:
a first direct inter-chip data fabric communicably coupling the first base IC die to the second base IC die [DU, Paragraph 0033, Memory external to the processing unit 120, such as memory 124, may be accessible to the processing unit 120, the display client 131, and/or the communication interface 126. For example, the processing unit 120 may be configured to read from and/or write to external memory, such as the memory 124.]; and
a second direct inter-chip data fabric communicably coupling the second base IC die to the third base IC die, wherein the first and second direct inter-chip data fabrics are configured to provide a multi-hop communications path between the first base IC die and the third base IC die during network bus congestion at a common input/output interface [Chung, Paragraph 0017-0018,…, the one or more stacked DRAM memory die 131, 141, 151 may be connected to the L3 cache layer 121 (and/or processor element 101) using through-silicon via technology. Though not shown, an off-chip main memory subsystem composed of one or more channels may connected to the three-layer die stack 101, 121, 138.].
As per claim 14, Chung and DU teach all the limitations of claim 13 above, where Chung teaches, a processor device, wherein the first DMA engine at the first base IC die is configured to transfer data corresponding to a first portion of the DMA transfer command after splitting into smaller workloads via the multi-hop communications path between the first base IC die and the third base IC die [Chung, Paragraph 0017-0018,…, the one or more stacked DRAM memory die 131, 141, 151 may be connected to the L3 cache layer 121 (and/or processor element 101) using through-silicon via technology. Though not shown, an off-chip main memory subsystem composed of one or more channels may connected to the three-layer die stack 101, 121, 138.].
As per claim 15, Chung and DU teach all the limitations of claim 14 above, where Chung teaches, a processor device, wherein a second DMA engine at the first base IC die is configured to transfer data corresponding to a second portion of the DMA transfer command after splitting into smaller workloads via the common input/output interface [Chung, Paragraph 0017-0018,…, the one or more stacked DRAM memory die 131, 141, 151 may be connected to the L3 cache layer 121 (and/or processor element 101) using through-silicon via technology. Though not shown, an off-chip main memory subsystem composed of one or more channels may connected to the three-layer die stack 101, 121, 138.].
As per claims 16-20,claims 16-20 are rejected in accordance to the same rational and reasoning as the above claims 1-2 and 6-8 above, wherein claims 16-20 are the system claims for the methods of claims 1-2 and 6-8.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
HU et al. (US Patent Application Pub. No: 20170102993 A1) teaches a data storage device includes a controller and a non-volatile memory coupled to the controller.HU discloses the controller is configured to generate first parity information based on first data and to generate second parity information based on second data.HU suggests the non-volatile memory is configured to store the first data and the second data and the data storage device also includes a buffer configured to store the first parity information. HU further discloses the controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.
GHETIE et al. (US Patent Application Pub. No: 20190108347 A1) teaches a processor can be configured to access boot firmware from a remote location independent from use of a chipset and after a processor powers-on or reboots, the processor can execute microcode. GHETIE discloses the microcode will cause the processor to train a link with a remote device. GHETIE suggests the remote device can provide the processor with access to boot firmware and the processor can copy the boot firmware to the processor's cache or memory. GHETIE further discloses the processor will attempt to authenticate the boot firmware and if the boot firmware is authenticated, the processor executes the copy of the boot firmware.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181
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