Prosecution Insights
Last updated: July 17, 2026
Application No. 17/559,427

DYNAMIC PROVISIONING OF PCIE DEVICES AT RUN TIME FOR BARE METAL SERVERS

Final Rejection §103
Filed
Dec 22, 2021
Examiner
PATEL, NIMESH G
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
4 (Final)
77%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
560 granted / 726 resolved
+22.1% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
15 currently pending
Career history
746
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
66.1%
+26.1% vs TC avg
§102
19.8%
-20.2% vs TC avg
§112
4.5%
-35.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 726 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shuler(US 2022/0075747)and Fender(US 2019/0146943). Regarding claim 1, Shuler discloses a system comprising: a peripheral component interconnect express (PCIe) device(Figure 1, 108) that comprises a programmable fabric comprising: a plurality of PCIe physical functions(Paragraph 33, The emulated PCIe switch 136 may also include multiple downstream hardware devices 160 and each of the hardware devices 160 can be populated with an emulated PCIe device 144); and switch circuitry having one or more embedded endpoints that dynamically hides or exposes one or more of the plurality of PCIe physical functions from a bare metal mode host server without using a reset(Paragraph 28, the resource manager 124 may be configured to provide one or more control signals on a control signal path 168 that selectively present and hide a plurality of emulated PCIe devices 140 for the host 104. The resource manager 112 may also be configured to control an emulated PCIe switch 136, which controls a presentation of each PCIe device 144 in the plurality of emulated PCIe devices 140 to the host 104), wherein the bare metal mode server comprises a physical computer server that is used by one consumer or tenant only(Paragraph 25, host 104, in some embodiments, may correspond to one or more of a Personal Computer (PC), a laptop, a tablet, a smartphone, a server, or the like), wherein the bare metal mode host server is a platform where virtualization software is disallowed(Figures 1 and 2, emulation manager 124 is separate from the host 104). Shuler does not specifically disclose the physical functions are implemented with the programmable fabric. However, Fender discloses physical functions implemented within a programmable fabric(Paragraph 30, configurable IC die is configured (e.g., programmed) with two or more of circuit devices, such as circuit devices 65a, 65b . . . 65n, where each circuit device has a different persona. Each circuit device may be a fully compliant PCIe device and have a unique PCIe identity. ). It whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Shuler and Fender to have the physical functions are implemented with the programmable fabric. The motivation to do so would be to have more programmability for flexibility. Regarding claim 2, Shuler and Fender disclose the system of claim 1, wherein the programmable fabric comprises a field-programmable gate array(Paragraph 31: FPGA). Regarding claim 3, Shuler discloses the system of claim 1, wherein the programmable fabric comprises an application- specific integrated circuit(Paragraph 26, In the example of FIG. 1, the NIC 164 is included as part of a smart NIC 108. NIC 164 and resource manager 112 may be provided on a common carrier board or the components of the resource manager 112 may be mounted to the same structure that also houses the NIC 164). Regarding claim 4, Shuler discloses the system of claim 1, comprising the bare metal mode host server coupled to the PCIe device via a PCIe port connection(Paragraph 30, the NIC 164 is connected to the root complex 148 of a host 104 using a cable or wired connection (e.g., utilizing PCIe cables)). Regarding claim 5, Shuler discloses the system of claim 4, wherein the PCIe device comprises a PCIe add-in card(Paragraph 24, Network Interface Card (NIC) 164). Regarding claim 6, Shuler discloses the system of claim 1, wherein the PCIe add-in card comprises an orchestration controller system on a chip (SoC)(Paragraph 26, The resource manager 112 may be provided on a circuit board (e.g., a Printed Circuit Board (PCB)) that is connected to the NIC 164 by one or more wires or traces). Regarding claim 7, Shuler discloses the system of claim 6, wherein the SoC performs backdoor register reprogramming to dynamically expose or hide the one or more of the plurality of PCIe physical functions(Paragraph 34, 43, the hotplug/hot-unplug may be emulated by setting appropriate registers in a configuration space of the NIC 164. As a more specific but non-limiting example, hotplug/hot-unplug may be emulated by setting/unsetting a register in a PCIe configuration space for a corresponding emulated PCIe device 144. The operations of the registers 308 (e.g., the setting of any particular register) may be managed/controlled by the emulation manager 124 using a control signal transmitted over a control signal path 168). Regarding claim 8, Shuler discloses the system of claim 7, wherein the switch circuitry comprises a PCIe upstream switch port, and the backdoor register programming comprises the SoC reprogramming an upstream register corresponding to the PCIe upstream switch port(Paragraph 34, 43, the hotplug/hot-unplug may be emulated by setting appropriate registers in a configuration space of the NIC 164. As a more specific but non-limiting example, hotplug/hot-unplug may be emulated by setting/unsetting a register in a PCIe configuration space for a corresponding emulated PCIe device 144. The operations of the registers 308 (e.g., the setting of any particular register) may be managed/controlled by the emulation manager 124 using a control signal transmitted over a control signal path 168). Regarding claim 9, Shuler discloses the system of claim 8, comprising a plurality of PCIe downstream switch ports, wherein respective PCIe downstream switch ports of the plurality of PCIe downstream switch ports correspond to respective PCIe physical functions of the plurality of PCIe physical functions, and the backdoor register programming comprises the SoC reprogramming downstream registers of the one or more PCIe downstream switch ports of the plurality of PCIe downstream switch ports corresponding to the one or more of the plurality of PCIe physical functions(Paragraph 34,43, the hotplug/hot-unplug may be emulated by setting appropriate registers in a configuration space of the NIC 164. As a more specific but non-limiting example, hotplug/hot-unplug may be emulated by setting/unsetting a register in a PCIe configuration space for a corresponding emulated PCIe device 144. The operations of the registers 308 (e.g., the setting of any particular register) may be managed/controlled by the emulation manager 124 using a control signal transmitted over a control signal path 168). Regarding claim 10, Shuler discloses the system of claim 9, wherein respective PCIe downstream switch ports of the plurality of PCIe downstream switch ports correspond to respective hot plug controllers of a plurality of hot plug controllers(Paragraph 34, the hotplug/hot-unplug may be emulated by setting appropriate registers in a configuration space of the NIC 164. As a more specific but non-limiting example, hotplug/hot-unplug may be emulated by setting/unsetting a register in a PCIe configuration space for a corresponding emulated PCIe device 144). Regarding claim 11, Shuler discloses the system of claim 7, wherein the backdoor register programming comprises accessing or changing values in endpoint registers corresponding to the one or more of the plurality of PCIe physical functions(Paragraph 34, the hotplug/hot-unplug may be emulated by setting appropriate registers in a configuration space of the NIC 164. As a more specific but non-limiting example, hotplug/hot-unplug may be emulated by setting/unsetting a register in a PCIe configuration space for a corresponding emulated PCIe device 144). Regarding claim 12, Shuler discloses the system of claim 11, wherein changing the values in the endpoint registers comprises setting a device type for at least one of the one or more of the plurality of PCIe physical functions in a respective endpoint register of the endpoint registers(Paragraph 30, this type of action (e.g., hotplug/hot-unplug or hot-swap) allows an endpoint (e.g., an emulated PCIe device 144) or one or more emulated PCIe switches 136 with one or more endpoints to be inserted or removed from a system 100 from the perspective of the host 104). Regarding claim 13, Shuler discloses the system of claim 1, wherein the PCIe add-in card hides or exposes the one or more of the plurality of PCIe physical functions according to fields specified in a vendor-defined message(Paragraph 30, this type of action (e.g., hotplug/hot-unplug or hot-swap) allows an endpoint (e.g., an emulated PCIe device 144) or one or more emulated PCIe switches 136 with one or more endpoints to be inserted or removed from a system 100 from the perspective of the host 104. If an appropriate control signal is provided to the NIC 164 from the resource manager 112, then the emulated PCIe switch 136 and one or more of the emulated PCIe devices 140 may appear to the host 104 as being available for access. More specifically, when an emulated PCIe device 144 is hotplugged or hot-swapped in for a host 104, then a hardware device 160 (e.g., a physical port) is made available to the host 104). Regarding claim 14, Shuler discloses a method comprising: receiving, at a peripheral component interconnect express (PCIe) device, a request to expose a PCIe endpoint in a programmable logic device of the PCIe device to a bare metal mode host server coupled to the PCIe device(Paragraph 28, the resource manager 124 may be configured to provide one or more control signals on a control signal path 168 that selectively present and hide a plurality of emulated PCIe devices 140 for the host 104. The resource manager 112 may also be configured to control an emulated PCIe switch 136, which controls a presentation of each PCIe device 144 in the plurality of emulated PCIe devices 140 to the host 104), wherein the bare metal mode server comprises a physical computer server that is used by one consumer or tenant only(Paragraph 25, host 104, in some embodiments, may correspond to one or more of a Personal Computer (PC), a laptop, a tablet, a smartphone, a server, or the like), and wherein the bare metal mode host server is a platform where virtualization software is disallowed(Figures 1 and 2, emulation manager 124 is separate from the host 104); determining a target register in the PCIe device based on the request; and changing the register in the PCIe device to expose the PCIe endpoint to the bare metal mode host server(Paragraph 34, 43, the hotplug/hot-unplug may be emulated by setting appropriate registers in a configuration space of the NIC 164. As a more specific but non-limiting example, hotplug/hot-unplug may be emulated by setting/unsetting a register in a PCIe configuration space for a corresponding emulated PCIe device 144. The operations of the registers 308 (e.g., the setting of any particular register) may be managed/controlled by the emulation manager 124 using a control signal transmitted over a control signal path 168). Shuler does not specifically disclose the physical functions are implemented with the programmable fabric. However, Fender discloses physical functions implemented within a programmable fabric(Paragraph 30, configurable IC die is configured (e.g., programmed) with two or more of circuit devices, such as circuit devices 65a, 65b . . . 65n, where each circuit device has a different persona. Each circuit device may be a fully compliant PCIe device and have a unique PCIe identity. ). It whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Shuler and Fender to have the physical functions are implemented with the programmable fabric. The motivation to do so would be to have more programmability for flexibility. Regarding claim 15, Shuler discloses the method of claim 14, wherein changing the register comprises performing backdoor programming of the register using an orchestration controller system on a chip(Paragraph 26, The resource manager 112 may be provided on a circuit board (e.g., a Printed Circuit Board (PCB)) that is connected to the NIC 164 by one or more wires or traces). Regarding claim 16, Shuler discloses the method of claim 14, wherein changing the register comprises changing the register based on a vendor-defined message sent to the PCIe device Paragraph 30, this type of action (e.g., hotplug/hot-unplug or hot-swap) allows an endpoint (e.g., an emulated PCIe device 144) or one or more emulated PCIe switches 136 with one or more endpoints to be inserted or removed from a system 100 from the perspective of the host 104. If an appropriate control signal is provided to the NIC 164 from the resource manager 112, then the emulated PCIe switch 136 and one or more of the emulated PCIe devices 140 may appear to the host 104 as being available for access. More specifically, when an emulated PCIe device 144 is hotplugged or hot-swapped in for a host 104, then a hardware device 160 (e.g., a physical port) is made available to the host 104). Regarding claim 17, Shuler discloses the method of claim 14, wherein receiving the request comprises a request to expose all PCIe endpoints of the PCIe device based on a common device type between the PCIe endpoints, and changing a register comprises changing multiple registers to expose all of the PCIe endpoints of the PCIe device having the common device type(Paragraph 45, The method begins by determining a number of hardware devices 160 to present to a host device 105 (step 404). This particular step may be performed based on a subscription level of a customer that is operating the host 104. The determining may also depend upon the nature of the hardware device 160, the number of resources requested by the customer, and the number of resources already made available to other customers). Regarding claim 18, Shuler discloses a method comprising: exposing a peripheral component interconnect express (PCIe) endpoint of a plurality of PCIe endpoints of a programmable fabric of a PCIe device to a bare metal mode host server coupled to the PCIe device(Paragraph 28, the resource manager 124 may be configured to provide one or more control signals on a control signal path 168 that selectively present and hide a plurality of emulated PCIe devices 140 for the host 104. The resource manager 112 may also be configured to control an emulated PCIe switch 136, which controls a presentation of each PCIe device 144 in the plurality of emulated PCIe devices 140 to the host 104), wherein the bare metal mode server comprises a physical computer server that is used by one consumer or tenant only(Paragraph 25, host 104, in some embodiments, may correspond to one or more of a Personal Computer (PC), a laptop, a tablet, a smartphone, a server, or the like); receiving, at the PCIe device, a request to hide the PCIe endpoint from the bare metal mode host server coupled to the PCIe device; and changing a register in the PCIe device to hide the PCIe endpoint from the bare metal mode host server(Paragraph 34,43, the hotplug/hot-unplug may be emulated by setting appropriate registers in a configuration space of the NIC 164. As a more specific but non-limiting example, hotplug/hot-unplug may be emulated by setting/unsetting a register in a PCIe configuration space for a corresponding emulated PCIe device 144. The operations of the registers 308 (e.g., the setting of any particular register) may be managed/controlled by the emulation manager 124 using a control signal transmitted over a control signal path 168), wherein the bare metal mode host server is a platform where virtualization software is disallowed(Figures 1 and 2, emulation manager 124 is separate from the host 104). Shuler does not specifically disclose the physical functions are implemented with the programmable fabric. However, Fender discloses physical functions implemented within a programmable fabric(Paragraph 30, configurable IC die is configured (e.g., programmed) with two or more of circuit devices, such as circuit devices 65a, 65b . . . 65n, where each circuit device has a different persona. Each circuit device may be a fully compliant PCIe device and have a unique PCIe identity. ). It whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Shuler and Fender to have the physical functions are implemented with the programmable fabric. The motivation to do so would be to have more programmability for flexibility. Regarding claim 19, Shuler discloses the method of claim 18, wherein exposing the PCIe endpoint comprises exposing the PCIe endpoint as a default exposure as part of a startup of the bare metal mode host server(Paragraph 45, The method begins by determining a number of hardware devices 160 to present to a host device 105 (step 404). This particular step may be performed based on a subscription level of a customer that is operating the host 104). Regarding claim 20, Shuler discloses the method of claim 18, wherein changing the register comprises changing the register using a system on chip (SoC) of the PCle device or based on a vendor-defined message to bypass the SoC(Paragraph 30, this type of action (e.g., hotplug/hot-unplug or hot-swap) allows an endpoint (e.g., an emulated PCIe device 144) or one or more emulated PCIe switches 136 with one or more endpoints to be inserted or removed from a system 100 from the perspective of the host 104. If an appropriate control signal is provided to the NIC 164 from the resource manager 112, then the emulated PCIe switch 136 and one or more of the emulated PCIe devices 140 may appear to the host 104 as being available for access. More specifically, when an emulated PCIe device 144 is hotplugged or hot-swapped in for a host 104, then a hardware device 160 (e.g., a physical port) is made available to the host 104). Response to Arguments Applicant's filed arguments have been fully considered but are not due to new grounds of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMESH G PATEL whose telephone number is (571)272-3640. The examiner can normally be reached Monday-Friday, 8:15-4:15. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMESH G PATEL/Primary Examiner, Art Unit 2176
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Prosecution Timeline

Show 12 earlier events
Nov 19, 2025
Request for Continued Examination
Nov 29, 2025
Response after Non-Final Action
Dec 31, 2025
Non-Final Rejection mailed — §103
Mar 05, 2026
Interview Requested
Mar 11, 2026
Applicant Interview (Telephonic)
Mar 13, 2026
Examiner Interview Summary
Mar 23, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
77%
Grant Probability
84%
With Interview (+7.4%)
2y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 726 resolved cases by this examiner. Grant probability derived from career allowance rate.

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