Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US8615727B2 (Ghanta) in view of US20150069524A1 (Hong), US20220050947A1 (Chai), and US20120117527A1 (Hemmett).
In regards to claim 1 (Ghanta) shows:
A method, comprising:Ghanta [Column 5, Lines 40-50] describes a method for timing analysis in which cell and net delays along paths are aggregated to calculate arrival times and slack values.
receiving a physical design of an electric circuit;Ghanta [Column 4, Lines 35-40] describes receiving a netlist during the netlist verification process, where the design data is checked for compliance with timing constraints and correspondence to the VHDL/Verilog source code, thereby providing the physical design of the electric circuit for timing analysis.
selecting a timing path within the electric circuit;Ghanta [Column 5, Lines 40-50] describes identifying specific timing paths by aggregating the delays of cells and nets along those paths to calculate arrival times and evaluate slack values, enabling the selection of a critical timing path within the electric circuit.
determining whether a timing requirement is met or not met for the selected timing path; and reporting whether the timing requirement is met or not met.Ghanta [Column 6, Lines 5-10] describes generating timing reports using slack samples to determine whether timing passes or fails, thereby determining whether a timing requirement is met or not met for the selected timing path and reporting the result.
Ghanta differs from the claimed invention in that it does not explicitly disclose determining that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor; wherein the first type of transistor differs from the second type of transistor in a type of a gate oxide; based on determining that the selected timing path includes both the first type of transistor and the second type of transistor, running a set of process corners with the first type of transistor at a given corner and the second type of transistor at a condition other than the given corner, the first type of transistor having a delay that is based on process correlation with the second type of transistor; and wherein running the set of process corners includes determining the delay of the first type of transistor by, at least in part, computing a product of a first variable for modeling global process variation and a second variable for modeling local variation.
Chai teaches determining that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor,Chai [0034] and [0038] teach performing static timing analysis on an integrated circuit design to identify pairs of launch and capture paths, wherein a launch path and a capture path each include circuit elements that belong to different classes of circuit elements, for example a class using low voltage threshold (LVT) transistors and other classes using standard voltage threshold (SVT), ultra-low voltage threshold (ULVT), and extremely low voltage threshold (ELVT) transistors, such that a selected timing path is determined to include a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor.
Chai teaches based on determining that the selected timing path includes both the first type of transistor and the second type of transistor, running a set of process corners with the first type of transistor at a given corner and the second type of transistor at a condition other than the given corner, the first type of transistor having a delay that is based on process correlation with the second type of transistor,Chai [0043] and [0050]-[0052] teach that, based on determining the classes of circuit elements in the launch and capture paths, a set of process corners is run by generating assignments in which each class of transistors is assigned either a minimum or a maximum timing derate, such that the first class of transistors is set at a given corner while the second class of transistors is set at a condition other than the given corner, and wherein the correlation among the different classes of circuit elements is explicitly modeled with a correlation matrix, such that the delay of the first type of transistor is based on process correlation with the second type of transistor.
Chai differs from the claimed invention in that it does not explicitly disclose wherein the first type of transistor differs from the second type of transistor in a type of a gate oxide; and wherein running the set of process corners includes determining the delay of the first type of transistor by, at least in part, computing a product of a first variable for modeling global process variation and a second variable for modeling local variation.
Hong teaches wherein the first type of transistor differs from the second type of transistor in a type of a gate oxide;Hong [0018] and [0037] teach a plurality of transistors having different gate dielectric structures integrated on a shared substrate, wherein a first transistor is formed with a first high-k gate dielectric layer comprising hafnium silicate having a relatively lower dielectric constant value and a second transistor is formed with a second high-k gate dielectric layer comprising hafnium oxide having a relatively higher dielectric constant value, thereby providing a first type of transistor that differs from a second type of transistor in a type of a gate oxide.
Hong differs from the claimed invention in that it does not explicitly disclose wherein running the set of process corners includes determining the delay of the first type of transistor by, at least in part, computing a product of a first variable for modeling global process variation and a second variable for modeling local variation.
Hemmett teaches wherein running the set of process corners includes determining the delay of the first type of transistor by, at least in part, computing a product of a first variable for modeling global process variation and a second variable for modeling local variation;Hemmett [0020] and [0021] teach determining a timing delay using an extended canonical form in which a cross-term for the non-separable interaction of a deterministic corner-based (global) variation variable and a statistical (local) process variation variable is computed as their product, thereby computing a product of a first variable for modeling global process variation and a second variable for modeling local variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ghanta and Chai to determine that a selected timing path includes different types of transistors and to run process corners accordingly, with a reasonable expectation of success as both references address static timing analysis of integrated circuit designs across process corners.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta and Chai with Hong to provide first and second types of transistors that differ in a type of a gate oxide, with a reasonable expectation of success as the references address integrated circuit devices formed with transistors of differing characteristics.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, and Hong with Hemmett to compute the delay as a product of a global process variation variable and a local process variation variable, with a reasonable expectation of success as the references address modeling process variation impact on timing delay.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US8615727B2 (Ghanta) in view of US20150069524A1 (Hong), US20220050947A1 (Chai), and US20120117527A1 (Hemmett) as applied to claim 1 above, and further in view of US6033943A (Gardner).
In regards to claim 2 (Ghanta modified by Hong, Chai, and Hemmett) does not show the method of claim 1:
in which the first type of transistor also differs from the second type of transistor in at least one of thickness of the gate oxide, type of implants used to form the transistors, and concentrations of the implants used to form the transistors.
Gardner teaches in which the first type of transistor also differs from the second type of transistor in at least one of thickness of the gate oxide, type of implants used to form the transistors, and concentrations of the implants used to form the transistors.Gardner [Column 6, Lines 5-15] teaches creating transistors with varying gate oxide thicknesses by performing a first oxidation for a thicker layer, followed by etching and a second oxidation for a thinner layer, and further using different types and concentrations of implants to form the transistors, thereby providing that the first type of transistor also differs from the second type of transistor in at least one of thickness of the gate oxide, type of implants, and concentrations of the implants.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, Hong, and Hemmett with Gardner to differentiate the transistors in thickness of the gate oxide, type of implants, or concentrations of the implants, with a reasonable expectation of success as the references address integrated circuits having transistors of differing physical structure.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US8615727B2 (Ghanta) in view of US20150069524A1 (Hong), US20220050947A1 (Chai), and US20120117527A1 (Hemmett) as applied to claim 1 above, and further in view of US20160300004A1 (Barker).
In regards to claim 4 (Ghanta modified by Hong, Chai, and Hemmett) does not show the method of claim 1:
in which running the set of process corners includes determining the delay of the first type of transistor by, at least in part, computing a product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.
Barker teaches a product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.Barker [0053] describes the use of coefficients, such as Pelgrom coefficients, that relate design dimensions to variations in threshold voltage; Barker [0055] describes global variation parameters such as oxide thickness variation and substrate doping density variation; and Barker [0056] describes local variation conditions and their impact on timing delay, thereby teaching computing a product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, Hong, and Hemmett with Barker to compute the delay using a coefficient together with the global and local process variation variables, with a reasonable expectation of success as the references address statistical modeling of process variation impact on timing delay.
In regards to claim 5 (Ghanta modified by Hong, Chai, and Hemmett) does not show the method of claim 1:
in which running the set of process corners includes determining the delay of the first type of transistor by computing, at least in part: a first product of a first coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation; a second product of a second coefficient and the first variable for modeling global process variation; and a sum of the first product, the second product, and a nominal delay value for the first type of transistor.
Barker teaches a first product of a first coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation; a second product of a second coefficient and the first variable for modeling global process variation; and a sum of the first product, the second product, and a nominal delay value for the first type of transistor.Barker [0053] describes coefficients for process variations such as the Pelgrom coefficient; Barker [0055] details global process variation parameters including oxide thickness and substrate doping density variation; and Barker [0056] addresses local process variations and their impact on delay computations, thereby teaching computing a first product of a first coefficient with the global and local variables, a second product of a second coefficient with the global variable, and a sum of the first product, the second product, and a nominal delay value.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, Hong, and Hemmett with Barker to compute the delay using a coefficient together with the global and local process variation variables, with a reasonable expectation of success as the references address statistical modeling of process variation impact on timing delay.
Claims 6, 8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US8615727B2 (Ghanta) in view of US20220050947A1 (Chai) and US20110066997A1 (O'Riordan).
In regards to claim 6 (Ghanta) shows:
A non-transitory storage device containing software that, when executed by a computer system, causes the computer system to:Ghanta [Column 5, Lines 10-15] describes static timing analysis performed by software during the netlist verification and analysis steps, and Ghanta [Column 12, Lines 20-30] describes that the samples-based static timing analysis is implemented in one or more computer programs that execute on a programmable system including a programmable processor coupled to a data storage system, corresponding to a non-transitory storage device containing software that, when executed by a computer system, causes the computer system to perform the recited operations.
receive a physical design of an electric circuit;Ghanta [Column 4, Lines 35-40] describes receiving a netlist during the netlist verification process, where the design data is checked for compliance with timing constraints and correspondence to the VHDL/Verilog source code, thereby providing the physical design of the electric circuit for timing analysis.
select a timing path within the electric circuit;Ghanta [Column 5, Lines 40-50] describes identifying specific timing paths by aggregating the delays of cells and nets along those paths to calculate arrival times and evaluate slack values, enabling the selection of a critical timing path within the electric circuit.
determine whether a timing requirement is met or not met for the selected timing path; and report whether the timing requirement is met or not met.Ghanta [Column 6, Lines 5-10] describes generating timing reports using slack samples to determine whether timing passes or fails, thereby determining whether a timing requirement is met or not met for the selected timing path and reporting the result.
Ghanta differs from the claimed invention in that it does not explicitly disclose determine that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor different from the first type of transistor; select, based on determining that the selected timing path includes both the first type of transistor and the second type of transistor, a timing delay model from among a plurality of timing delay models; the selected timing delay model including at least one cross-term that is a product of a first variable for modeling global process variation and a second variable for modeling local variation; analyze, using the selected timing delay model, delays of the first type of transistor at a slow corner and the second type of transistor faster than a slow corner of the second type of transistor, the first type of transistor having a delay that is based on process correlation with the second type of transistor; analyze, using the selected timing delay model, delays of the first type of transistor at its respective fast corner and the second type of transistor slower than a fast corner of the second type of transistor; and by determining the delay of the first type of transistor by, at least in part, computing the product of the first variable for modeling global process variation and the second variable for modeling local variation.
Chai teaches determine that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor different from the first type of transistor;Chai [0034] and [0038] teach performing static timing analysis to identify pairs of launch and capture paths, wherein the paths include circuit elements belonging to different classes of transistors (for example LVT, SVT, ULVT, and ELVT), such that the selected timing path is determined to include a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor different from the first type of transistor.
Chai teaches select, based on determining that the selected timing path includes both the first type of transistor and the second type of transistor, a timing delay model from among a plurality of timing delay models,Chai [0041], [0044], and [0047] teach a plurality of timing delay models, including a corner-based model and a statistical model, from among which a model is selected based on the classes of circuit elements in the path.
Chai teaches analyze, using the selected timing delay model, delays of the first type of transistor at a slow corner and the second type of transistor faster than a slow corner of the second type of transistor, the first type of transistor having a delay that is based on process correlation with the second type of transistor;Chai [0043] and [0050]-[0052] teach analyzing delays by assigning the first class of transistors a maximum (slow) derate while the second class of transistors is assigned a different derate faster than the slow corner, wherein the correlation among classes is explicitly modeled, such that the delay of the first type of transistor is based on process correlation with the second type of transistor.
Chai teaches analyze, using the selected timing delay model, delays of the first type of transistor at its respective fast corner and the second type of transistor slower than a fast corner of the second type of transistor;Chai [0043] teaches enumerating combinations of minimum and maximum derates for the classes of transistors, such that the first class is analyzed at its respective fast corner while the second class is analyzed slower than a fast corner of the second class.
Chai differs from the claimed invention in that it does not explicitly disclose the selected timing delay model including at least one cross-term that is a product of a first variable for modeling global process variation and a second variable for modeling local variation; and by determining the delay of the first type of transistor by, at least in part, computing the product of the first variable for modeling global process variation and the second variable for modeling local variation.
O'Riordan teaches the selected timing delay model including at least one cross-term that is a product of a first variable for modeling global process variation and a second variable for modeling local variation;O'Riordan [0042] and [0053] teach delay computations in which correlation coefficients relating device parameters are multiplied together, thereby providing a cross-term that is a product of a variable for modeling global process variation and a variable for modeling local variation.
O'Riordan teaches by determining the delay of the first type of transistor by, at least in part, computing the product of the first variable for modeling global process variation and the second variable for modeling local variation;O'Riordan [0042] and [0082] teach software that computes the product of variables representing global manufacturing variations and local device-specific variation effects, thereby determining the delay by computing the product of the first variable for modeling global process variation and the second variable for modeling local variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ghanta and Chai to determine that a selected timing path includes different types of transistors and to analyze delays of the transistor types at differing corner conditions, with a reasonable expectation of success as both references address static timing analysis across process corners.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta and Chai with O'Riordan to compute the delay as a product of variables representing global and local process variation, with a reasonable expectation of success as the references address modeling of process variation effects on device delay.
In regards to claim 8 (Ghanta modified by Chai) does not show the non-transitory storage device of claim 6:
in which the software causing the computer system to analyze the delays includes the software causing the computer system to compute the product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.
O'Riordan teaches in which the software causing the computer system to analyze the delays includes the software causing the computer system to compute the product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.O'Riordan [0082] and [0042] teach software simulators that access internal data structures containing correlation coefficients and compute mathematical relationships in which coefficients are multiplied with process variation parameters, thereby computing the product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ghanta, Chai, and O'Riordan to compute the product of a coefficient with the global and local process variation variables, with a reasonable expectation of success as the references address modeling of process variation effects on device delay.
In regards to claim 10 (Ghanta modified by Chai) does not show the non-transitory storage device of claim 8:
wherein the product is a first product, and wherein the software causing the computer system to analyze the delays includes the software causing the computer system to determine the delay of the first type of transistor by computing, at least in part: a second product of a second coefficient and the first variable for modeling global process variation; and a sum of the first product, the second product, and a nominal delay value for the first type of transistor.
O'Riordan teaches wherein the product is a first product, and wherein the software causing the computer system to analyze the delays includes the software causing the computer system to determine the delay of the first type of transistor by computing, at least in part: a second product of a second coefficient and the first variable for modeling global process variation; and a sum of the first product, the second product, and a nominal delay value for the first type of transistor.O'Riordan [0079] and [0080] teach software-implemented computations involving multiple correlation coefficients, including a first coefficient product for a first group of parameters and a second coefficient product for a second group of parameters, combined through additive operations with baseline values, thereby computing a second product of a second coefficient and the global process variation variable and a sum of the first product, the second product, and a nominal delay value.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ghanta, Chai, and O'Riordan to compute the product of a coefficient with the global and local process variation variables, with a reasonable expectation of success as the references address modeling of process variation effects on device delay.
In regards to claim 11 (Ghanta) shows:
A computer system, comprising: a storage device containing software; and a processor coupled to the storage device, wherein, when executed by the processor, the software causes the processor to:Ghanta [Column 12, Lines 20-30] describes a system in which software is stored in a storage device and executed by a processor coupled to the storage device to perform samples-based static timing analysis, corresponding to the recited computer system comprising a storage device containing software and a processor.
receive a physical design of an electric circuit;Ghanta [Column 4, Lines 35-40] describes receiving a netlist during the netlist verification process, where the design data is checked for compliance with timing constraints and correspondence to the VHDL/Verilog source code, thereby providing the physical design of the electric circuit for timing analysis.
select a timing path within the electric circuit;Ghanta [Column 5, Lines 40-50] describes identifying specific timing paths by aggregating the delays of cells and nets along those paths to calculate arrival times and evaluate slack values, enabling the selection of a critical timing path within the electric circuit.
determine whether a timing requirement is met or not met for the selected timing path; and report whether the timing requirement is met or not met.Ghanta [Column 6, Lines 5-10] describes generating timing reports using slack samples to determine whether timing passes or fails, thereby determining whether a timing requirement is met or not met for the selected timing path and reporting the result.
Ghanta differs from the claimed invention in that it does not explicitly disclose determine that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor that differs from the first type of transistor; based on determining that the selected timing path includes both the first type of transistor and the second type of transistor, run a set of process corners with the first type of transistor at a slow corner and the second type of transistor faster than a slow corner of the second type of transistor; and the first type of transistor having a delay that is determined based on a product of a first variable for modeling global process variation and a second variable for modeling local variation.
Chai teaches determine that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor that differs from the first type of transistor;Chai [0034] and [0038] teach performing static timing analysis to identify pairs of launch and capture paths, wherein the paths include circuit elements belonging to different classes of transistors (for example LVT, SVT, ULVT, and ELVT), such that the selected timing path is determined to include a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor different from the first type of transistor.
Chai teaches based on determining that the selected timing path includes both the first type of transistor and the second type of transistor, run a set of process corners with the first type of transistor at a slow corner and the second type of transistor faster than a slow corner of the second type of transistor,Chai [0043] and [0050]-[0052] teach that, based on determining the classes of circuit elements in the launch and capture paths, a set of process corners is run in which the first class of transistors is assigned a maximum (slow) derate while the second class of transistors is set faster than the slow corner, such that the first type of transistor is run at a slow corner and the second type of transistor faster than a slow corner of the second type of transistor.
Chai differs from the claimed invention in that it does not explicitly disclose the first type of transistor having a delay that is determined based on a product of a first variable for modeling global process variation and a second variable for modeling local variation.
O'Riordan teaches the first type of transistor having a delay that is determined based on a product of a first variable for modeling global process variation and a second variable for modeling local variation;O'Riordan [0053] and [0079] teach computing delay parameters using mathematical products of correlation coefficients representing global and local variation effects, thereby determining the delay based on a product of a first variable for modeling global process variation and a second variable for modeling local variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Ghanta and Chai to run a set of process corners with the first type of transistor at a slow corner and the second type of transistor faster than a slow corner, with a reasonable expectation of success as both references address static timing analysis across process corners.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta and Chai with O'Riordan to compute the delay as a product of variables representing global and local process variation, with a reasonable expectation of success as the references address modeling of process variation effects on device delay.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US8615727B2 (Ghanta) in view of US20220050947A1 (Chai) and US20110066997A1 (O'Riordan) as applied to claim 6 above, and further in view of US6033943A (Gardner).
In regards to claim 7 (Ghanta modified by Chai and O'Riordan) does not show the non-transitory storage device of claim 6:
in which the first type of transistor differs from the second type of transistor in at least one of type of a gate oxide, thickness of the gate oxide, type of implants used to form the transistors, and concentrations of the implants used to form the transistors.
Gardner teaches in which the first type of transistor differs from the second type of transistor in at least one of type of a gate oxide, thickness of the gate oxide, type of implants used to form the transistors, and concentrations of the implants used to form the transistors.Gardner [Column 6, Lines 5-15] describes creating transistors with varying gate oxide thicknesses by performing a first oxidation for a thicker layer followed by etching and a second oxidation for a thinner layer, and using different implant types and concentrations to form the transistors, thereby differentiating the transistors in at least one of type of a gate oxide, thickness of the gate oxide, type of implants, and concentrations of the implants.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, and O'Riordan with Gardner to differentiate the transistors in gate oxide type, gate oxide thickness, or implants, with a reasonable expectation of success as the references address integrated circuits having transistors of differing physical structure.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over US8615727B2 (Ghanta) in view of US20220050947A1 (Chai) and US20110066997A1 (O'Riordan) as applied to claim 11 above, and further in view of US6033943A (Gardner).
In regards to claim 12 (Ghanta modified by Chai and O'Riordan) does not show the computer system of claim 11:
in which the first type of transistor differs from the second type of transistor in at least one of type of a gate oxide, thickness of the gate oxide, type of implants used to form the transistors, and concentrations of the implants used to form the transistors.
Gardner teaches in which the first type of transistor differs from the second type of transistor in at least one of type of a gate oxide, thickness of the gate oxide, type of implants used to form the transistors, and concentrations of the implants used to form the transistors.Gardner [Column 6, Lines 5-15] describes creating transistors with varying gate oxide thicknesses by performing a first oxidation for a thicker layer followed by etching and a second oxidation for a thinner layer, and using different implant types and concentrations to form the transistors, thereby differentiating the transistors in at least one of type of a gate oxide, thickness of the gate oxide, type of implants, and concentrations of the implants.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, and O'Riordan with Gardner to differentiate the transistors in gate oxide type, gate oxide thickness, or implants, with a reasonable expectation of success as the references address integrated circuits having transistors of differing physical structure.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US8615727B2 (Ghanta) in view of US20220050947A1 (Chai) and US20110066997A1 (O'Riordan) as applied to claim 11 above, and further in view of US20160300004A1 (Barker).
In regards to claim 14 (Ghanta modified by Chai and O'Riordan) does not show the computer system of claim 11:
in which the processor is configured to determine the delay of the first type of transistor by, at least in part, computing the product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.
Barker teaches the product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.Barker [0053] describes coefficients such as the Pelgrom coefficient that tie design dimensions to variability; Barker [0055] describes global process variation parameters including oxide thickness and substrate doping density variation; and Barker [0056] addresses local variation parameters, thereby teaching computing the product of a coefficient, the first variable for modeling global process variation, and the second variable for modeling local variation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, and O'Riordan with Barker to compute the product of a coefficient with the global and local process variation variables, with a reasonable expectation of success as the references address statistical modeling of process variation impact on timing delay.
In regards to claim 15 (Ghanta modified by Chai, O'Riordan, and Barker) does not show the computer system of claim 14:
wherein the product is a first product and wherein the processor is configured to determine the delay of the first type of transistor by, at least in part, computing: a second product of a second coefficient and the first variable for modeling global process variation; and a sum of the first product, the second product, and a nominal delay value for the first type of transistor.
O'Riordan teaches a second product of a second coefficient and the first variable for modeling global process variation; and a sum of the first product, the second product, and a nominal delay value for the first type of transistor.O'Riordan [0079] and [0080] teach processor-based computations in which multiple correlation coefficients are applied to different parameter groups, including a first coefficient product and a second coefficient product, combined through summation with nominal values, thereby computing a second product of a second coefficient and the global process variation variable and a sum of the first product, the second product, and a nominal delay value.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Ghanta, Chai, O'Riordan, and Barker to compute a second coefficient product and a sum with a nominal delay value, with a reasonable expectation of success as the references address statistical modeling of device delay.
Response to Arguments
Applicant's arguments filed on July 13, 2026 have been fully considered but are not persuasive for the reasons set forth below. Applicant's amendments necessitated the newly cited reference US20220050947A1 (Chai), which qualifies as prior art under 35 U.S.C. 102(a)(2) by virtue of its effective filing date of August 5, 2021, prior to the December 22, 2021 effective filing date of the present application.
Applicant argues that the standard for inherency has not been met because a given timing path need not necessarily include logic cells implemented with two different types of transistors. This argument is moot in view of the present rejection, which no longer relies on inherency for this limitation. Chai [0034] and [0038] expressly teach performing static timing analysis to identify launch and capture paths that include circuit elements belonging to different classes of transistors, thereby determining that a selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor.
Applicant argues that the asserted combination does not disclose running a particular set of process corners based on determining that a selected timing path includes both the first and the second type of transistor. The Examiner respectfully disagrees. Chai [0043] and [0050]-[0052] teach that, based on the classes of circuit elements identified in the launch and capture paths, a set of process corners is run in which each class of transistors is assigned a different (minimum or maximum) derate, with the correlation among the classes explicitly modeled, such that the first type of transistor is set at a given corner and the second type at a condition other than the given corner with a delay based on process correlation between the two types.
With respect to the gate oxide type limitation, Hong [0018] and [0037] teach transistors having different gate dielectric structures (hafnium silicate versus hafnium oxide) integrated on a shared substrate; and with respect to the product limitation, Hemmett [0020] and [0021] teach computing a cross-term that is the product of a global corner-based variation variable and a local statistical variation variable. Accordingly, the amended claims remain unpatentable over the cited combinations, and the rejections are maintained as modified above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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