DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Specification Objections
Applicant has amended the specification at issue and the previous objections have therefore been withdrawn.
Claim Rejections – 35 USC 112
Applicant has amended the claims at issue and the previous rejections have therefore been withdrawn.
Prior Art Rejections
Applicant's arguments filed September 4, 2025 have been fully considered but they are not persuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Moreover, Anderson Figure 8 shows checking for consecutive zeroes comprising a chain of AND gates, and Iacono [0054]-[0055] suggests that person having ordinary skill in the art (PHOSITA) may substitute a series of AND gates to a logically equivalent series of other logic gates, which includes a chain of OR gates.
In particular, a PHOSITA will look at Anderson and Iacono with a basic understanding of digital design and understand that they can apply De Morgan's law (evidentiary reference Wikipedia page) to come up with alternate equivalent circuits. A use of De Morgan’s law for the conversion may be shown as (A’B’)’ = A’’ + B’’ = A + B, wherein the apostrophe represents inversion. Hence, by adding inverters in a way to maintain logical equivalence in Figure 8 of Anderson, a PHOSITA may substitute the chain of AND gates to a chain of OR gates as shown below, wherein each circle represents an inverter:
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For clarity, after adding inverters as shown above, the use of De Morgan’s law, (A’B’)’ = A’’ + B’’ = A + B, allows of the series of AND gates with corresponding inverters to be converted into a series of OR gates while maintaining the same logical function of Anderson.
Additionally, it is noted that with the example substitution, the outputs of elements 830, 832, 834 of Anderson Fig. 8 are now of the form P[N]⨀K[N-1], where P[N] = A[N] ⨁ B[N] and K[N]= ~(A[N] | B[N]) which directly corresponds to the second mask definition of claim 6.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-23 are rejected under 35 U.S.C. 103 as being anticipated by Anderson et al. (US 20130013656 A1, hereinafter "Anderson") in view of Iacono (US 20040073586 A1, hereinafter “Iacono”).
As per claim 1, Anderson teaches An apparatus comprising: first circuitry to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first circuitry in parallel with generation of the sum by an adder (Anderson: Fig. 6 elements 640, 642, 644, [0048]- [0049]);
However, while Anderson teaches a consecutive zeros predictor (Fig. 8, [0059]; The Examiner notes the title of Fig. 8 of Anderson contains a typo), Anderson does not explicitly teach circuitry comprising an OR chain. Thus, Anderson does not teach and second circuitry to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second circuitry in parallel with generation of the sum.
Iacono teaches and a second mask to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second mask in parallel with generation of the sum (Iacono: Fig. 7A – 7B; [0049], [0055]; wherein Iacono suggests a PHOSITA may substitute an AND chain to a desired chain, an exemplary example discussed in response to arguments above).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the consecutive zeros predictor of Anderson with the teachings of Iacono. One would have been motivated to combine these references because both references disclose detecting all bits of a bit-string to be the same value, and combining prior art elements according to known methods to yield predictable results (modifying circuitry to logically equivalent circuitry).
As per claim 2, Anderson/Iacono further teaches the apparatus of claim 1, the first circuitry to generate an increment of any portion of the sum using an AND chain of the first circuitry in parallel with generation of the sum (Anderson: Fig. 9 element 904, [0068]).
As per claim 3, Anderson/Iacono further teaches The apparatus of claim 1, the second circuitry to generate a decrement of any portion of the sum using an OR chain of the second circuitry in parallel with generation of the sum (Anderson: Fig. 9 element 906, [0069]).
As per claim 4, Anderson/Iacono further teaches the apparatus of claim 1, wherein the first circuitry is defined by First Mask[k] ≝ P[k] ⨁ G[k -1] for n ≥ k > i where G[k] is generation and P[k] is propagation of an adder at bit position 'k' which is computed from the first input operand denoted X[n:0] and the second input operand denoted Y[n:0] as G [k]=X[k] & Y[k] and P[k]=X[k] ⨁ Y[k] (Anderson: Fig. 6, [0038] Of note equation 7, [0035]).
As per claim 5, Anderson/Iacono further teaches the apparatus of claim 1, wherein the first circuitry is defined by First Mask[k]=X[k]⨁Y[k]⊕(X[k-1]&Y[k-1]) wherein the first input operand is denoted X[n:0], the second input operand is denoted Y[n:0], and 'k' is a bit position of an adder (Anderson: Fig. 6, [0038], [0035]).
As per claim 6, Anderson/Iacono further teaches The apparatus of claim 1, wherein the second circuitry is defined by Second Mask[k]≝ P[k]⨀Z[k-1]for n≥k>i where Z[k] is zero and P[k] is propagation of an adder at bit position 'k' which is computed from the first input operand denoted X[n:0] and the second input operand denoted Y[n:0] as Z[k]= ~(X[k] | Y[k]) and P[k]=X[k] ⨁ Y[k] (Anderson: Fig. 8, [0055], [0035]; A more explanation is discussed in the response to arguments above).
As per claim 7, Anderson/Iacono further teaches The apparatus of claim 1, wherein the second circuitry is defined by Second Mask[k]≝ X[k]⨁Y[k]⊕(X[k-1] | Y[k-1]) wherein the first input operand is denoted X[n:0], the second input operand is denoted Y[n:0], and 'k' is a bit position of an adder (Anderson: Fig. 8, [0055], [0035]). The definition of the second mask of claim 7 is logically equivalent to claim 6 as shown: P[k]⨀Z[k-1]
= (P[k] & Z[k-1]) | (~P[k] & ~Z[k-1])
= ((X[k] ⨁ Y[k]) & (~(X[k-1] | Y[k-1]))) | (~(X[k] ⨁ Y[k]) & ~ (~(X[k-1] | Y[k-1])))
= ((X[k] ⨁ Y[k]) & ~(X[k-1] | Y[k-1])) | (~(X[k] ⨁ Y[k]) & (X[k-1] | Y[k-1]))
= (X[k]⨁Y[k]) ⊕ (X[k-1] | Y[k-1])
= X[k]⨁Y[k]⊕(X[k-1] | Y[k-1])
As per claim 8, Anderson/Iacono further teaches The apparatus of claim 1, comprising generating the selected portion of the OR of the sum of the first input operand and the second input operand in parallel with a carry chain of the adder at a lesser delay than the carry chain (Anderson: [0069]).
As per claim 9, Anderson/Iacono further teaches the apparatus of claim 1, comprising generating the selected portion of the AND of the sum of the first input operand and the second input operand in parallel with a carry chain of the adder at a lesser delay than the carry chain (Anderson: [0068]).
As per claims 10-18, the claims are directed to a method that implements the same or similar features as the apparatus of claims 1-9, respectively, and are therefore rejected for at least the same reasons therein.
As per claims 19-23, the claims are directed to a method that implements the same or similar features as the apparatus of claims 1-4, 6, respectively, and are therefore rejected for at least the same reasons therein.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182