DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 110 and 326.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 9 and 15-20 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 9 lines 1-2, “wherein the embedded arithmetic block comprises” should read “wherein the embedded arithmetic block further comprises” instead for better clarity.
B. In claim 15 line 5, “the embedded arithmetic blocks” should read “the plurality of arithmetic blocks” instead for consistency of claim terminologies. Claims 16-20 inherit the same deficiency as claim 1 by reason of dependence.
C. In claim 17, lines 1-2, “wherein the at least one of the plurality of arithmetic blocks comprises” should read “wherein the at least one of the plurality of arithmetic blocks further comprises” instead for better clarity. Claim 18 recites a similar limitation and is objected to for the same reason.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 10 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “wherein the via-configured structured logic circuitry comprises a via-configured feedback path that couples an output of the embedded arithmetic block with an input of the embedded arithmetic block”. It is unclear how feedback path of one circuit couples an output of a different circuit back to the input of the different circuit. For purposes of examination, this is interpreted as wherein the via-configured structured logic circuitry comprises a via-configured feedback path that couples an output of the embedded arithmetic block with an input of the via-configured structured logic circuitry consistent with Fig. 15 where output 146 of the embedded arithmetic block 80 being connected to an input of the via-configured structured logic circuitry 88.
Claim 10 recites “wherein the embedded arithmetic block, in concert with the via-configured structured logic circuitry, provides a functionality that can be performed using a digital signal processing (DSP) block of a field-programmable gate array (FPGA)”. This limitation is unclear because the use of the phrase “can be” creates confusion as to whether the subsequent limitations are required or optional. Furthermore, it is unclear what are the functionalities that can be performed by a DSP block of an FPGA. Paragraph [0068] only provides two examples (i.e., Finite Impulse Response (FIR) and Fast Fourier Transform (FFT)), however, it is unclear whether these are the only functionalities that can be performed by DSP block of an FPGA. Further, clarification is required.
Claim 19 recites “the at least one of the plurality of arithmetic blocks” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. The at least one of the plurality of arithmetic blocks is introduced in claim 16, however, claim 19 does not depend on claim 16. For purposes of examination, this is interpreted as at least one of the plurality of arithmetic blocks. Claim 20 recites a similar limitation and is rejected for the same reason.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Andreev et al. (US 20140103959 A1), hereinafter Andreev.
Regarding claim 1, Andreev teaches an integrated circuit comprising:
via-configured structured logic circuitry (Andreev Fig. 3B and paragraph [0073] “The Structured ASIC has logic unit block module array 203 that contain, inter alia, transistor based, via-programmable, via-configurable logic block (VCLB) or logic cells 105 for building any sort of random logic, sequential circuit or combinational circuit”; paragraph [0084] “Matrix 203 has customizable logic, such as a via-configurable logic block (VCLB), or any other type of mask-programmable logic or logic, using transistors that are connected to one another, often by vias, and the vias can configurable by a user or customer of the Structured ASIC chip 100”; via-configured structured logic circuitry - VCLB or logic cells 105); and
an embedded arithmetic block that interfaces with the via-configured structured logic circuitry to perform an arithmetic function, wherein the embedded arithmetic block comprises a plurality of monolithic arithmetic circuits (Andreev Fig. 3B and paragraph [0084] “In FIG. 3B, eight full adders 204 surround each four-by-four block 206 of tiled pattern logic block cells 105 of the eMotif eCELL Matrix 203 from the outside. There are 32 full adders 204 for each eMotif eCELL Matrix 203, as shown. Full adders are often used in addition and complex multiplication of the kind performed by communications ASICs and in multiplexers”; embedded arithmetic block – 32 full adders 204).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Andreev as applied to claim 1 above, and further in view of Hutton et al. (NPL – “A Methodology for FPGA to Structured-ASIC Synthesis and Verification”), hereinafter Hutton.
Regarding claim 2, Andreev teaches all the limitations of claim 1 as stated above.
Andreev does not explicitly teach wherein the via-configured structured logic circuitry comprises a plurality of via-configured lookup tables.
However, on the same field of endeavor, Hutton discloses a via-configured structured logic circuitry that comprises a plurality of via-configured lookup tables (Hutton Figs. 1 and 6-8 and section 2 “SRAM-based FPGA logic cells normally consist of k-input LUTs and flip-flops … We will use the term HCell to represent the fine-grained basic logic unit which forms the logic fabric in the structured ASIC base array. It is similar to the FPGA logic cell”; section 2.2 left col “We used 100 commercial FPGA designs above 25,000 LUT4 logic elements in size. Each was reimplemented in HCell macros by the synthesis flow (described in Section 3) and then placed and routed using commercial ASIC placement tools”; page 5 right col top “first we optimize the FPGA logic cell using a minimal number of HCells. Then in a recursive manner we select LUTs to cover the whole HCell network according to the following criteria – these LUTs have to be part of the ASIC library”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev using Hutton and configure the logic cells 105 to include a plurality of LUTs to implement the sequential or combinational circuits or functions of the logic cells 105 (Hutton section 2.1).
Therefore, the combination of Andreev as modified using Hutton teaches wherein the via-configured structured logic circuitry comprises a plurality of via-configured lookup tables.
Regarding claim 10, Andreev teaches all the limitations of claim 1 as stated above.
Andreev does not explicitly teach wherein the embedded arithmetic block, in concert with the via-configured structured logic circuitry, provides a functionality that can be performed using a digital signal processing (DSP) block of a field-programmable gate array (FPGA).
However, on the same field of endeavor, Hutton discloses a via-configured structured logic circuitry that provides a functionality that can be performed using a digital signal processing (DSP) block of a field-programmable gate array (FPGA) (Hutton section 2 page 2 right col bottom “A group of HCells together emulate a given FPGA combinational logic cell, DFF, or DSP (multiplier) block”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev using Hutton and configure the logic cells and the full adders to emulate a functionality of a DSP block of an FPGA in order to build the DSP blocks only on as-needed basis for a particular mode of the FPGA DSP block (Hutton section 2.1 paragraph above Fig. 6).
Therefore, the combination of Andreev as modified in view of Hutton teaches wherein the embedded arithmetic block, in concert with the via-configured structured logic circuitry, provides a functionality that can be performed using a digital signal processing (DSP) block of a field-programmable gate array (FPGA).
Claims 4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Andreev as applied to claim 1 above, and further in view of Boswell et al. (US 20180321938 A1), hereinafter Boswell.
Regarding claim 4, Andreev teaches all the limitations of claim 1 as stated above.
Andreev does not explicitly teach wherein the embedded arithmetic block comprises a multiplier.
However, on the same field of endeavor, Boswell discloses an arithmetic block comprises a multiplier (Boswell Fig. 10 and paragraphs [0112-0113] multiplier – multiplier 1010).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev using Boswell and configure the arithmetic block to include a multiplier in order to implement FMA operations in combination with the adders (Boswell paragraph [0112]).
Therefore, the combination of Andreev as modified using Boswell teaches wherein the embedded arithmetic block comprises a multiplier.
Regarding claim 6, Andreev as modified in view of Boswell teaches all the limitations of claim 4 as stated above. Further, Andreev as modified in view of Boswell teaches wherein the via-configured structured logic circuitry comprises structured logic circuitry that has been via-configured to form a pre-adder to perform an addition function prior to the embedded arithmetic block (Andreev Fig. 3B and paragraph [0084]).
Regarding claim 7, Andreev as modified in view of Boswell teaches all the limitations of claim 4 as stated above.
Andreev does not explicitly teach wherein the embedded arithmetic block comprises a post-adder to perform an addition function using outputs of the multiplier.
However, on the same field of endeavor, Boswell discloses an arithmetic block that comprises an adder that performs an addition function using outputs of a multiplier (Boswell Fig. 10 and paragraphs [0113-0115] adder – 3:2 CSA 1040 and/or completion adder 1050).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev using Boswell and configure the arithmetic block to include an adder downstream of the multiplier to perform an addition function using outputs of the multiplier in order to implement FMA operations (Boswell paragraph [0112]).
Therefore, the combination of Andreev as modified in view of Boswell teaches wherein the embedded arithmetic block comprises a post-adder to perform an addition function using outputs of the multiplier.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Andreev in view of Hutton.
Regarding claim 15, Andreev teaches an integrated circuit comprising:
via-configured structured logic circuitry (Andreev Fig. 3B and paragraph [0073] “The Structured ASIC has logic unit block module array 203 that contain, inter alia, transistor based, via-programmable, via-configurable logic block (VCLB) or logic cells 105 for building any sort of random logic, sequential circuit or combinational circuit”; paragraph [0084] “Matrix 203 has customizable logic, such as a via-configurable logic block (VCLB), or any other type of mask-programmable logic or logic, using transistors that are connected to one another, often by vias, and the vias can configurable by a user or customer of the Structured ASIC chip 100”; via-configured structured logic circuitry - VCLB or logic cells 105); and
a plurality of arithmetic blocks embedded adjacent to the via-configured structured logic circuitry, wherein the embedded arithmetic blocks comprise a plurality of monolithic arithmetic circuits (Andreev Figs. 3A-3B and paragraph [0084] “In FIG. 3B, eight full adders 204 surround each four-by-four block 206 of tiled pattern logic block cells 105 of the eMotif eCELL Matrix 203 from the outside. There are 32 full adders 204 for each eMotif eCELL Matrix 203, as shown. Full adders are often used in addition and complex multiplication of the kind performed by communications ASICs and in multiplexers”; plurality of arithmetic blocks – 32 full adders 204 in each of modules 203).
Andreev does not explicitly teach the via-configured structured logic circuitry having a plurality of via-configured lookup tables and a plurality of via-configured routing wires.
However, on the same field of endeavor, Hutton discloses a via-configured structured logic circuitry that comprises a plurality of via-configured lookup tables and a plurality of via-configured routing wires (Hutton Figs. 1 and 6-8 and section 2 “SRAM-based FPGA logic cells normally consist of k-input LUTs and flip-flops … We will use the term HCell to represent the fine-grained basic logic unit which forms the logic fabric in the structured ASIC base array. It is similar to the FPGA logic cell”; section 2.2 left col “We used 100 commercial FPGA designs above 25,000 LUT4 logic elements in size. Each was reimplemented in HCell macros by the synthesis flow (described in Section 3) and then placed and routed using commercial ASIC placement tools”; page 5 right col top “first we optimize the FPGA logic cell using a minimal number of HCells. Then in a recursive manner we select LUTs to cover the whole HCell network according to the following criteria – these LUTs have to be part of the ASIC library”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev using Hutton and configure the logic cells 105 to include a plurality of LUTs and a plurality of via-configured routing wires to implement the sequential or combinational circuits or functions of the logic cells 105 (Hutton section 2.1).
Therefore, the combination of Andreev as modified using Hutton teaches via-configured structured logic circuitry having a plurality of via-configured lookup tables and a plurality of via-configured routing wires.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Andreev in view of Hutton as applied to claim 15 above, and further in view of Abdelaziz et al. (US 20210319079 A1), hereinafter, Abdelaziz.
Regarding claim 16, Andreev as modified using Hutton teaches all the limitations of claim 15 as stated above.
Andreev does not explicitly teach wherein at least one of the plurality of arithmetic blocks comprises an array of monolithic multipliers.
However, on the same field of endeavor, Abdelaziz discloses an arithmetic block that comprises an array of multipliers (Abdelaziz Fig. 2 and paragraph [0031] array of multipliers - section 204 in each block 2010-210N).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev in view of Hutton using Abdelaziz and configure at least one arithmetic block to include an array of multipliers in order to implement dot-product operations (Abdelaziz paragraph [0029]).
Therefore, the combination of Andreev as modified in view of Hutton and Abdelaziz teaches wherein at least one of the plurality of arithmetic blocks comprises an array of monolithic multipliers.
Regarding claim 17, Andreev as modified using Hutton and Abdelaziz teaches all the limitations of claim 16 as stated above.
Andreev does not explicitly teach wherein the at least one of the plurality of arithmetic blocks comprises a monolithic shift/sum block.
However, on the same field of endeavor, Abdelaziz discloses an arithmetic block that comprises a shift/sum block (Abdelaziz Fig. 2 and paragraph [0034] shift/sum block – section 205 and 206 in each block 2010-210N).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev in view of Hutton using Abdelaziz and configure the at least one arithmetic block to include a shift/sum block in order to implement floating-point dot-product operations using the shift/add block to for aligning the product values output by each multiplier prior to addition (Abdelaziz paragraphs [0035-0036]).
Therefore, the combination of Andreev as modified in view of Hutton and Abdelaziz teaches wherein the at least one of the plurality of arithmetic blocks comprises a monolithic shift/sum block.
Regarding claim 18, Andreev as modified using Hutton and Abdelaziz teaches all the limitations of claim 17 as stated above.
Andreev does not explicitly teach wherein the at least one of the plurality of arithmetic blocks comprises a monolithic adder tree.
However, on the same field of endeavor, Abdelaziz discloses an arithmetic block that comprises an adder tree (Abdelaziz Fig. 2 and paragraphs [0029, 0031 and 0037] adder tree – adder tree 202).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev in view of Hutton using Abdelaziz and configure the at least one arithmetic block to include an adder tree for adding the aligned product values in order to implement floating-point dot-product operations (Abdelaziz paragraphs [0029 and 0037]).
Therefore, the combination of Andreev as modified in view of Hutton and Abdelaziz teaches wherein the at least one of the plurality of arithmetic blocks comprises a monolithic adder tree.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Andreev in view of Hutton as applied to claim 15 above, and further in view of Boswell.
Regarding claim 19, Andreev as modified using Hutton teaches all the limitations of claim 15 as stated above.
Andreev does not explicitly teach wherein the at least one of the plurality of arithmetic blocks comprises a monolithic multiplier that multiplies FP64 or wider data.
However, on the same field of endeavor, Boswell discloses an arithmetic block that comprises a multiplier that multiplies FP64 data (Boswell Fig. 10 and paragraphs [0112-0113] multiplier – multiplier 1010).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev in view of Hutton using Boswell and configure at least one arithmetic block to include a multiplier that multiplier FP64 or wider data in order to implement double-precision floating-point FMA operations in combination with the adders (Boswell paragraph [0112]).
Therefore, the combination of Andreev as modified in view of Hutton and Boswell teaches wherein the at least one of the plurality of arithmetic blocks comprises a monolithic multiplier that multiplies FP64 or wider data.
Regarding claim 20, Andreev as modified in view of Hutton teaches all the limitations of claim 15 as stated above.
Andreev does not explicitly teach wherein the at least one of the plurality of arithmetic blocks comprises a monolithic adder that adds FP64 or wider data.
However, on the same field of endeavor, Boswell discloses an arithmetic block that comprises an adder that adds FP64 or wider data (Boswell Fig. 10 and paragraphs [0113-0115] adder – 3:2 CSA 1040 and/or completion adder 1050).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Andreev in view of Hutton using Boswell and configure at least one arithmetic block to include an adder for adding FP64 or wider data in order to support double-precision floating point addition (Boswell paragraphs [0113-0115]).
Therefore, the combination of Andreev as modified in view of Hutton and Boswell teaches wherein the at least one of the plurality of arithmetic blocks comprises a monolithic adder that adds FP64 or wider data.
Allowable Subject Matter
Claims 3, 5 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if rewritten to overcome the 35 U.S.C. 112(b) rejections discussed above.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, wherein the via-configured structured logic circuitry comprises a via-configured feedback path that couples an output of the embedded arithmetic block with an input of the embedded arithmetic block as recited in claim 3; wherein the embedded arithmetic block comprises a pre-adder to perform an addition function on data prior to multiplication by the multiplier as recited in claim 5; wherein the via-configured structured logic circuitry comprises structured logic circuitry that has been via-configured to form a post-adder to perform an addition function using outputs of the multiplier as recited in claim 8; and wherein the embedded arithmetic block comprises via-configured control circuitry that controls an operation of the plurality of monolithic arithmetic circuits as recited in claim 9.
Andreev is the closest prior art found. Andreev discloses a Structured ASIC comprising a logic unit block module array 203 and memory cells 110 comprising of Block RAM (BRAM). The logic unit block module array 203 comprises a tiled (squared) pattern of logic cells 105 with each tiled logic cell having via-configurable logic block (VCLB) using transistors that are connected by vias for implementing sequential or combinational circuits and full adders adjacent to each tiled logic cell used for addition and complex multiplication. However, Andreev fails to explicitly teach or suggest the logic cells 105 comprises a via-configured feedback path that couples an output of the full adders with an input of the full adders as required in claim 3; wherein the adders perform an addition function on data prior to multiplication by a multiplier as required in claim 5; wherein the logic cells 105 comprises structured logic circuitry that has been via-configured to form a post-adder to perform an addition function using outputs of a multiplier as required in claim 8; and wherein the full adders comprises via-configured control circuitry that controls an operation of the full adders as required in claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ran et al. (NPL – “The Magic of a Via-Configurable Regular Fabric”) discloses various arithmetic circuits (adders and multipliers) implementation in a via-configurable gate array (VCGA) (Structured-ASIC).
Deering (US 4754412 A) discloses an arithmetic logic system comprising a plurality of arithmetic logic units and a control unit is coupled to the plurality of arithmetic logic units to control operation of the plurality of arithmetic logic units.
Visishta et al. (US 20160124899 A1) and Chuang et al. (US 20150270214 A1) are generally related to a via-configurable logic device.
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/Carlo Waje/Examiner, Art Unit 2182 (571)272-5767