DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 March 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16, and 18-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 10,606,003 to Peterson et al in view of U.S. Patent Application Publication 2020/0271873 to Chang et al.
In regards to claims 1, 15, and 22, Peterson recites a package/method (Figure 2) comprising: a photonic integrated circuit (PIC) (203); an electronic integrated circuit (EIC) (205) electrically and physically coupled with the PIC; an optical coupling connector (OCC) (213) physically and optically coupled with the PIC, the OCC laterally spaced apart from the EIC along a same horizontal plane, and the OCC and the EIC vertically over and attached directly to the PIC; and wherein the PIC, EIC, and OCC are in a mold [0044]. But Peterson fails to expressly recite the mold having an uppermost surface at a same level as an uppermost surface of the EIC and at a same level as an uppermost surface of the OCC. However, Chang teaches a photonic integrated circuit (Figures 3 & 4) comprising a PIC and EIC along the same horizontal plane. Chang further teaches an insulating encapsulation layer (100’), where the insulating encapsulation laterally encapsulates the PIC and EIC, the top surface of the substantially level. [0026] Therefore, it would have been obvious before the effective filing date to a person having ordinary skill in the art for the mold having an uppermost surface at a same level as an uppermost surface of the EIC and at a same level as an uppermost surface of the OCC in order to allow for the planar formation additional layers, such as an RDL layer.
In regards to claim 2, Peterson teaches the OCC and the PIC are optically coupled with one or more lenses (211).
In regards to claim 3, Peterson recites the PIC includes an optical coupler, and wherein the OCC includes one or more optical waveguides (232) that optically couple with the optical coupler of the PIC. (Column 6)
In regards to claim 4, although Peterson in view of Chang does not expressly recite the one or more optical waveguides of the OCC terminate at a side of the OCC that is perpendicular to the side of the PIC, it has been held that rearranging parts of an invention involves only routine skill in the art. Since the placement of components in the fashion as claimed would be advantageous in order to reduce the size of the device, it would have been obvious before the effective filing date to a person having ordinary skill in the art for the one or more optical waveguides of the OCC terminate at a side of the OCC that is perpendicular to the side of the PIC.
In regards to claims 5 and 7, Peterson recites a cap (1201; Figure 12) at the side of the OCC that covers the one or more optical waveguides.
In regards to claim 6, Peterson recites the one or more optical waveguides of the OCC terminate at a top of the OCC that is parallel to the side of the PIC. (Figure 3A & 3B)
In regards to claim 8, although Peterson in view of Chang does not expressly teach the OCC is optically coupled the PIC through evanescent coupling, evanescent coupling between two waveguides/optical components is a known alternative coupling method. Evanescent coupling would allow the signal to couple between the desired waveguides without the need for an additional coupler. Therefore, it would have been obvious before the effective filing date to a person having ordinary skill in the art to have provided the OCC is optically coupled the PIC through evanescent coupling.
In regards to claim 9, Peterson recites the PIC has a first side and a second side opposite the first side, wherein the EIC and the OCC are coupled with the first side of the PIC.
In regards to claim 10, Peterson recites the second side of the PIC includes electrical and physical couplings.
In regards to claim 11, Peterson recites the PIC is electrically coupled with the EIC with one or more electrical routing layers (360).
In regards to claim 12, Peterson recites the one or more electrical routing layers include copper. [0048]
In regards to claim 13, although Peterson in view of Chang does not expressly recite the OCC and the PIC include physical alignment features, aligning optical components in order to achieve improved efficiency is a common technique in the optical art. Chang also teaches the need for alignment of optical components by use of a pick and place tool. [0022] Furthermore, the use of physical alignment features is a well known concept to align optical components in order to reduce signal loss. Therefore, it would have been obvious before the effective filing date to a person having ordinary skill in the art for the OCC and the PIC include physical alignment features.
In regards to claims 14 and 25, although Peterson in view of Chang does not expressly teach the mold is an epoxy compound, epoxy is well known molding material in the art. Epoxy is inexpensive, readily available and easy to mold. Since epoxy is a known material for molding, it would have been obvious before the effective filing date to a person having ordinary skill in the art for the mold to be epoxy.
In regards to claim 16, Peterson recites coupling the EIC with the side of the PIC further includes electrically coupling the EIC with the PIC.
In regards to claim 18, Peterson teaches coupling the OCC further includes optically coupling one or more optical waveguides in the OCC to one or more optical couplers in the PIC.
In regards to claims 19-21, although Peterson in view of Chang does not expressly recite prior to coupling the OCC with the side of the PIC, placing cap on a side of the OCC proximate to a termination of the one or more optical waveguides in the OCC, subsequent to coupling the OCC with the side of the PIC, removing the cap and wherein the PIC, the EIC, and the OCC are on a wafer; and wherein removing the cap further includes a selected one of: dicing the wafer or grinding the cap, the cap would necessarily be removed in order for the coupling of the components to occur. Additionally, dicing of the wafter or grinding the cap are known methods of removing optical layers. Furthermore, Applicant has not disclosed dicing or grinding to solve a stated problem or one method to have an advantageous over the other and it appears either method of removal would result in the same outcome. Therefore, it would have been obvious before the effective filing date to a person having ordinary skill in the art that prior to coupling the OCC with the side of the PIC, placing cap on a side of the OCC proximate to a termination of the one or more optical waveguides in the OCC, subsequent to coupling the OCC with the side of the PIC, removing the cap and wherein the PIC, the EIC, and the OCC are on a wafer; and wherein removing the cap further includes a selected one of: dicing the wafer or grinding the cap.
In regards to claim 23, Peterson recites one or more dies electrically and physically coupled with the substrate.
In regards to claim 24, Peterson recites the one or more dies include a selected one or more of: a CPU, GPU, memory, or application-specific integrated circuit (ASIC), Artificial Intelligence Chips, Accelerators, SERDES.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 10,606,003 to Peterson et al in view of U.S. Patent Application Publication 2020/0271873 to Chang et al as applied to claim 15 above and in further view of U.S. Patent Application Publication 2021/0088722 to Razdan et al.
Peterson and Chang both teach the side of the PIC is a first side and further including a second side opposite the first side. Although neither Peterson or Chang teach the second side further including one or more electrically conductive vias extending from the first side of the PIC to the second side of the PIC, wherein the EIC is electrically coupled with the one or more electrically conductive vias, Chang teaches electrical connections through RDL layers with solder bumps, metal pillars and ball grid arrays [0033]. Furthermore, Razdan teaches a similar device including a PIC (410), EIC (220) and OCC (120) and further teaches an electrical connection through solder bumps (250) in Figure 2. Similar to connection pads, solder bumps provide the desired electrical connection between the two components. Razdan further teaches in Figure 4 electrical vias (440) as an alternative electrical coupling component to the solder connections of Figure 2. Since solder bumps, connection pads and electrical vias are all known alternatives as evidenced by the various configurations and embodiments of Razdan, it would have been obvious before the effective filing date to a person having ordinary skill in the art to have provided the second side further including one or more electrically conductive vias extending from the first side of the PIC to the second side of the PIC, wherein the EIC is electrically coupled with the one or more electrically conductive vias.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TINA M WONG whose telephone number is (571)272-2352. The examiner can normally be reached M-F 8:30-5:30.
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/TINA WONG/Primary Examiner, Art Unit 2874
